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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [_xmsgs/] [xst.xmsgs] - Blame information for rev 33

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Line No. Rev Author Line
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Unit work/INTERCON_P2P is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd".
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Unit work/INTERCON_P2P/Behavioral is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd".
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Unit work/SERIALMASTER is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/SERIALMASTER.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd".
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Unit work/SERIALMASTER/Behavioral is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/SERIALMASTER.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd".
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Unit work/SYC0001a is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/SYC0001a.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd".
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Unit work/SYC0001a/SYC0001a1 is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/SYC0001a.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/SYC0001a.vhd".
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Unit work/uart_wishbone_slave is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd".
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Unit work/uart_wishbone_slave/Behavioral is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd".
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Unit work/uart_communication_blocks is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd".
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Unit work/uart_communication_blocks/Behavioral is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd".
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Unit work/uart_control is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/uart_control.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd".
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Unit work/uart_control/Behavioral is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/uart_control.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd".
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Unit work/baud_generator is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/baud_generator.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd".
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Unit work/baud_generator/Behavioral is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/baud_generator.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd".
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Unit work/divisor is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/divisor.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd".
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Unit work/divisor/Behavioral is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/divisor.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd".
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Unit work/serial_receiver is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/serial_receiver.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd".
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Unit work/serial_receiver/Behavioral is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/serial_receiver.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd".
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Unit work/serial_transmitter is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/serial_transmitter.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd".
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Unit work/serial_transmitter/Behavioral is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/serial_transmitter.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd".
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Unit work/pkgDefinitions is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd".
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Unit work/pkgDefinitions is now defined in a different file.  It was defined in "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd", and is now defined in "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd".
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"/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'CYC_O' of component 'SERIALMASTER'.
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"/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 80: Unconnected output port 'SEL_O' of component 'SERIALMASTER'.
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"/home/laraujo/work/uart_block/hdl/iseProject/INTERCON_P2P.vhd" line 95: Unconnected output port 'data_Avaible' of component 'uart_wishbone_slave'.
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"/home/laraujo/work/uart_block/hdl/iseProject/SERIALMASTER.vhd" line 46: Width mismatch. <byteIncome> has a width of 8 bits but assigned expression is 32-bit wide.
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"/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" line 62: Unconnected output port 'reminder' of component 'divisor'.
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Input <DAT_I<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Output <CYC_O> is never assigned. Tied to value 0.
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Output <SEL_O> is never assigned. Tied to value 0.
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Output <data_avaible> is never assigned.
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The FF/Latch <cycle_wait_oversample_24> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_23>
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The FF/Latch <cycle_wait_oversample_7> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_6>
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107 32 leonardoar 
The FF/Latch <cycle_wait_oversample_19> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_18>
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The FF/Latch <cycle_wait_oversample_20> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_19>
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The FF/Latch <cycle_wait_oversample_15> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_14>
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The FF/Latch <cycle_wait_oversample_0> in Unit <uBaudGen> is equivalent to the following FF/Latch, which will be removed : <half_cycle_1>
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The FF/Latch <cycle_wait_oversample_29> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_28>
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The FF/Latch <cycle_wait_oversample_3> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_2>
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The FF/Latch <cycle_wait_oversample_27> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_26>
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The FF/Latch <cycle_wait_oversample_23> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_22>
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The FF/Latch <cycle_wait_oversample_8> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_7>
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The FF/Latch <cycle_wait_oversample_5> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_4>
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137 32 leonardoar 
The FF/Latch <cycle_wait_oversample_18> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_17>
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140 32 leonardoar 
The FF/Latch <cycle_wait_oversample_14> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_13>
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The FF/Latch <cycle_wait_oversample_28> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_27>
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146 32 leonardoar 
The FF/Latch <cycle_wait_oversample_26> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_25>
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149 32 leonardoar 
The FF/Latch <cycle_wait_oversample_1> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <half_cycle0_0>
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152 32 leonardoar 
The FF/Latch <cycle_wait_oversample_22> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_21>
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155 32 leonardoar 
The FF/Latch <cycle_wait_oversample_17> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_16>
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158 32 leonardoar 
The FF/Latch <cycle_wait_oversample_31> in Unit <uBaudGen> is equivalent to the following 5 FFs/Latches, which will be removed : <cycle_wait_oversample_30> <half_cycle_31> <half_cycle0_31> <half_cycle0_30> <half_cycle0_29>
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161 32 leonardoar 
The FF/Latch <cycle_wait_oversample_13> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_12>
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164 32 leonardoar 
The FF/Latch <cycle_wait_oversample_9> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_8>
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167 32 leonardoar 
The FF/Latch <cycle_wait_oversample_6> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_5>
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The FF/Latch <cycle_wait_oversample_11> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_10>
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173 32 leonardoar 
The FF/Latch <cycle_wait_oversample_25> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_24>
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176 32 leonardoar 
The FF/Latch <cycle_wait_oversample_21> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_20>
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179 32 leonardoar 
The FF/Latch <cycle_wait_oversample_16> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_15>
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182 32 leonardoar 
The FF/Latch <cycle_wait_oversample_2> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_1>
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185 32 leonardoar 
The FF/Latch <cycle_wait_oversample_12> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_11>
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188 32 leonardoar 
The FF/Latch <cycle_wait_oversample_10> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_9>
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191 32 leonardoar 
The FF/Latch <cycle_wait_oversample_4> in Unit <uBaudGen> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_3>
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194 32 leonardoar 
FF/Latch <N_24> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
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197 32 leonardoar 
FF/Latch <N_18> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
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200 32 leonardoar 
FF/Latch <N_11> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
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203 32 leonardoar 
FF/Latch <N_10> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
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206 32 leonardoar 
FF/Latch <N_8> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
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209 32 leonardoar 
FF/Latch <config_clk_8> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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212 32 leonardoar 
FF/Latch <config_clk_10> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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215 32 leonardoar 
FF/Latch <config_clk_11> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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218 32 leonardoar 
FF/Latch <config_clk_18> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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221 32 leonardoar 
FF/Latch <config_clk_24> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
222
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224 32 leonardoar 
FF/Latch <config_clk_26> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
225
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227 32 leonardoar 
FF/Latch <config_clk_27> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
228
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230 32 leonardoar 
FF/Latch <config_clk_28> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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233 32 leonardoar 
FF/Latch <config_clk_29> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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236 32 leonardoar 
FF/Latch <config_clk_30> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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239 32 leonardoar 
FF/Latch <config_clk_31> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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242 32 leonardoar 
FF/Latch <config_baud_8> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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245 32 leonardoar 
FF/Latch <config_baud_10> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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248 32 leonardoar 
FF/Latch <config_baud_11> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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251 32 leonardoar 
FF/Latch <config_baud_18> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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254 32 leonardoar 
FF/Latch <config_baud_24> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
255
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257 32 leonardoar 
FF/Latch <config_baud_26> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
258
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260 32 leonardoar 
FF/Latch <config_baud_27> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
261
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263 32 leonardoar 
FF/Latch <config_baud_28> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
264
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266 32 leonardoar 
FF/Latch <config_baud_29> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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269 32 leonardoar 
FF/Latch <config_baud_30> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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272 32 leonardoar 
FF/Latch <config_baud_31> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
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275 32 leonardoar 
FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <uBaudGen>. This FF/Latch will be trimmed during the optimization process.
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278 32 leonardoar 
FF/Latch <DAT_O_8> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
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281 32 leonardoar 
FF/Latch <DAT_O_10> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
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284 32 leonardoar 
FF/Latch <DAT_O_11> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
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287 32 leonardoar 
FF/Latch <DAT_O_18> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
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290 32 leonardoar 
FF/Latch <DAT_O_24> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
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293 32 leonardoar 
FF/Latch <DAT_O_26> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
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296 32 leonardoar 
FF/Latch <DAT_O_27> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
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299 32 leonardoar 
FF/Latch <DAT_O_28> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
300
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302 32 leonardoar 
FF/Latch <DAT_O_29> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
303
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305 32 leonardoar 
FF/Latch <DAT_O_30> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
306
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308 32 leonardoar 
FF/Latch <DAT_O_31> (without init value) has a constant value of 0 in block <uMasterSerial>. This FF/Latch will be trimmed during the optimization process.
309
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311 32 leonardoar 
FF/Latch <D_31> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
312
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314 32 leonardoar 
FF/Latch <D_28> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
315
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317 32 leonardoar 
FF/Latch <D_30> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
318
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320 32 leonardoar 
FF/Latch <N_27> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
321
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323 32 leonardoar 
FF/Latch <N_28> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
324
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326 32 leonardoar 
FF/Latch <N_26> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
327
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329 32 leonardoar 
FF/Latch <N_29> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
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331 27 leonardoar 
 
332 32 leonardoar 
FF/Latch <N_30> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
333
334 27 leonardoar 
 
335 32 leonardoar 
FF/Latch <N_31> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
336
337 27 leonardoar 
 
338 32 leonardoar 
FF/Latch <D_8> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
339
340 27 leonardoar 
 
341 32 leonardoar 
FF/Latch <D_29> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
342
343 27 leonardoar 
 
344 32 leonardoar 
FF/Latch <D_27> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
345
346 27 leonardoar 
 
347 32 leonardoar 
FF/Latch <D_26> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
348
349 27 leonardoar 
 
350 32 leonardoar 
FF/Latch <D_10> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
351
352 27 leonardoar 
 
353 32 leonardoar 
FF/Latch <D_11> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
354
355 27 leonardoar 
 
356 32 leonardoar 
FF/Latch <D_24> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
357
358 27 leonardoar 
 
359 32 leonardoar 
FF/Latch <D_18> (without init value) has a constant value of 0 in block <uDiv>. This FF/Latch will be trimmed during the optimization process.
360
361 27 leonardoar 
 
362 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_31> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
363
364 27 leonardoar 
 
365 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_30> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
366
367 27 leonardoar 
 
368 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_29> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
369
370 27 leonardoar 
 
371 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_28> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
372
373 27 leonardoar 
 
374 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_27> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
375
376 27 leonardoar 
 
377 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_26> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
378
379 27 leonardoar 
 
380 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_24> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
381
382 27 leonardoar 
 
383 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_18> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
384
385 27 leonardoar 
 
386 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_11> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
387
388 27 leonardoar 
 
389 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_10> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
390
391 27 leonardoar 
 
392 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivDividend_8> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
393
394 27 leonardoar 
 
395 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_31> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
396
397 27 leonardoar 
 
398 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_30> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
399
400 27 leonardoar 
 
401 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_29> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
402
403 27 leonardoar 
 
404 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_28> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
405
406 27 leonardoar 
 
407 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_27> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
408
409 27 leonardoar 
 
410 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_26> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
411
412 27 leonardoar 
 
413 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_24> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
414
415 27 leonardoar 
 
416 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_18> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
417
418 27 leonardoar 
 
419 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_11> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
420
421 27 leonardoar 
 
422 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_10> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
423
424 27 leonardoar 
 
425 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <sigDivNumerator_8> (without init value) has a constant value of 0 in block <uUartControl>. This FF/Latch will be trimmed during the optimization process.
426
427 27 leonardoar 
 
428 32 leonardoar 
FF/Latch <DAT_O_8> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
429
430 27 leonardoar 
 
431 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <DAT_O_10> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
432
433 27 leonardoar 
 
434 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <DAT_O_11> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
435
436 27 leonardoar 
 
437 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <DAT_O_18> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
438
439 27 leonardoar 
 
440 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <DAT_O_24> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
441
442 27 leonardoar 
 
443 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <DAT_O_26> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
444
445 27 leonardoar 
 
446 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <DAT_O_27> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
447
448 27 leonardoar 
 
449 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <DAT_O_28> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
450
451 27 leonardoar 
 
452 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <DAT_O_29> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
453
454 27 leonardoar 
 
455 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <DAT_O_30> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
456
457 27 leonardoar 
 
458 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <DAT_O_31> (without init value) has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
459
460 27 leonardoar 
 
461 32 leonardoar 
FF/Latch <cycle_wait_oversample_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
462
463 27 leonardoar 
 
464 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <cycle_wait_oversample_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
465
466 27 leonardoar 
 
467 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <half_cycle_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
468
469 27 leonardoar 
 
470 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <half_cycle0_31> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
471
472 27 leonardoar 
 
473 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <half_cycle0_30> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
474
475 27 leonardoar 
 
476 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <half_cycle0_29> (without init value) has a constant value of 0 in block <baud_generator>. This FF/Latch will be trimmed during the optimization process.
477
478 27 leonardoar 
 
479 32 leonardoar 
The FF/Latch <cycle_wait_oversample_24> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_25> <half_cycle0_23>
480
481 27 leonardoar 
 
482 32 leonardoar 
The FF/Latch <cycle_wait_oversample_7> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_8> <half_cycle0_6>
483
484 27 leonardoar 
 
485 32 leonardoar 
The FF/Latch <cycle_wait_oversample_19> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_20> <half_cycle0_18>
486
487 27 leonardoar 
 
488 32 leonardoar 
The FF/Latch <cycle_wait_oversample_20> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_21> <half_cycle0_19>
489
490 27 leonardoar 
 
491 32 leonardoar 
The FF/Latch <cycle_wait_oversample_15> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_16> <half_cycle0_14>
492
493 27 leonardoar 
 
494 32 leonardoar 
The FF/Latch <cycle_wait_oversample_0> in Unit <baud_generator> is equivalent to the following FF/Latch, which will be removed : <half_cycle_1>
495
496 27 leonardoar 
 
497 32 leonardoar 
The FF/Latch <cycle_wait_oversample_29> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_30> <half_cycle0_28>
498
499 27 leonardoar 
 
500 32 leonardoar 
The FF/Latch <cycle_wait_oversample_3> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_4> <half_cycle0_2>
501
502 27 leonardoar 
 
503 32 leonardoar 
The FF/Latch <cycle_wait_oversample_27> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_28> <half_cycle0_26>
504
505 27 leonardoar 
 
506 32 leonardoar 
The FF/Latch <cycle_wait_oversample_23> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_24> <half_cycle0_22>
507
508 28 leonardoar 
 
509 32 leonardoar 
The FF/Latch <cycle_wait_oversample_8> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_9> <half_cycle0_7>
510
511 28 leonardoar 
 
512 32 leonardoar 
The FF/Latch <cycle_wait_oversample_5> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_6> <half_cycle0_4>
513
514 28 leonardoar 
 
515 32 leonardoar 
The FF/Latch <cycle_wait_oversample_18> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_19> <half_cycle0_17>
516
517 28 leonardoar 
 
518 32 leonardoar 
The FF/Latch <cycle_wait_oversample_14> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_15> <half_cycle0_13>
519
520 28 leonardoar 
 
521 32 leonardoar 
The FF/Latch <cycle_wait_oversample_28> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_29> <half_cycle0_27>
522
523 28 leonardoar 
 
524 32 leonardoar 
The FF/Latch <cycle_wait_oversample_26> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_27> <half_cycle0_25>
525
526 28 leonardoar 
 
527 32 leonardoar 
The FF/Latch <cycle_wait_oversample_1> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_2> <half_cycle0_0>
528
529 27 leonardoar 
 
530 32 leonardoar 
The FF/Latch <cycle_wait_oversample_22> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_23> <half_cycle0_21>
531
532 27 leonardoar 
 
533 32 leonardoar 
The FF/Latch <cycle_wait_oversample_17> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_18> <half_cycle0_16>
534
535 27 leonardoar 
 
536 32 leonardoar 
The FF/Latch <cycle_wait_oversample_13> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_14> <half_cycle0_12>
537
538 27 leonardoar 
 
539 32 leonardoar 
The FF/Latch <cycle_wait_oversample_9> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_10> <half_cycle0_8>
540
541 27 leonardoar 
 
542 32 leonardoar 
The FF/Latch <cycle_wait_oversample_6> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_7> <half_cycle0_5>
543
544 27 leonardoar 
 
545 32 leonardoar 
The FF/Latch <cycle_wait_oversample_11> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_12> <half_cycle0_10>
546
547 27 leonardoar 
 
548 32 leonardoar 
The FF/Latch <cycle_wait_oversample_25> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_26> <half_cycle0_24>
549
550 27 leonardoar 
 
551 32 leonardoar 
The FF/Latch <cycle_wait_oversample_21> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_22> <half_cycle0_20>
552
553 27 leonardoar 
 
554 32 leonardoar 
The FF/Latch <cycle_wait_oversample_16> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_17> <half_cycle0_15>
555
556 27 leonardoar 
 
557 32 leonardoar 
The FF/Latch <cycle_wait_oversample_2> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_3> <half_cycle0_1>
558
559 27 leonardoar 
 
560 32 leonardoar 
The FF/Latch <cycle_wait_oversample_12> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_13> <half_cycle0_11>
561
562 27 leonardoar 
 
563 32 leonardoar 
The FF/Latch <cycle_wait_oversample_10> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_11> <half_cycle0_9>
564
565 27 leonardoar 
 
566 32 leonardoar 
The FF/Latch <cycle_wait_oversample_4> in Unit <baud_generator> is equivalent to the following 2 FFs/Latches, which will be removed : <half_cycle_5> <half_cycle0_3>
567
568 27 leonardoar 
 
569 32 leonardoar 
FF/Latch <cycles2Wait_0> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
570
571 27 leonardoar 
 
572 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_1> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
573
574 27 leonardoar 
 
575 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_2> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
576
577 27 leonardoar 
 
578 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_3> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
579
580 27 leonardoar 
 
581 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_4> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
582
583 27 leonardoar 
 
584 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_5> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
585
586 27 leonardoar 
 
587 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <cycles2Wait_23> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
588
589 27 leonardoar 
 
590 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <nextState_1> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
591
592 27 leonardoar 
 
593 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <nextState_5> has a constant value of 0 in block <SERIALMASTER>. This FF/Latch will be trimmed during the optimization process.
594
595 27 leonardoar 
 
596 32 leonardoar 
The FF/Latch <current_s_FSM_FFd1> in Unit <serial_receiver> is equivalent to the following FF/Latch, which will be removed : <data_ready>
597
598 27 leonardoar 
 
599 32 leonardoar 
Unit uart_control: 32 internal tristates are replaced by logic (pull-up yes):
600 27 leonardoar 
 
601 32 leonardoar 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
602
603 27 leonardoar 
 
604 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
605
606 27 leonardoar 
 
607 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
608
609 27 leonardoar 
 
610 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
611
612 27 leonardoar 
 
613 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
614
615 27 leonardoar 
 
616 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
617
618 27 leonardoar 
 
619 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
620
621 27 leonardoar 
 
622 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
623
624 27 leonardoar 
 
625 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
626
627 27 leonardoar 
 
628 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
629
630 27 leonardoar 
 
631 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
632
633 27 leonardoar 
 
634 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
635
636 27 leonardoar 
 
637 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
638
639 27 leonardoar 
 
640 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
641
642 27 leonardoar 
 
643 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
644
645 27 leonardoar 
 
646 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
647
648 27 leonardoar 
 
649 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
650
651 27 leonardoar 
 
652 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
653
654 27 leonardoar 
 
655 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
656
657 27 leonardoar 
 
658 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
659
660 27 leonardoar 
 
661 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
662
663 27 leonardoar 
 
664 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
665
666 27 leonardoar 
 
667 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
668
669 27 leonardoar 
 
670 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
671
672 27 leonardoar 
 
673 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
674
675 27 leonardoar 
 
676 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
677
678 27 leonardoar 
 
679 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_clk_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
680
681 27 leonardoar 
 
682 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
683
684 27 leonardoar 
 
685 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
686
687 27 leonardoar 
 
688 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
689
690 27 leonardoar 
 
691 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
692
693 27 leonardoar 
 
694 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
695
696 27 leonardoar 
 
697 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/config_baud_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
698
699 27 leonardoar 
 
700 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
701
702 27 leonardoar 
 
703 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
704
705 27 leonardoar 
 
706 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
707
708 27 leonardoar 
 
709 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
710
711 27 leonardoar 
 
712 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
713
714 27 leonardoar 
 
715 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
716
717 27 leonardoar 
 
718 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
719
720 27 leonardoar 
 
721 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
722
723 27 leonardoar 
 
724 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
725
726 27 leonardoar 
 
727 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
728
729 27 leonardoar 
 
730 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivNumerator_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
731
732 27 leonardoar 
 
733 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
734
735 27 leonardoar 
 
736 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
737
738 27 leonardoar 
 
739 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
740
741 27 leonardoar 
 
742 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
743
744 27 leonardoar 
 
745 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
746
747 27 leonardoar 
 
748 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
749
750 27 leonardoar 
 
751 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
752
753 27 leonardoar 
 
754 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
755
756 27 leonardoar 
 
757 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
758
759 27 leonardoar 
 
760 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
761
762 27 leonardoar 
 
763 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/sigDivDividend_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
764
765 27 leonardoar 
 
766 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
767
768 27 leonardoar 
 
769 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
770
771 27 leonardoar 
 
772 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
773
774 27 leonardoar 
 
775 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
776
777 27 leonardoar 
 
778 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
779
780 27 leonardoar 
 
781 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
782
783 27 leonardoar 
 
784 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
785
786 27 leonardoar 
 
787 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
788
789 27 leonardoar 
 
790 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
791
792 27 leonardoar 
 
793 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
794
795 27 leonardoar 
 
796 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/D_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
797
798 27 leonardoar 
 
799 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
800
801 27 leonardoar 
 
802 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
803
804 27 leonardoar 
 
805 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
806
807 27 leonardoar 
 
808 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
809
810 27 leonardoar 
 
811 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
812
813 27 leonardoar 
 
814 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
815
816 27 leonardoar 
 
817 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
818
819 27 leonardoar 
 
820 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
821
822 27 leonardoar 
 
823 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
824
825 27 leonardoar 
 
826 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
827
828 27 leonardoar 
 
829 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/uDiv/N_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
830
831 27 leonardoar 
 
832 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/R_31> of sequential type is unconnected in block <INTERCON_P2P>.
833
834 27 leonardoar 
 
835 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_0> of sequential type is unconnected in block <INTERCON_P2P>.
836
837 27 leonardoar 
 
838 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_1> of sequential type is unconnected in block <INTERCON_P2P>.
839
840 27 leonardoar 
 
841 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_2> of sequential type is unconnected in block <INTERCON_P2P>.
842
843 27 leonardoar 
 
844 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_3> of sequential type is unconnected in block <INTERCON_P2P>.
845
846 27 leonardoar 
 
847 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_4> of sequential type is unconnected in block <INTERCON_P2P>.
848
849 27 leonardoar 
 
850 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_5> of sequential type is unconnected in block <INTERCON_P2P>.
851
852 27 leonardoar 
 
853 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_6> of sequential type is unconnected in block <INTERCON_P2P>.
854
855 27 leonardoar 
 
856 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_7> of sequential type is unconnected in block <INTERCON_P2P>.
857
858 27 leonardoar 
 
859 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_8> of sequential type is unconnected in block <INTERCON_P2P>.
860
861 27 leonardoar 
 
862 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_9> of sequential type is unconnected in block <INTERCON_P2P>.
863
864 27 leonardoar 
 
865 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_10> of sequential type is unconnected in block <INTERCON_P2P>.
866
867 27 leonardoar 
 
868 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_11> of sequential type is unconnected in block <INTERCON_P2P>.
869
870 27 leonardoar 
 
871 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_12> of sequential type is unconnected in block <INTERCON_P2P>.
872
873 27 leonardoar 
 
874 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_13> of sequential type is unconnected in block <INTERCON_P2P>.
875
876 27 leonardoar 
 
877 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_14> of sequential type is unconnected in block <INTERCON_P2P>.
878
879 27 leonardoar 
 
880 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_15> of sequential type is unconnected in block <INTERCON_P2P>.
881
882 27 leonardoar 
 
883 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_16> of sequential type is unconnected in block <INTERCON_P2P>.
884
885 27 leonardoar 
 
886 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_17> of sequential type is unconnected in block <INTERCON_P2P>.
887
888 27 leonardoar 
 
889 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_18> of sequential type is unconnected in block <INTERCON_P2P>.
890
891 27 leonardoar 
 
892 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_19> of sequential type is unconnected in block <INTERCON_P2P>.
893
894 27 leonardoar 
 
895 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_20> of sequential type is unconnected in block <INTERCON_P2P>.
896
897 27 leonardoar 
 
898 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_21> of sequential type is unconnected in block <INTERCON_P2P>.
899
900 27 leonardoar 
 
901 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_22> of sequential type is unconnected in block <INTERCON_P2P>.
902
903 27 leonardoar 
 
904 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_23> of sequential type is unconnected in block <INTERCON_P2P>.
905
906 27 leonardoar 
 
907 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_24> of sequential type is unconnected in block <INTERCON_P2P>.
908
909 27 leonardoar 
 
910 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_25> of sequential type is unconnected in block <INTERCON_P2P>.
911
912 27 leonardoar 
 
913 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_26> of sequential type is unconnected in block <INTERCON_P2P>.
914
915 27 leonardoar 
 
916 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_27> of sequential type is unconnected in block <INTERCON_P2P>.
917
918 27 leonardoar 
 
919 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_28> of sequential type is unconnected in block <INTERCON_P2P>.
920
921 27 leonardoar 
 
922 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_29> of sequential type is unconnected in block <INTERCON_P2P>.
923
924 27 leonardoar 
 
925 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_30> of sequential type is unconnected in block <INTERCON_P2P>.
926
927 27 leonardoar 
 
928 32 leonardoar 
Node <uUartWishboneSlave/uUartControl/uDiv/reminder_31> of sequential type is unconnected in block <INTERCON_P2P>.
929
930 27 leonardoar 
 
931 32 leonardoar 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
932
933 27 leonardoar 
 
934 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
935
936 27 leonardoar 
 
937 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
938
939 27 leonardoar 
 
940 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
941
942 27 leonardoar 
 
943 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
944
945 27 leonardoar 
 
946 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
947
948 27 leonardoar 
 
949 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
950
951 27 leonardoar 
 
952 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
953
954 27 leonardoar 
 
955 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
956
957 27 leonardoar 
 
958 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
959
960 27 leonardoar 
 
961 32 leonardoar 
Due to other FF/Latch trimming, FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
962
963 27 leonardoar 
 
964 32 leonardoar 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
965
966 
 
967 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
968
969 
 
970 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
971
972 
 
973 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
974
975 
 
976 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
977
978 
 
979 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
980
981 
 
982 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
983
984 
 
985 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
986
987 
 
988 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
989
990 
 
991 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
992
993 
 
994 
FF/Latch <uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8> (without init value) has a constant value of 0 in block <INTERCON_P2P>. This FF/Latch will be trimmed during the optimization process.
995
996 
 
997 
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<11> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
998
999 
 
1000 
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<18> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
1001
1002 
 
1003 
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<24> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
1004
1005 
 
1006 
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<26> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
1007
1008 
 
1009 
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<27> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
1010
1011 
 
1012 
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<28> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
1013
1014 
 
1015 
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<29> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
1016
1017 
 
1018 
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<30> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
1019
1020 
 
1021 
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<31> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
1022
1023 
 
1024 
in unit INTERCON_P2P Conflict on KEEP property on signal uUartWishboneSlave/uUartControl/Mtridata_DAT_O<8> and uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10> signal will be lost.
1025
1026 
 
1027 
HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
1028
1029 
 
1030 21 leonardoar
1031 32 leonardoar 
 

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