1 |
6 |
leonardoar |
--! Baud generator
|
2 |
|
|
--! http://www.fpga4fun.com/SerialInterface.html
|
3 |
|
|
library ieee;
|
4 |
|
|
use ieee.std_logic_1164.all;
|
5 |
|
|
use ieee.std_logic_unsigned.all;
|
6 |
|
|
use ieee.std_logic_arith.all;
|
7 |
|
|
|
8 |
|
|
--! Use CPU Definitions package
|
9 |
|
|
use work.pkgDefinitions.all;
|
10 |
|
|
|
11 |
|
|
entity baud_generator is
|
12 |
|
|
Port ( rst : in STD_LOGIC;
|
13 |
|
|
clk : in STD_LOGIC;
|
14 |
|
|
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
|
15 |
11 |
leonardoar |
baud_oversample : out std_logic;
|
16 |
6 |
leonardoar |
baud : out STD_LOGIC);
|
17 |
|
|
end baud_generator;
|
18 |
|
|
|
19 |
|
|
architecture Behavioral of baud_generator is
|
20 |
|
|
signal genTick : std_logic;
|
21 |
11 |
leonardoar |
signal genTickOverSample : std_logic;
|
22 |
6 |
leonardoar |
begin
|
23 |
|
|
process (rst, clk)
|
24 |
|
|
variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
|
25 |
|
|
variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
|
26 |
|
|
begin
|
27 |
|
|
if rst = '1' then
|
28 |
|
|
wait_clk_cycles := (others => '0');
|
29 |
|
|
half_cycle := '0' & cycle_wait(cycle_wait'high downto 1);
|
30 |
|
|
genTick <= '0';
|
31 |
|
|
elsif rising_edge(clk) then
|
32 |
8 |
leonardoar |
-- Just decremented the cycle_wait by one because genTick would be updated on the next cycle
|
33 |
|
|
-- and we really want to bring genTick <= '1' when (wait_clk_cycles = cycle_wait)
|
34 |
|
|
if wait_clk_cycles = (cycle_wait - conv_std_logic_vector(1, (nBitsLarge-1))) then
|
35 |
6 |
leonardoar |
genTick <= '1';
|
36 |
|
|
wait_clk_cycles := (others => '0');
|
37 |
|
|
else
|
38 |
|
|
wait_clk_cycles := wait_clk_cycles + conv_std_logic_vector(1, (nBitsLarge-1));
|
39 |
|
|
-- If we're at half of the cycle
|
40 |
|
|
if wait_clk_cycles = half_cycle then
|
41 |
|
|
genTick <= '0';
|
42 |
|
|
end if;
|
43 |
|
|
end if;
|
44 |
|
|
end if;
|
45 |
|
|
end process;
|
46 |
|
|
|
47 |
|
|
baud <= genTick;
|
48 |
11 |
leonardoar |
baud_oversample <= genTickOverSample;
|
49 |
|
|
|
50 |
|
|
-- Process to generate the overclocked (8x) sample
|
51 |
|
|
process (rst, clk)
|
52 |
|
|
variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
|
53 |
|
|
variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
|
54 |
|
|
variable cycle_wait_oversample : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
|
55 |
|
|
begin
|
56 |
|
|
if rst = '1' then
|
57 |
|
|
wait_clk_cycles := (others => '0');
|
58 |
|
|
|
59 |
|
|
-- Divide cycle_wait by 8
|
60 |
|
|
cycle_wait_oversample := '0' & cycle_wait(cycle_wait'high downto 1);
|
61 |
|
|
cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
|
62 |
|
|
cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
|
63 |
|
|
|
64 |
|
|
-- Half of cycle_wait_oversample
|
65 |
|
|
half_cycle := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
|
66 |
|
|
genTickOverSample <= '0';
|
67 |
|
|
elsif rising_edge(clk) then
|
68 |
|
|
-- Just decremented the cycle_wait by one because genTick would be updated on the next cycle
|
69 |
|
|
-- and we really want to bring genTick <= '1' when (wait_clk_cycles = cycle_wait)
|
70 |
|
|
if wait_clk_cycles = (cycle_wait_oversample - conv_std_logic_vector(1, (nBitsLarge-1))) then
|
71 |
|
|
genTickOverSample <= '1';
|
72 |
|
|
wait_clk_cycles := (others => '0');
|
73 |
|
|
else
|
74 |
|
|
wait_clk_cycles := wait_clk_cycles + conv_std_logic_vector(1, (nBitsLarge-1));
|
75 |
|
|
-- If we're at half of the cycle
|
76 |
|
|
if wait_clk_cycles = half_cycle then
|
77 |
|
|
genTickOverSample <= '0';
|
78 |
|
|
end if;
|
79 |
|
|
end if;
|
80 |
|
|
end if;
|
81 |
|
|
end process;
|
82 |
6 |
leonardoar |
|
83 |
|
|
end Behavioral;
|
84 |
|
|
|