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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [baud_generator.vhd] - Blame information for rev 31

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1 6 leonardoar
--! Baud generator
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--! http://www.fpga4fun.com/SerialInterface.html
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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entity baud_generator is
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    Port ( rst : in STD_LOGIC;
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                          clk : in  STD_LOGIC;
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           cycle_wait : in  STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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                          baud_oversample : out std_logic;
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           baud : out  STD_LOGIC);
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end baud_generator;
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architecture Behavioral of baud_generator is
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signal genTick : std_logic;
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signal genTickOverSample : std_logic;
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begin
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        process (rst, clk, cycle_wait)
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        variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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        variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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        begin
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                if rst = '1' then
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                        wait_clk_cycles := (others => '0');
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                        half_cycle := '0' & cycle_wait(cycle_wait'high downto 1);
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                        genTick <= '0';
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                elsif rising_edge(clk) then
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                        -- Just decremented the cycle_wait by one because genTick would be updated on the next cycle
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                        -- and we really want to bring genTick <= '1' when (wait_clk_cycles = cycle_wait)
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                        if wait_clk_cycles = (cycle_wait - conv_std_logic_vector(1, nBitsLarge)) then
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                                genTick <= '1';
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                                wait_clk_cycles := (others => '0');
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                        else
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                                wait_clk_cycles := wait_clk_cycles + conv_std_logic_vector(1, nBitsLarge);
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                                -- If we're at half of the cycle
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                                if wait_clk_cycles = half_cycle then
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                                        genTick <= '0';
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                                end if;
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                        end if;
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                        -- Avoid creation of transparent latch (By default the VHDL will create an register for vectors that are assigned only in one
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                        -- ocasion of a (if, case) instruction
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                        half_cycle := '0' & cycle_wait(cycle_wait'high downto 1);
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                end if;
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        end process;
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        baud <= genTick;
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        baud_oversample <= genTickOverSample;
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        -- Process to generate the overclocked (8x) sample
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        process (rst, clk, cycle_wait)
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        variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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        variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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        variable cycle_wait_oversample : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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        begin
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                if rst = '1' then
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                        wait_clk_cycles := (others => '0');
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                        -- Divide cycle_wait by 4
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                        --cycle_wait_oversample := '0' & cycle_wait(cycle_wait'high downto 1);                  
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                        --cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
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                        cycle_wait_oversample := "00" & cycle_wait(cycle_wait'high downto 2);   -- Shift right by 2                     
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                        -- Half of cycle_wait_oversample
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                        half_cycle := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1); -- Shift right by 1
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                        genTickOverSample <= '0';
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                elsif rising_edge(clk) then
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                        -- Just decremented the cycle_wait by one because genTick would be updated on the next cycle
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                        -- and we really want to bring genTick <= '1' when (wait_clk_cycles = cycle_wait)
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                        if wait_clk_cycles = (cycle_wait_oversample - conv_std_logic_vector(1, nBitsLarge)) then
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                                genTickOverSample <= '1';
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                                wait_clk_cycles := (others => '0');
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                        else
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                                wait_clk_cycles := wait_clk_cycles + conv_std_logic_vector(1, nBitsLarge);
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                                -- If we're at half of the cycle
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                                if wait_clk_cycles = half_cycle then
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                                        genTickOverSample <= '0';
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                                end if;
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                        end if;
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                        -- Avoid creation of transparent latch (By default the VHDL will create an register for vectors that are assigned only in one
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                        -- ocasion of a (if, case) instruction
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                        cycle_wait_oversample := "00" & cycle_wait(cycle_wait'high downto 2);
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                        half_cycle := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
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                end if;
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        end process;
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end Behavioral;
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