Subversion Repositories uart_block

#ChipScope Core Inserter Project File Version 3.0

#Fri May 04 02:43:15 CEST 2012

Project.device.designInputFile=E\:\\uart_block\\hdl\\iseProject\\INTERCON_P2P_cs.ngc

Project.device.designOutputFile=E\:\\uart_block\\hdl\\iseProject\\INTERCON_P2P_cs.ngc

Project.device.deviceFamily=13

Project.device.enableRPMs=true

Project.device.outputDirectory=E\:\\uart_block\\hdl\\iseProject\\_ngo

Project.device.useSRL16=true

Project.filter.dimension=12

Project.filter<0>=*genTick*

Project.filter<10>=byte*

Project.filter<11>=byte

Project.filter<1>=*baud*

Project.filter<2>=*avai*

Project.filter<3>=*rx*

Project.filter<4>=

Project.filter<5>=*_OBUF*

Project.filter<6>=*_OBUF

Project.filter<7>=_OBUF

Project.filter<8>=*DAT_*

Project.filter<9>=*byte*

Project.icon.boundaryScanChain=1

Project.icon.enableExtTriggerIn=false

Project.icon.enableExtTriggerOut=false

Project.icon.triggerInPinName=

Project.icon.triggerOutPinName=

Project.unit.dimension=1

Project.unit<0>.clockChannel=uUartWishboneSlave/uUartCommunicationBlocks/uBaudGen/genTickOverSample

Project.unit<0>.clockEdge=Rising

Project.unit<0>.dataChannel<0>=rx_IBUF

Project.unit<0>.dataChannel<1>=uUartWishboneSlave/uUartCommunicationBlocks/uBaudGen/genTick

Project.unit<0>.dataChannel<2>=uUartWishboneSlave/uUartCommunicationBlocks/uBaudGen/genTickOverSample

Project.unit<0>.dataChannel<3>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<3>

Project.unit<0>.dataChannel<4>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<4>

Project.unit<0>.dataChannel<5>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<5>

Project.unit<0>.dataChannel<6>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<6>

Project.unit<0>.dataChannel<7>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<7>

Project.unit<0>.dataDepth=512

Project.unit<0>.dataEqualsTrigger=false

Project.unit<0>.dataPortWidth=3

Project.unit<0>.enableGaps=false

Project.unit<0>.enableStorageQualification=false

Project.unit<0>.enableTimestamps=false

Project.unit<0>.timestampDepth=0

Project.unit<0>.timestampWidth=0

Project.unit<0>.triggerChannel<0><0>=rx_IBUF

Project.unit<0>.triggerChannel<0><1>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<1>

Project.unit<0>.triggerChannel<0><2>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<2>

Project.unit<0>.triggerChannel<0><3>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<3>

Project.unit<0>.triggerChannel<0><4>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<4>

Project.unit<0>.triggerChannel<0><5>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<5>

Project.unit<0>.triggerChannel<0><6>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<6>

Project.unit<0>.triggerChannel<0><7>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<7>

Project.unit<0>.triggerConditionCountWidth=0

Project.unit<0>.triggerMatchCount<0>=1

Project.unit<0>.triggerMatchCountWidth<0><0>=0

Project.unit<0>.triggerMatchType<0><0>=0

Project.unit<0>.triggerPortCount=1

Project.unit<0>.triggerPortIsData<0>=true

Project.unit<0>.triggerPortWidth<0>=1

Project.unit<0>.triggerSequencerLevels=16

Project.unit<0>.triggerSequencerType=0

Project.unit<0>.type=ilapro