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leonardoar |
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj work.testUart_wishbone_slave
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ISim O.87xd (signature 0xc3576ebc)
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Number of CPUs detected in this system: 8
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Turning on mult-threading, number of parallel sub-compilation jobs: 16
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Determining compilation order of HDL files
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Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
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Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work
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Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
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Parsing VHDL file "E:/uart_block/hdl/iseProject/divisor.vhd" into library work
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Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work
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Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_control.vhd" into library work
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Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work
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WARNING:HDLCompiler:946 - "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 62: Actual for formal port rst is neither a static name nor a globally static expression
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Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work
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Parsing VHDL file "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work
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Starting static elaboration
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Completed static elaboration
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Compiling package standard
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Compiling package std_logic_1164
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Compiling package std_logic_arith
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Compiling package std_logic_unsigned
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Compiling package pkgdefinitions
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Compiling architecture behavioral of entity divisor [divisor_default]
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Compiling architecture behavioral of entity uart_control [uart_control_default]
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Compiling package numeric_std
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Compiling architecture behavioral of entity baud_generator [baud_generator_default]
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Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default]
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Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
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Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
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Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default]
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Compiling architecture behavior of entity testuart_wishbone_slave
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Time Resolution for simulation is 1ps.
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Waiting for 1 sub-compilation(s) to finish...
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Compiled 21 VHDL Units
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Built simulation executable E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe
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Fuse Memory Usage: 37428 KB
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Fuse CPU Usage: 420 ms
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