OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [iseconfig/] [iseProject.projectmgr] - Blame information for rev 27

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 25 leonardoar
2
3
4
5
6
7
8
9 
         2
10 
         /serial_transmitter - Behavioral E:|uart_block|hdl|iseProject|serial_transmitter.vhd
11
12
13 
         uart_wishbone_slave - Behavioral (/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd)
14
15 
      0
16 
      0
17 
      000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000306000000020000000000000000000000000200000064ffffffff000000810000000300000002000003060000000100000003000000000000000100000003
18 
      true
19 
      uart_wishbone_slave - Behavioral (/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd)
20
21
22
23 
         1
24 
         Configure Target Device
25 
         Design Utilities
26 
         Implement Design
27 
         User Constraints
28
29
30
31
32 
      0
33 
      0
34 
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000
35 
      false
36
37
38
39
40 
         1
41
42
43 
         pkgDefinitions.vhd
44
45 
      0
46 
      0
47 
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000157000000040101000100000000000000000000000064ffffffff000000810000000000000004000000690000000100000000000000240000000100000000000000660000000100000000000000640000000100000000
48 
      false
49 
      pkgDefinitions.vhd
50
51
52
53 
         1
54
55
56 
      0
57 
      0
58 
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000119000000010001000100000000000000000000000064ffffffff000000810000000000000001000001190000000100000000
59 
      false
60 
      work
61
62
63
64 
         1
65 
         Configure Target Device
66 
         Design Utilities
67 
         Implement Design
68 
         User Constraints
69
70
71
72
73 
      0
74 
      0
75 
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000
76 
      false
77
78
79
80
81 
         2
82 
         /testBaud_generator - behavior E:|uart_block|hdl|iseProject|testBaud_generator.vhd
83 
         /testBaud_generator - behavior |home|laraujo|work|uart_block|hdl|iseProject|testBaud_generator.vhd
84 
         /testDivisor - behavior E:|uart_block|hdl|iseProject|testDivisor.vhd
85 
         /testDivisor - behavior |home|laraujo|work|uart_block|hdl|iseProject|testDivisor.vhd
86 
         /testSerial_receiver - behavior E:|uart_block|hdl|iseProject|testSerial_receiver.vhd
87 
         /testSerial_receiver - behavior |home|laraujo|work|uart_block|hdl|iseProject|testSerial_receiver.vhd
88 
         /testSerial_transmitter - behavior E:|uart_block|hdl|iseProject|testSerial_transmitter.vhd
89 
         /testSerial_transmitter - behavior |home|laraujo|work|uart_block|hdl|iseProject|testSerial_transmitter.vhd
90 
         /testUart_communication_block - behavior E:|uart_block|hdl|iseProject|testUart_communication_block.vhd
91 
         /testUart_communication_block - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_communication_block.vhd
92 
         /testUart_control - behavior E:|uart_block|hdl|iseProject|testUart_control.vhd
93 
         /testUart_control - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_control.vhd/uut - uart_control - Behavioral
94 
         /testUart_wishbone_slave - behavior E:|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd
95 
         /testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd
96 
         /testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartCommunicationBlocks - uart_communication_blocks - Behavioral
97 
         /testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartControl - uart_control - Behavioral
98
99
100 
         testUart_wishbone_slave - behavior (/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd)
101
102 
      0
103 
      0
104 
      000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000024a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000024a0000000100000003000000000000000100000003
105 
      true
106 
      testUart_wishbone_slave - behavior (/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd)
107
108
109
110 
         1
111 
         Design Utilities
112
113
114
115
116 
      0
117 
      0
118 
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000
119 
      false
120
121
122
123
124 
         1
125
126
127
128
129 
      0
130 
      0
131 
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000
132 
      false
133
134
135 
   000000ff00000000000000020000011b0000011b01000000040100000002
136 
   Behavioral Simulation
137
138
139 
         1
140
141
142
143
144 
      0
145 
      0
146 
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
147 
      false
148
149
150

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.