URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [iseconfig/] [iseProject.projectmgr] - Blame information for rev 35

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         2
         /INTERCON_P2P - Behavioral E:|uart_block|hdl|iseProject|INTERCON_P2P.vhd/uUartWishboneSlave - uart_wishbone_slave - Behavioral
         /INTERCON_P2P - Behavioral |home|laraujo|work|uart_block|hdl|iseProject|INTERCON_P2P.vhd/uUartWishboneSlave - uart_wishbone_slave - Behavioral
         /serial_transmitter - Behavioral E:|uart_block|hdl|iseProject|serial_transmitter.vhd
         /uart_wishbone_slave - Behavioral |home|laraujo|work|uart_block|hdl|iseProject|uart_wishbone_slave.vhd/uUartCommunicationBlocks - uart_communication_blocks - Behavioral
         /uart_wishbone_slave - Behavioral |home|laraujo|work|uart_block|hdl|iseProject|uart_wishbone_slave.vhd/uUartControl - uart_control - Behavioral
      
      
         INTERCON_P2P - Behavioral (E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd)
      
      0
      0
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      INTERCON_P2P - Behavioral (E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd)
   
   
      
         1
         Configure Target Device
         Design Utilities/Compile HDL Simulation Libraries
         Implement Design
         User Constraints
      
      
         Design Utilities
      
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      0
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      0
      0
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      work
   
   
      
         1
         Configure Target Device
         Design Utilities
         Implement Design/Map
         Implement Design/Place & Route/Back-annotate Pin Locations
         Implement Design/Place & Route/Generate IBIS Model
         Implement Design/Place & Route/Generate Post-Place & Route Static Timing
         Implement Design/Translate
         User Constraints
      
      
         Analyze Design Using ChipScope
      
      10
      0
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000
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      Analyze Design Using ChipScope
   
   
      
         2
         /INTERCON_P2P - Behavioral E:|uart_block|hdl|iseProject|INTERCON_P2P.vhd
         /INTERCON_P2P - Behavioral |home|laraujo|work|uart_block|hdl|iseProject|INTERCON_P2P.vhd
         /testBaud_generator - behavior E:|uart_block|hdl|iseProject|testBaud_generator.vhd
         /testBaud_generator - behavior |home|laraujo|work|uart_block|hdl|iseProject|testBaud_generator.vhd
         /testDivisor - behavior E:|uart_block|hdl|iseProject|testDivisor.vhd
         /testDivisor - behavior |home|laraujo|work|uart_block|hdl|iseProject|testDivisor.vhd
         /testSerial_receiver - behavior E:|uart_block|hdl|iseProject|testSerial_receiver.vhd
         /testSerial_receiver - behavior |home|laraujo|work|uart_block|hdl|iseProject|testSerial_receiver.vhd
         /testSerial_transmitter - behavior E:|uart_block|hdl|iseProject|testSerial_transmitter.vhd
         /testSerial_transmitter - behavior |home|laraujo|work|uart_block|hdl|iseProject|testSerial_transmitter.vhd
         /testUart_communication_block - behavior E:|uart_block|hdl|iseProject|testUart_communication_block.vhd
         /testUart_communication_block - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_communication_block.vhd
         /testUart_control - behavior E:|uart_block|hdl|iseProject|testUart_control.vhd
         /testUart_control - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_control.vhd
         /testUart_control - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_control.vhd/uut - uart_control - Behavioral
         /testUart_wishbone_slave - behavior E:|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd
         /testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd
         /testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartCommunicationBlocks - uart_communication_blocks - Behavioral
         /testUart_wishbone_slave - behavior |home|laraujo|work|uart_block|hdl|iseProject|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartControl - uart_control - Behavioral
      
      
         testUart_communication_block - behavior (E:/uart_block/hdl/iseProject/testUart_communication_block.vhd)
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001bd000000020000000000000000000000000200000064ffffffff000000810000000300000002000001bd0000000100000003000000000000000100000003
      true
      testUart_communication_block - behavior (E:/uart_block/hdl/iseProject/testUart_communication_block.vhd)
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000
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         1
      
      
         Simulate Behavioral Model
      
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      0
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      Simulate Behavioral Model
   
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         1
      
      
         
      
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Line No.	Rev	Author	Line
1	34	leonardoar
2
3
4
5
6
7
8
9			`2`
10	35	leonardoar	`/INTERCON_P2P - Behavioral E:\|uart_block\|hdl\|iseProject\|INTERCON_P2P.vhd/uUartWishboneSlave - uart_wishbone_slave - Behavioral`
11	34	leonardoar	`/INTERCON_P2P - Behavioral \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|INTERCON_P2P.vhd/uUartWishboneSlave - uart_wishbone_slave - Behavioral`
12			`/serial_transmitter - Behavioral E:\|uart_block\|hdl\|iseProject\|serial_transmitter.vhd`
13			`/uart_wishbone_slave - Behavioral \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|uart_wishbone_slave.vhd/uUartCommunicationBlocks - uart_communication_blocks - Behavioral`
14			`/uart_wishbone_slave - Behavioral \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|uart_wishbone_slave.vhd/uUartControl - uart_control - Behavioral`
15
16
17			`INTERCON_P2P - Behavioral (E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd)`
18
19			`0`
20			`0`
21	35	leonardoar	`000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001ef000000020000000000000000000000000200000064ffffffff000000810000000300000002000001ef0000000100000003000000000000000100000003`
22	34	leonardoar	`true`
23			`INTERCON_P2P - Behavioral (E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd)`
24
25
26
27			`1`
28			`Configure Target Device`
29			`Design Utilities/Compile HDL Simulation Libraries`
30			`Implement Design`
31			`User Constraints`
32
33
34			`Design Utilities`
35
36			`0`
37			`0`
38	35	leonardoar	`000000ff00000000000000010000000100000000000000000000000000000000000000000000000163000000010000000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000`
39	34	leonardoar	`false`
40			`Design Utilities`
41
42
43
44			`1`
45
46
47			`pkgDefinitions.vhd`
48
49			`0`
50			`0`
51	35	leonardoar	`000000ff00000000000000010000000000000000010000000000000000000000000000000000000301000000040101000100000000000000000000000064ffffffff0000008100000000000000040000006900000001000000000000002400000001000000000000006600000001000000000000020e0000000100000000`
52	34	leonardoar	`false`
53			`pkgDefinitions.vhd`
54
55
56
57			`1`
58
59
60			`0`
61			`0`
62			`000000ff000000000000000100000000000000000100000000000000000000000000000000000000f9000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f90000000100000000`
63			`false`
64			`work`
65
66
67
68			`1`
69			`Configure Target Device`
70			`Design Utilities`
71	35	leonardoar	`Implement Design/Map`
72			`Implement Design/Place & Route/Back-annotate Pin Locations`
73			`Implement Design/Place & Route/Generate IBIS Model`
74			`Implement Design/Place & Route/Generate Post-Place & Route Static Timing`
75			`Implement Design/Translate`
76	34	leonardoar	`User Constraints`
77
78
79	35	leonardoar	`Analyze Design Using ChipScope`
80	34	leonardoar
81	35	leonardoar	`10`
82	34	leonardoar	`0`
83	35	leonardoar	`000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000`
84	34	leonardoar	`false`
85	35	leonardoar	`Analyze Design Using ChipScope`
86	34	leonardoar
87
88
89			`2`
90	35	leonardoar	`/INTERCON_P2P - Behavioral E:\|uart_block\|hdl\|iseProject\|INTERCON_P2P.vhd`
91	34	leonardoar	`/INTERCON_P2P - Behavioral \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|INTERCON_P2P.vhd`
92			`/testBaud_generator - behavior E:\|uart_block\|hdl\|iseProject\|testBaud_generator.vhd`
93			`/testBaud_generator - behavior \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|testBaud_generator.vhd`
94			`/testDivisor - behavior E:\|uart_block\|hdl\|iseProject\|testDivisor.vhd`
95			`/testDivisor - behavior \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|testDivisor.vhd`
96			`/testSerial_receiver - behavior E:\|uart_block\|hdl\|iseProject\|testSerial_receiver.vhd`
97			`/testSerial_receiver - behavior \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|testSerial_receiver.vhd`
98			`/testSerial_transmitter - behavior E:\|uart_block\|hdl\|iseProject\|testSerial_transmitter.vhd`
99			`/testSerial_transmitter - behavior \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|testSerial_transmitter.vhd`
100			`/testUart_communication_block - behavior E:\|uart_block\|hdl\|iseProject\|testUart_communication_block.vhd`
101			`/testUart_communication_block - behavior \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|testUart_communication_block.vhd`
102			`/testUart_control - behavior E:\|uart_block\|hdl\|iseProject\|testUart_control.vhd`
103			`/testUart_control - behavior \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|testUart_control.vhd`
104			`/testUart_control - behavior \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|testUart_control.vhd/uut - uart_control - Behavioral`
105			`/testUart_wishbone_slave - behavior E:\|uart_block\|hdl\|iseProject\|testUart_wishbone_slave.vhd`
106			`/testUart_wishbone_slave - behavior \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|testUart_wishbone_slave.vhd`
107			`/testUart_wishbone_slave - behavior \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartCommunicationBlocks - uart_communication_blocks - Behavioral`
108			`/testUart_wishbone_slave - behavior \|home\|laraujo\|work\|uart_block\|hdl\|iseProject\|testUart_wishbone_slave.vhd/uut - uart_wishbone_slave - Behavioral/uUartControl - uart_control - Behavioral`
109
110
111	35	leonardoar	`testUart_communication_block - behavior (E:/uart_block/hdl/iseProject/testUart_communication_block.vhd)`
112	34	leonardoar
113			`0`
114			`0`
115	35	leonardoar	`000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001bd000000020000000000000000000000000200000064ffffffff000000810000000300000002000001bd0000000100000003000000000000000100000003`
116	34	leonardoar	`true`
117	35	leonardoar	`testUart_communication_block - behavior (E:/uart_block/hdl/iseProject/testUart_communication_block.vhd)`
118	34	leonardoar
119
120
121			`1`
122			`Design Utilities`
123
124
125
126
127			`0`
128			`0`
129			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000`
130			`false`
131
132
133
134
135			`1`
136
137
138			`Simulate Behavioral Model`
139
140			`0`
141			`0`
142			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000`
143			`false`
144			`Simulate Behavioral Model`
145
146			`000000ff00000000000000020000011b0000011b01000000040100000002`
147	35	leonardoar	`Implementation`
148	34	leonardoar
149
150			`1`
151
152
153
154
155			`0`
156			`0`
157			`000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000`
158			`false`
159
160
161
162
163			`1`
164
165
166	35	leonardoar
167	34	leonardoar
168			`0`
169			`0`
170	35	leonardoar	`000000ff00000000000000010000000100000000000000000000000000000000000000000000000163000000010000000100000000000000000000000064ffffffff000000810000000000000001000001630000000100000000`
171	34	leonardoar	`false`
172	35	leonardoar
173	34	leonardoar
174

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Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [iseconfig/] [iseProject.projectmgr] - Blame information for rev 35