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35 leonardoar
ISim log file
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39 leonardoar
Running: E:\uart_block\hdl\iseProject\testUart_communication_block_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testUart_communication_block_isim_beh.wdb
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35 leonardoar
ISim O.87xd (signature 0xc3576ebc)
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WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
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This is a Full version of ISim.
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Time resolution is 1 ps
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# onerror resume
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# wave add /
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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39 leonardoar
In process testUart_communication_block.vhd:stim_proc
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35 leonardoar
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INFO: Simulator is stopped.
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