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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [isim.log] - Blame information for rev 18

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Line No. Rev Author Line
1 10 leonardoar 
ISim log file
2 16 leonardoar 
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
3 10 leonardoar 
ISim O.87xd (signature 0x8ddf5b5d)
4 
WARNING: A WEBPACK license was found.
5 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
6 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
7 
This is a Lite version of ISim.
8 
Time resolution is 1 ps
9 
# onerror resume
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# wave add /
11 16 leonardoar 
# run 1000 ms
12 10 leonardoar 
Simulator is doing circuit initialization process.
13 
Finished circuit initialization process.
14 
 
15 
** Failure:NONE. End of simulation.
16 
User(VHDL) Code Called Simulation Stop
17 16 leonardoar 
In process testUart_wishbone_slave.vhd:stim_proc
18 10 leonardoar 
 
19 
INFO: Simulator is stopped.
20 18 leonardoar 
ISim O.87xd (signature 0x8ddf5b5d)
21 
WARNING: A WEBPACK license was found.
22 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
23 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
24 
This is a Lite version of ISim.
25 
# run 1000 ms
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Simulator is doing circuit initialization process.
27 
Finished circuit initialization process.
28 
Stopped at time : 0 fs : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 30
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# run all
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Stopped at time : 24706500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
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# run all
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Stopped at time : 25249500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
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# run all
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Stopped at time : 25792500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
35 
ISim O.87xd (signature 0x8ddf5b5d)
36 
WARNING: A WEBPACK license was found.
37 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
38 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
39 
This is a Lite version of ISim.
40 
# run 1000 ms
41 
Simulator is doing circuit initialization process.
42 
Finished circuit initialization process.
43 
Stopped at time : 87 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
44 
# run all
45 
Stopped at time : 1821 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" Line 46
46 
# run all
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Stopped at time : 8765 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" Line 87
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# run all
49 
 
50 
** Failure:NONE. End of simulation.
51 
User(VHDL) Code Called Simulation Stop
52 
In process testUart_wishbone_slave.vhd:stim_proc
53 
 
54 
INFO: Simulator is stopped.
55 
ISim O.87xd (signature 0x8ddf5b5d)
56 
WARNING: A WEBPACK license was found.
57 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
58 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
59 
This is a Lite version of ISim.
60 
# run 1000 ms
61 
Simulator is doing circuit initialization process.
62 
Finished circuit initialization process.
63 
 
64 
** Failure:NONE. End of simulation.
65 
User(VHDL) Code Called Simulation Stop
66 
In process testUart_wishbone_slave.vhd:stim_proc
67 
 
68 
INFO: Simulator is stopped.
69 
ISim O.87xd (signature 0x8ddf5b5d)
70 
WARNING: A WEBPACK license was found.
71 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
72 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
73 
This is a Lite version of ISim.
74 
# run 1000 ms
75 
Simulator is doing circuit initialization process.
76 
Finished circuit initialization process.
77 
Stopped at time : 87 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
78 
ISim O.87xd (signature 0x8ddf5b5d)
79 
WARNING: A WEBPACK license was found.
80 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
81 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
82 
This is a Lite version of ISim.
83 
# run 1000 ms
84 
Simulator is doing circuit initialization process.
85 
Finished circuit initialization process.
86 
Stopped at time : 870 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35
87 
# run all
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89 
** Failure:NONE. End of simulation.
90 
User(VHDL) Code Called Simulation Stop
91 
In process testUart_wishbone_slave.vhd:stim_proc
92 
 
93 
INFO: Simulator is stopped.
94 
ISim O.87xd (signature 0x8ddf5b5d)
95 
WARNING: A WEBPACK license was found.
96 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
97 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
98 
This is a Lite version of ISim.
99 
# run 1000 ms
100 
Simulator is doing circuit initialization process.
101 
Finished circuit initialization process.
102 
Stopped at time : 9627710 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" Line 60
103 
ISim O.87xd (signature 0x8ddf5b5d)
104 
WARNING: A WEBPACK license was found.
105 
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
106 
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
107 
This is a Lite version of ISim.
108 
# run 1000 ms
109 
Simulator is doing circuit initialization process.
110 
Finished circuit initialization process.
111 
Stopped at time : 87690 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 125
112 
# run all
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Stopped at time : 96330 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 91
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# run all
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Stopped at time : 105010 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 96
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# run all
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Stopped at time : 113690 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 101
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# run all
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Stopped at time : 122370 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 106
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# run all
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Stopped at time : 131050 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 111
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# run all
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Stopped at time : 139730 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 116
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# run all
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Stopped at time : 148410 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 121
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# run all
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Stopped at time : 157090 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 126
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# run all
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Stopped at time : 165770 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 132
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# run all
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Stopped at time : 9633330 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 71
132 
# exit 0

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