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leonardoar |
ISim log file
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Running: E:\uart_block\hdl\iseProject\testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
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ISim O.87xd (signature 0xc3576ebc)
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WARNING: A WEBPACK license was found.
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| 5 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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| 6 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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Time resolution is 1 ps
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# onerror resume
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# wave add /
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0xc3576ebc)
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WARNING: A WEBPACK license was found.
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| 22 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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| 23 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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| 24 |
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 174470 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220
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ISim O.87xd (signature 0xc3576ebc)
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WARNING: A WEBPACK license was found.
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| 31 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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| 32 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 174470 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220
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ISim O.87xd (signature 0xc3576ebc)
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WARNING: A WEBPACK license was found.
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| 40 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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| 41 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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| 42 |
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220
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# run all
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Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
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ISim O.87xd (signature 0xc3576ebc)
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WARNING: A WEBPACK license was found.
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| 51 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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| 52 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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| 53 |
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
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ISim O.87xd (signature 0xc3576ebc)
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WARNING: A WEBPACK license was found.
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| 60 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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| 61 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
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ISim O.87xd (signature 0xc3576ebc)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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| 70 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
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# run all
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0xc3576ebc)
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WARNING: A WEBPACK license was found.
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| 85 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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| 86 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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| 87 |
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151
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# run all
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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# show driver /testuart_wishbone_slave/dat_o0
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Driver for /testuart_wishbone_slave/dat_o0[0]
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'1' : /testuart_wishbone_slave/uut/uUartControl/:64
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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Driver for /testuart_wishbone_slave/dat_o0[10]
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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Driver for /testuart_wishbone_slave/dat_o0[11]
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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Driver for /testuart_wishbone_slave/dat_o0[12]
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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Driver for /testuart_wishbone_slave/dat_o0[13]
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 119 |
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| 120 |
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Driver for /testuart_wishbone_slave/dat_o0[14]
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 122 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 123 |
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Driver for /testuart_wishbone_slave/dat_o0[15]
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| 125 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 127 |
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| 128 |
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Driver for /testuart_wishbone_slave/dat_o0[16]
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 130 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 131 |
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| 132 |
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Driver for /testuart_wishbone_slave/dat_o0[17]
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 134 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 135 |
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| 136 |
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Driver for /testuart_wishbone_slave/dat_o0[18]
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| 137 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 138 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 139 |
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| 140 |
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Driver for /testuart_wishbone_slave/dat_o0[19]
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| 141 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 142 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 143 |
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| 144 |
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Driver for /testuart_wishbone_slave/dat_o0[1]
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| 145 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 146 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 147 |
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| 148 |
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Driver for /testuart_wishbone_slave/dat_o0[20]
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| 149 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 150 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 151 |
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| 152 |
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Driver for /testuart_wishbone_slave/dat_o0[21]
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| 153 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 154 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 155 |
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| 156 |
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Driver for /testuart_wishbone_slave/dat_o0[22]
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| 157 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 158 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 159 |
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| 160 |
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Driver for /testuart_wishbone_slave/dat_o0[23]
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| 161 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 162 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 163 |
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| 164 |
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Driver for /testuart_wishbone_slave/dat_o0[24]
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| 165 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 166 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 167 |
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| 168 |
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Driver for /testuart_wishbone_slave/dat_o0[25]
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| 169 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 170 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 171 |
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| 172 |
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Driver for /testuart_wishbone_slave/dat_o0[26]
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| 173 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 174 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 175 |
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| 176 |
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Driver for /testuart_wishbone_slave/dat_o0[27]
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| 177 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 178 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 179 |
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| 180 |
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Driver for /testuart_wishbone_slave/dat_o0[28]
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| 181 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 182 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 183 |
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| 184 |
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Driver for /testuart_wishbone_slave/dat_o0[29]
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| 185 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 186 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 187 |
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| 188 |
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Driver for /testuart_wishbone_slave/dat_o0[2]
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| 189 |
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'1' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 190 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 191 |
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| 192 |
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Driver for /testuart_wishbone_slave/dat_o0[30]
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| 193 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 194 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 195 |
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| 196 |
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Driver for /testuart_wishbone_slave/dat_o0[31]
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| 197 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 198 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 199 |
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| 200 |
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Driver for /testuart_wishbone_slave/dat_o0[3]
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| 201 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 202 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 203 |
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| 204 |
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Driver for /testuart_wishbone_slave/dat_o0[4]
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| 205 |
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'1' : /testuart_wishbone_slave/uut/uUartControl/:64
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| 206 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
| 207 |
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| 208 |
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Driver for /testuart_wishbone_slave/dat_o0[5]
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| 209 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
| 210 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 211 |
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| 212 |
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Driver for /testuart_wishbone_slave/dat_o0[6]
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| 213 |
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'1' : /testuart_wishbone_slave/uut/uUartControl/:64
|
| 214 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 215 |
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| 216 |
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Driver for /testuart_wishbone_slave/dat_o0[7]
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| 217 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
| 218 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
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| 219 |
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| 220 |
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Driver for /testuart_wishbone_slave/dat_o0[8]
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| 221 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
| 222 |
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
| 223 |
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| 224 |
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Driver for /testuart_wishbone_slave/dat_o0[9]
|
| 225 |
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'0' : /testuart_wishbone_slave/uut/uUartControl/:64
|
| 226 |
|
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in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64
|
| 227 |
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|
| 228 |
|
|
ISim O.87xd (signature 0xc3576ebc)
|
| 229 |
|
|
WARNING: A WEBPACK license was found.
|
| 230 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
| 231 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
| 232 |
|
|
This is a Lite version of ISim.
|
| 233 |
|
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# run 1000 ms
|
| 234 |
|
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Simulator is doing circuit initialization process.
|
| 235 |
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Finished circuit initialization process.
|
| 236 |
|
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Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
| 237 |
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# run all
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| 238 |
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Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
| 239 |
|
|
ISim O.87xd (signature 0xc3576ebc)
|
| 240 |
|
|
WARNING: A WEBPACK license was found.
|
| 241 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
| 242 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
| 243 |
|
|
This is a Lite version of ISim.
|
| 244 |
|
|
# run 1000 ms
|
| 245 |
|
|
Simulator is doing circuit initialization process.
|
| 246 |
|
|
Finished circuit initialization process.
|
| 247 |
|
|
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
| 248 |
|
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# run all
|
| 249 |
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Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
| 250 |
|
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# run all
|
| 251 |
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|
| 252 |
|
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** Failure:NONE. End of simulation.
|
| 253 |
|
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User(VHDL) Code Called Simulation Stop
|
| 254 |
|
|
In process testUart_wishbone_slave.vhd:stim_proc
|
| 255 |
|
|
|
| 256 |
|
|
INFO: Simulator is stopped.
|
| 257 |
|
|
ISim O.87xd (signature 0xc3576ebc)
|
| 258 |
|
|
WARNING: A WEBPACK license was found.
|
| 259 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
| 260 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
| 261 |
|
|
This is a Lite version of ISim.
|
| 262 |
|
|
# run 1000 ms
|
| 263 |
|
|
Simulator is doing circuit initialization process.
|
| 264 |
|
|
Finished circuit initialization process.
|
| 265 |
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Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
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| 266 |
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ISim O.87xd (signature 0xc3576ebc)
|
| 267 |
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|
WARNING: A WEBPACK license was found.
|
| 268 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
| 269 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
| 270 |
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|
This is a Lite version of ISim.
|
| 271 |
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|
# run 1000 ms
|
| 272 |
|
|
Simulator is doing circuit initialization process.
|
| 273 |
|
|
Finished circuit initialization process.
|
| 274 |
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Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
| 275 |
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|
# run all
|
| 276 |
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|
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| 277 |
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** Failure:NONE. End of simulation.
|
| 278 |
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User(VHDL) Code Called Simulation Stop
|
| 279 |
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In process testUart_wishbone_slave.vhd:stim_proc
|
| 280 |
|
|
|
| 281 |
|
|
INFO: Simulator is stopped.
|
| 282 |
|
|
ISim O.87xd (signature 0xc3576ebc)
|
| 283 |
|
|
WARNING: A WEBPACK license was found.
|
| 284 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
| 285 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
| 286 |
|
|
This is a Lite version of ISim.
|
| 287 |
|
|
# run 1000 ms
|
| 288 |
|
|
Simulator is doing circuit initialization process.
|
| 289 |
|
|
Finished circuit initialization process.
|
| 290 |
|
|
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
| 291 |
|
|
# run all
|
| 292 |
|
|
|
| 293 |
|
|
** Failure:NONE. End of simulation.
|
| 294 |
|
|
User(VHDL) Code Called Simulation Stop
|
| 295 |
|
|
In process testUart_wishbone_slave.vhd:stim_proc
|
| 296 |
|
|
|
| 297 |
|
|
INFO: Simulator is stopped.
|
| 298 |
|
|
ISim O.87xd (signature 0xc3576ebc)
|
| 299 |
|
|
WARNING: A WEBPACK license was found.
|
| 300 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
| 301 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
| 302 |
|
|
This is a Lite version of ISim.
|
| 303 |
|
|
# run 1000 ms
|
| 304 |
|
|
Simulator is doing circuit initialization process.
|
| 305 |
|
|
Finished circuit initialization process.
|
| 306 |
|
|
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81
|
| 307 |
|
|
# run all
|
| 308 |
|
|
|
| 309 |
|
|
** Failure:NONE. End of simulation.
|
| 310 |
|
|
User(VHDL) Code Called Simulation Stop
|
| 311 |
|
|
In process testUart_wishbone_slave.vhd:stim_proc
|
| 312 |
|
|
|
| 313 |
|
|
INFO: Simulator is stopped.
|
| 314 |
|
|
ISim O.87xd (signature 0xc3576ebc)
|
| 315 |
|
|
WARNING: A WEBPACK license was found.
|
| 316 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
| 317 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
| 318 |
|
|
This is a Lite version of ISim.
|
| 319 |
|
|
# run 1000 ms
|
| 320 |
|
|
Simulator is doing circuit initialization process.
|
| 321 |
|
|
Finished circuit initialization process.
|
| 322 |
|
|
Stopped at time : 26193350 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 39
|
| 323 |
|
|
ISim O.87xd (signature 0xc3576ebc)
|
| 324 |
|
|
WARNING: A WEBPACK license was found.
|
| 325 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
| 326 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
| 327 |
|
|
This is a Lite version of ISim.
|
| 328 |
|
|
# run 1000 ms
|
| 329 |
|
|
Simulator is doing circuit initialization process.
|
| 330 |
|
|
Finished circuit initialization process.
|
| 331 |
|
|
Stopped at time : 36542110 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 39
|
| 332 |
|
|
ISim O.87xd (signature 0xc3576ebc)
|
| 333 |
|
|
WARNING: A WEBPACK license was found.
|
| 334 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
| 335 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
| 336 |
|
|
This is a Lite version of ISim.
|
| 337 |
|
|
# run 1000 ms
|
| 338 |
|
|
Simulator is doing circuit initialization process.
|
| 339 |
|
|
Finished circuit initialization process.
|
| 340 |
|
|
Stopped at time : 23647410 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 82
|
| 341 |
|
|
ISim O.87xd (signature 0xc3576ebc)
|
| 342 |
|
|
WARNING: A WEBPACK license was found.
|
| 343 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
| 344 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
| 345 |
|
|
This is a Lite version of ISim.
|
| 346 |
|
|
# run 1000 ms
|
| 347 |
|
|
Simulator is doing circuit initialization process.
|
| 348 |
|
|
Finished circuit initialization process.
|
| 349 |
|
|
Stopped at time : 16400510 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 89
|
| 350 |
|
|
ISim O.87xd (signature 0xc3576ebc)
|
| 351 |
|
|
WARNING: A WEBPACK license was found.
|
| 352 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
| 353 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
| 354 |
|
|
This is a Lite version of ISim.
|
| 355 |
|
|
# run 1000 ms
|
| 356 |
|
|
Simulator is doing circuit initialization process.
|
| 357 |
|
|
Finished circuit initialization process.
|
| 358 |
|
|
|
| 359 |
|
|
** Failure:NONE. End of simulation.
|
| 360 |
|
|
User(VHDL) Code Called Simulation Stop
|
| 361 |
|
|
In process testUart_wishbone_slave.vhd:stim_proc
|
| 362 |
|
|
|
| 363 |
|
|
INFO: Simulator is stopped.
|
