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leonardoar |
ISim log file
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leonardoar |
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
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leonardoar |
ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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5 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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6 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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Time resolution is 1 ps
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# onerror resume
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# wave add /
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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leonardoar |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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leonardoar |
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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leonardoar |
In process testUart_wishbone_slave.vhd:stim_proc
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leonardoar |
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INFO: Simulator is stopped.
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leonardoar |
ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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25 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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26 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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43 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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77 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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Stopped at time : 950 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 116
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# run all
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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Stopped at time : 950 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 116
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# run all
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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131 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
132 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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148 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
149 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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150 |
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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Stopped at time : 950 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 105
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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160 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 186
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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169 |
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
170 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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Stopped at time : 950 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 104
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# run all
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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188 |
|
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
189 |
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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Stopped at time : 950 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 105
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# run all
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Stopped at time : 970 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 105
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# run all
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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207 |
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ISim O.87xd (signature 0x8ddf5b5d)
|
208 |
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WARNING: A WEBPACK license was found.
|
209 |
|
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
210 |
|
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
211 |
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This is a Lite version of ISim.
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212 |
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# run 1000 ms
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213 |
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
|
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Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
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# run all
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Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
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# run all
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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Stopped at time : 850 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
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Stopped at time : 1030 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 161
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
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|
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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Stopped at time : 910 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
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Stopped at time : 990 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
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# run all
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
|
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
305 |
|
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
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# run all
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
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** Failure:NONE. End of simulation.
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User(VHDL) Code Called Simulation Stop
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In process testUart_wishbone_slave.vhd:stim_proc
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INFO: Simulator is stopped.
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
|
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
324 |
|
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.
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Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
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|
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
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This is a Lite version of ISim.
|
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# run 1000 ms
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Simulator is doing circuit initialization process.
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Stopped at time : 0 fs : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 157
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ISim O.87xd (signature 0x8ddf5b5d)
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WARNING: A WEBPACK license was found.
|
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|
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WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
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|
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WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
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This is a Lite version of ISim.
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# run 1000 ms
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Simulator is doing circuit initialization process.
|
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Stopped at time : 0 fs : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 157
|
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# run all
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Finished circuit initialization process.
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Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 157
|
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# run all
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
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Stopped at time : 10 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 157
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# run all
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Stopped at time : 30 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 169
|
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# run all
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** Failure:NONE. End of simulation.
|
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User(VHDL) Code Called Simulation Stop
|
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In process testUart_wishbone_slave.vhd:stim_proc
|
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|
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INFO: Simulator is stopped.
|
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|
ISim O.87xd (signature 0x8ddf5b5d)
|
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|
|
WARNING: A WEBPACK license was found.
|
365 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
366 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
367 |
|
|
This is a Lite version of ISim.
|
368 |
|
|
# run 1000 ms
|
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|
|
Simulator is doing circuit initialization process.
|
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|
|
Finished circuit initialization process.
|
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|
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
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|
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
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Stopped at time : 30 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 163
|
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|
|
ISim O.87xd (signature 0x8ddf5b5d)
|
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|
|
WARNING: A WEBPACK license was found.
|
377 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
378 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
379 |
|
|
This is a Lite version of ISim.
|
380 |
|
|
# run 1000 ms
|
381 |
|
|
Simulator is doing circuit initialization process.
|
382 |
|
|
Finished circuit initialization process.
|
383 |
|
|
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
384 |
|
|
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
385 |
|
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
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|
|
Stopped at time : 30 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 163
|
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|
|
ISim O.87xd (signature 0x8ddf5b5d)
|
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|
|
WARNING: A WEBPACK license was found.
|
389 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
390 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
391 |
|
|
This is a Lite version of ISim.
|
392 |
|
|
# run 1000 ms
|
393 |
|
|
Simulator is doing circuit initialization process.
|
394 |
|
|
Finished circuit initialization process.
|
395 |
|
|
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
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|
|
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
397 |
|
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at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
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|
|
Stopped at time : 850 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 164
|
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# run all
|
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Stopped at time : 930 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 164
|
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# run all
|
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Stopped at time : 1010 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 164
|
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# run all
|
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Stopped at time : 1090 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 164
|
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# run all
|
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|
Stopped at time : 1170 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" Line 164
|
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# run all
|
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|
409 |
|
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** Failure:NONE. End of simulation.
|
410 |
|
|
User(VHDL) Code Called Simulation Stop
|
411 |
|
|
In process testUart_wishbone_slave.vhd:stim_proc
|
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|
413 |
|
|
INFO: Simulator is stopped.
|
414 |
|
|
ISim O.87xd (signature 0x8ddf5b5d)
|
415 |
|
|
WARNING: A WEBPACK license was found.
|
416 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
417 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
418 |
|
|
This is a Lite version of ISim.
|
419 |
|
|
# run 1000 ms
|
420 |
|
|
Simulator is doing circuit initialization process.
|
421 |
|
|
Finished circuit initialization process.
|
422 |
|
|
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
423 |
|
|
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
424 |
|
|
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
425 |
|
|
|
426 |
|
|
** Failure:NONE. End of simulation.
|
427 |
|
|
User(VHDL) Code Called Simulation Stop
|
428 |
|
|
In process testUart_wishbone_slave.vhd:stim_proc
|
429 |
|
|
|
430 |
|
|
INFO: Simulator is stopped.
|
431 |
|
|
ISim O.87xd (signature 0x8ddf5b5d)
|
432 |
|
|
WARNING: A WEBPACK license was found.
|
433 |
|
|
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
434 |
|
|
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
435 |
|
|
This is a Lite version of ISim.
|
436 |
|
|
# run 1000 ms
|
437 |
|
|
Simulator is doing circuit initialization process.
|
438 |
|
|
Finished circuit initialization process.
|
439 |
|
|
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
440 |
|
|
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
441 |
|
|
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
|
442 |
|
|
|
443 |
|
|
** Failure:NONE. End of simulation.
|
444 |
|
|
User(VHDL) Code Called Simulation Stop
|
445 |
|
|
In process testUart_wishbone_slave.vhd:stim_proc
|
446 |
|
|
|
447 |
|
|
INFO: Simulator is stopped.
|