URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [pins_spartan3EStarterKit.ucf] - Blame information for rev 36
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
36 |
leonardoar |
# Constraint file to point to the right pins on the Spartan3E starter kit
|
2 |
27 |
leonardoar |
NET "EXTCLK" LOC = "c9"| IOSTANDARD = LVCMOS33 ;
|
3 |
|
|
|
4 |
|
|
NET "EXTRST" LOC = "n17"| IOSTANDARD = LVCMOS33 ;
|
5 |
|
|
|
6 |
|
|
NET "byte_out<7>" LOC = "f9"| IOSTANDARD = LVCMOS33 ;
|
7 |
|
|
NET "byte_out<6>" LOC = "e9"| IOSTANDARD = LVCMOS33 ;
|
8 |
|
|
NET "byte_out<5>" LOC = "d11"| IOSTANDARD = LVCMOS33 ;
|
9 |
|
|
NET "byte_out<4>" LOC = "c11"| IOSTANDARD = LVCMOS33 ;
|
10 |
|
|
NET "byte_out<3>" LOC = "f11"| IOSTANDARD = LVCMOS33 ;
|
11 |
|
|
NET "byte_out<2>" LOC = "e11"| IOSTANDARD = LVCMOS33 ;
|
12 |
|
|
NET "byte_out<1>" LOC = "e12"| IOSTANDARD = LVCMOS33 ;
|
13 |
|
|
NET "byte_out<0>" LOC = "f12"| IOSTANDARD = LVCMOS33 ;
|
14 |
|
|
|
15 |
|
|
#NET "data_avaible" LOC = "u17"| IOSTANDARD = LVCMOS33 ;
|
16 |
|
|
|
17 |
|
|
NET "tx" LOC = "m14"| IOSTANDARD = LVCMOS33 ; #m14
|
18 |
|
|
|
19 |
|
|
NET "rx" LOC = "r7"| IOSTANDARD = LVCMOS33 ; #r7
|
20 |
|
|
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.