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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [serial_receiver.syr] - Blame information for rev 30

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Release 13.4 - xst O.87xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
 
-->
Parameter xsthdpdir set to xst
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
 
-->
Reading design: serial_receiver.prj
 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT
 
 
=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "serial_receiver.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
 
---- Target Parameters
Output File Name                   : "serial_receiver"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320
 
---- Source Options
Top Module Name                    : serial_receiver
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No
 
---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES
 
---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5
 
=========================================================================
 
 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
Architecture pkgdefinitions of Entity pkgdefinitions is up to date.
Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" in Library work.
Architecture behavioral of Entity serial_receiver is up to date.
 
=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity  in library  (architecture ).
 
 
=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity  in library  (Architecture ).
Entity  analyzed. Unit  generated.
 
 
=========================================================================
*                           HDL Synthesis                               *
=========================================================================
 
Performing bidirectional port resolution...
 
Synthesizing Unit .
    Related source file is "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd".
    Found finite state machine  for signal .
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 10                                             |
    | Inputs             | 0                                              |
    | Outputs            | 11                                             |
    | Clock              | baudClk                   (rising_edge)        |
    | Reset              | syncDetected              (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | bit0                                           |
    | Power Up State     | bit0                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine  for signal .
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 8                                              |
    | Inputs             | 2                                              |
    | Outputs            | 4                                              |
    | Clock              | baudOverSampleClk         (rising_edge)        |
    | Reset              | rst                       (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | s0                                             |
    | Power Up State     | s0                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal .
    Found 8-bit register for signal .
    Found 8-bit register for signal .
    Found 1-bit register for signal .
    Summary:
        inferred   2 Finite State Machine(s).
        inferred  18 D-type flip-flop(s).
Unit  synthesized.
 
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# Registers                                            : 11
 1-bit register                                        : 10
 8-bit register                                        : 1
 
=========================================================================
 
=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
 
Analyzing FSM  for best encoding.
Optimizing FSM  on signal  with gray encoding.
-------------------
 State | Encoding
-------------------
 s0    | 00
 s1    | 01
 s2    | 11
 s3    | 10
-------------------
Analyzing FSM  for best encoding.
Optimizing FSM  on signal  with one-hot encoding.
-----------------------
 State   | Encoding
-----------------------
 bit0    | 0000000001
 bit1    | 0000000010
 bit2    | 0000000100
 bit3    | 0000001000
 bit4    | 0000010000
 bit5    | 0000100000
 bit6    | 0001000000
 bit7    | 0010000000
 rx_stop | 0100000000
 rx_idle | 1000000000
-----------------------
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# FSMs                                                 : 2
# Registers                                            : 18
 Flip-Flops                                            : 18
 
=========================================================================
 
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
 
Optimizing unit  ...
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block serial_receiver, actual ratio is 0.
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers                                            : 29
 Flip-Flops                                            : 29
 
=========================================================================
 
=========================================================================
*                           Partition Report                            *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : serial_receiver.ngr
Top Level Output File Name         : serial_receiver
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No
 
Design Statistics
# IOs                              : 13
 
Cell Usage :
# BELS                             : 19
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 1
#      LUT2_L                      : 1
#      LUT3                        : 1
#      LUT3_D                      : 1
#      LUT4                        : 11
#      LUT4_D                      : 1
#      VCC                         : 1
# FlipFlops/Latches                : 29
#      FDC                         : 11
#      FDCE                        : 9
#      FDE                         : 8
#      FDP                         : 1
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 11
#      IBUF                        : 2
#      OBUF                        : 9
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 3s500efg320-4
 
 Number of Slices:                       19  out of   4656     0%
 Number of Slice Flip Flops:             29  out of   9312     0%
 Number of 4 input LUTs:                 17  out of   9312     0%
 Number of IOs:                          13
 Number of bonded IOBs:                  13  out of    232     5%
 Number of GCLKs:                         2  out of     24     8%
 
---------------------------
Partition Resource Summary:
---------------------------
 
  No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
baudOverSampleClk                  | BUFGP                  | 3     |
baudClk                            | BUFGP                  | 26    |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------------------------------+------------------------+-------+
Control Signal                                                 | Buffer(FF name)        | Load  |
---------------------------------------------------------------+------------------------+-------+
current_s_FSM_Acst_FSM_inv(current_s_FSM_Acst_FSM_inv1_INV_0:O)| NONE(byteReceived_0)   | 18    |
rst                                                            | IBUF                   | 3     |
---------------------------------------------------------------+------------------------+-------+
 
Timing Summary:
---------------
Speed Grade: -4
 
   Minimum period: 4.853ns (Maximum Frequency: 206.058MHz)
   Minimum input arrival time before clock: 4.569ns
   Maximum output required time after clock: 4.450ns
   Maximum combinational path delay: No path found
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'baudOverSampleClk'
  Clock period: 2.489ns (frequency: 401.768MHz)
  Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Delay:               2.489ns (Levels of Logic = 1)
  Source:            syncDetected (FF)
  Destination:       syncDetected (FF)
  Source Clock:      baudOverSampleClk rising
  Destination Clock: baudOverSampleClk rising
 
  Data Path: syncDetected to syncDetected
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             10   0.591   0.886  syncDetected (syncDetected)
     LUT4:I3->O            1   0.704   0.000  syncDetected_mux00001 (syncDetected_mux0000)
     FDC:D                     0.308          syncDetected
    ----------------------------------------
    Total                      2.489ns (1.603ns logic, 0.886ns route)
                                       (64.4% logic, 35.6% route)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'baudClk'
  Clock period: 4.853ns (frequency: 206.058MHz)
  Total number of paths / destination ports: 113 / 25
-------------------------------------------------------------------------
Delay:               4.853ns (Levels of Logic = 3)
  Source:            current_s_FSM_FFd7 (FF)
  Destination:       data_byte_0 (FF)
  Source Clock:      baudClk rising
  Destination Clock: baudClk rising
 
  Data Path: current_s_FSM_FFd7 to data_byte_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.591   0.706  current_s_FSM_FFd7 (current_s_FSM_FFd7)
     LUT4:I0->O            1   0.704   0.424  data_byte_mux0000<0>1_SW0 (N5)
     LUT4_D:I3->O          7   0.704   0.712  data_byte_mux0000<0>1 (N01)
     LUT4:I3->O            1   0.704   0.000  data_byte_mux0000<6>1 (data_byte_mux0000<6>)
     FDE:D                     0.308          data_byte_6
    ----------------------------------------
    Total                      4.853ns (3.011ns logic, 1.842ns route)
                                       (62.0% logic, 38.0% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'baudOverSampleClk'
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset:              3.366ns (Levels of Logic = 2)
  Source:            serial_in (PAD)
  Destination:       filterRx_FSM_FFd2 (FF)
  Destination Clock: baudOverSampleClk rising
 
  Data Path: serial_in to filterRx_FSM_FFd2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   1.218   1.136  serial_in_IBUF (serial_in_IBUF)
     LUT2:I0->O            1   0.704   0.000  filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In)
     FDC:D                     0.308          filterRx_FSM_FFd2
    ----------------------------------------
    Total                      3.366ns (2.230ns logic, 1.136ns route)
                                       (66.3% logic, 33.7% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'baudClk'
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset:              4.569ns (Levels of Logic = 3)
  Source:            serial_in (PAD)
  Destination:       data_byte_7 (FF)
  Destination Clock: baudClk rising
 
  Data Path: serial_in to data_byte_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   1.218   1.136  serial_in_IBUF (serial_in_IBUF)
     LUT4:I0->O            1   0.704   0.499  data_byte_mux0000<7>_SW0 (N3)
     LUT3:I1->O            1   0.704   0.000  data_byte_mux0000<7> (data_byte_mux0000<7>)
     FDE:D                     0.308          data_byte_7
    ----------------------------------------
    Total                      4.569ns (2.934ns logic, 1.635ns route)
                                       (64.2% logic, 35.8% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk'
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset:              4.450ns (Levels of Logic = 1)
  Source:            current_s_FSM_FFd1 (FF)
  Destination:       data_ready (PAD)
  Source Clock:      baudClk rising
 
  Data Path: current_s_FSM_FFd1 to data_ready
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             4   0.591   0.587  current_s_FSM_FFd1 (current_s_FSM_FFd1)
     OBUF:I->O                 3.272          data_ready_OBUF (data_ready)
    ----------------------------------------
    Total                      4.450ns (3.863ns logic, 0.587ns route)
                                       (86.8% logic, 13.2% route)
 
=========================================================================
 
 
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.59 secs
 
-->
 
 
Total memory usage is 164420 kilobytes
 
Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)
 

Line No.	Rev	Author	Line
1	15	leonardoar	`Release 13.4 - xst O.87xd (lin)`
2	2	leonardoar	`Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.`
3	15	leonardoar	`-->`
4			`Parameter TMPDIR set to xst/projnav.tmp`
5	2	leonardoar
6
7			`Total REAL time to Xst completion: 0.00 secs`
8			`Total CPU time to Xst completion: 0.05 secs`
9
10	15	leonardoar	`-->`
11			`Parameter xsthdpdir set to xst`
12	2	leonardoar
13
14			`Total REAL time to Xst completion: 0.00 secs`
15			`Total CPU time to Xst completion: 0.05 secs`
16
17	15	leonardoar	`-->`
18			`Reading design: serial_receiver.prj`
19	2	leonardoar
20			`TABLE OF CONTENTS`
21			`1) Synthesis Options Summary`
22			`2) HDL Compilation`
23			`3) Design Hierarchy Analysis`
24			`4) HDL Analysis`
25			`5) HDL Synthesis`
26			`5.1) HDL Synthesis Report`
27			`6) Advanced HDL Synthesis`
28			`6.1) Advanced HDL Synthesis Report`
29			`7) Low Level Synthesis`
30			`8) Partition Report`
31			`9) Final Report`
32			`9.1) Device utilization summary`
33			`9.2) Partition Resource Summary`
34			`9.3) TIMING REPORT`
35
36
37			`=========================================================================`
38			`* Synthesis Options Summary *`
39			`=========================================================================`
40			`---- Source Parameters`
41			`Input File Name : "serial_receiver.prj"`
42			`Input Format : mixed`
43			`Ignore Synthesis Constraint File : NO`
44
45			`---- Target Parameters`
46			`Output File Name : "serial_receiver"`
47			`Output Format : NGC`
48			`Target Device : xc3s500e-4-fg320`
49
50			`---- Source Options`
51			`Top Module Name : serial_receiver`
52			`Automatic FSM Extraction : YES`
53			`FSM Encoding Algorithm : Auto`
54			`Safe Implementation : No`
55			`FSM Style : LUT`
56			`RAM Extraction : Yes`
57			`RAM Style : Auto`
58			`ROM Extraction : Yes`
59			`Mux Style : Auto`
60			`Decoder Extraction : YES`
61			`Priority Encoder Extraction : Yes`
62			`Shift Register Extraction : YES`
63			`Logical Shifter Extraction : YES`
64			`XOR Collapsing : YES`
65			`ROM Style : Auto`
66			`Mux Extraction : Yes`
67			`Resource Sharing : YES`
68			`Asynchronous To Synchronous : NO`
69			`Multiplier Style : Auto`
70			`Automatic Register Balancing : No`
71
72			`---- Target Options`
73			`Add IO Buffers : YES`
74			`Global Maximum Fanout : 100000`
75			`Add Generic Clock Buffer(BUFG) : 24`
76			`Register Duplication : YES`
77			`Slice Packing : YES`
78			`Optimize Instantiated Primitives : NO`
79			`Use Clock Enable : Yes`
80			`Use Synchronous Set : Yes`
81			`Use Synchronous Reset : Yes`
82			`Pack IO Registers into IOBs : Auto`
83			`Equivalent register Removal : YES`
84
85			`---- General Options`
86			`Optimization Goal : Speed`
87			`Optimization Effort : 1`
88			`Keep Hierarchy : No`
89			`Netlist Hierarchy : As_Optimized`
90			`RTL Output : Yes`
91			`Global Optimization : AllClockNets`
92			`Read Cores : YES`
93			`Write Timing Constraints : NO`
94			`Cross Clock Analysis : NO`
95			`Hierarchy Separator : /`
96			`Bus Delimiter : <>`
97			`Case Specifier : Maintain`
98			`Slice Utilization Ratio : 100`
99			`BRAM Utilization Ratio : 100`
100			`Verilog 2001 : YES`
101			`Auto BRAM Packing : NO`
102			`Slice Utilization Ratio Delta : 5`
103
104			`=========================================================================`
105
106
107			`=========================================================================`
108			`* HDL Compilation *`
109			`=========================================================================`
110	15	leonardoar	`Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.`
111	2	leonardoar	`Architecture pkgdefinitions of Entity pkgdefinitions is up to date.`
112	15	leonardoar	`Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" in Library work.`
113			`Architecture behavioral of Entity serial_receiver is up to date.`
114	2	leonardoar
115			`=========================================================================`
116			`* Design Hierarchy Analysis *`
117			`=========================================================================`
118			`Analyzing hierarchy for entity in library (architecture ).`
119
120
121			`=========================================================================`
122			`* HDL Analysis *`
123			`=========================================================================`
124			`Analyzing Entity in library (Architecture ).`
125			`Entity analyzed. Unit generated.`
126
127
128			`=========================================================================`
129			`* HDL Synthesis *`
130			`=========================================================================`
131
132			`Performing bidirectional port resolution...`
133
134			`Synthesizing Unit .`
135	15	leonardoar	`Related source file is "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd".`
136	2	leonardoar	`Found finite state machine for signal .`
137			`-----------------------------------------------------------------------`
138			`\| States \| 10 \|`
139			`\| Transitions \| 10 \|`
140			`\| Inputs \| 0 \|`
141	15	leonardoar	`\| Outputs \| 11 \|`
142	2	leonardoar	`\| Clock \| baudClk (rising_edge) \|`
143			`\| Reset \| syncDetected (negative) \|`
144			`\| Reset type \| asynchronous \|`
145	15	leonardoar	`\| Reset State \| bit0 \|`
146			`\| Power Up State \| bit0 \|`
147	2	leonardoar	`\| Encoding \| automatic \|`
148			`\| Implementation \| LUT \|`
149			`-----------------------------------------------------------------------`
150			`Found finite state machine for signal .`
151			`-----------------------------------------------------------------------`
152	4	leonardoar	`\| States \| 4 \|`
153			`\| Transitions \| 8 \|`
154			`\| Inputs \| 2 \|`
155			`\| Outputs \| 4 \|`
156	2	leonardoar	`\| Clock \| baudOverSampleClk (rising_edge) \|`
157			`\| Reset \| rst (positive) \|`
158			`\| Reset type \| asynchronous \|`
159			`\| Reset State \| s0 \|`
160			`\| Power Up State \| s0 \|`
161			`\| Encoding \| automatic \|`
162			`\| Implementation \| LUT \|`
163			`-----------------------------------------------------------------------`
164	15	leonardoar	`Found 1-bit register for signal .`
165			`Found 8-bit register for signal .`
166			`Found 8-bit register for signal .`
167	2	leonardoar	`Found 1-bit register for signal .`
168			`Summary:`
169			`inferred 2 Finite State Machine(s).`
170	15	leonardoar	`inferred 18 D-type flip-flop(s).`
171	2	leonardoar	`Unit synthesized.`
172
173
174			`=========================================================================`
175			`HDL Synthesis Report`
176
177			`Macro Statistics`
178	15	leonardoar	`# Registers : 11`
179			`1-bit register : 10`
180			`8-bit register : 1`
181	2	leonardoar
182			`=========================================================================`
183
184			`=========================================================================`
185			`* Advanced HDL Synthesis *`
186			`=========================================================================`
187
188			`Analyzing FSM for best encoding.`
189			`Optimizing FSM on signal with gray encoding.`
190			`-------------------`
191			`State \| Encoding`
192			`-------------------`
193			`s0 \| 00`
194			`s1 \| 01`
195			`s2 \| 11`
196	4	leonardoar	`s3 \| 10`
197	2	leonardoar	`-------------------`
198			`Analyzing FSM for best encoding.`
199			`Optimizing FSM on signal with one-hot encoding.`
200			`-----------------------`
201			`State \| Encoding`
202			`-----------------------`
203	15	leonardoar	`bit0 \| 0000000001`
204			`bit1 \| 0000000010`
205			`bit2 \| 0000000100`
206			`bit3 \| 0000001000`
207			`bit4 \| 0000010000`
208			`bit5 \| 0000100000`
209			`bit6 \| 0001000000`
210			`bit7 \| 0010000000`
211			`rx_stop \| 0100000000`
212			`rx_idle \| 1000000000`
213	2	leonardoar	`-----------------------`
214
215			`=========================================================================`
216			`Advanced HDL Synthesis Report`
217
218			`Macro Statistics`
219			`# FSMs : 2`
220	15	leonardoar	`# Registers : 18`
221			`Flip-Flops : 18`
222	2	leonardoar
223			`=========================================================================`
224
225			`=========================================================================`
226			`* Low Level Synthesis *`
227			`=========================================================================`
228	15	leonardoar	`INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed :`
229	2	leonardoar
230			`Optimizing unit ...`
231
232			`Mapping all equations...`
233			`Building and optimizing final netlist ...`
234			`Found area constraint ratio of 100 (+ 5) on block serial_receiver, actual ratio is 0.`
235
236			`Final Macro Processing ...`
237
238			`=========================================================================`
239			`Final Register Report`
240
241			`Macro Statistics`
242	15	leonardoar	`# Registers : 29`
243			`Flip-Flops : 29`
244	2	leonardoar
245			`=========================================================================`
246
247			`=========================================================================`
248			`* Partition Report *`
249			`=========================================================================`
250
251			`Partition Implementation Status`
252			`-------------------------------`
253
254			`No Partitions were found in this design.`
255
256			`-------------------------------`
257
258			`=========================================================================`
259			`* Final Report *`
260			`=========================================================================`
261			`Final Results`
262			`RTL Top Level Output File Name : serial_receiver.ngr`
263			`Top Level Output File Name : serial_receiver`
264			`Output Format : NGC`
265			`Optimization Goal : Speed`
266			`Keep Hierarchy : No`
267
268			`Design Statistics`
269			`# IOs : 13`
270
271			`Cell Usage :`
272	15	leonardoar	`# BELS : 19`
273	4	leonardoar	`# GND : 1`
274	15	leonardoar	`# INV : 1`
275			`# LUT2 : 1`
276			`# LUT2_L : 1`
277			`# LUT3 : 1`
278			`# LUT3_D : 1`
279			`# LUT4 : 11`
280			`# LUT4_D : 1`
281	4	leonardoar	`# VCC : 1`
282	15	leonardoar	`# FlipFlops/Latches : 29`
283	4	leonardoar	`# FDC : 11`
284	15	leonardoar	`# FDCE : 9`
285			`# FDE : 8`
286	2	leonardoar	`# FDP : 1`
287			`# Clock Buffers : 2`
288			`# BUFGP : 2`
289			`# IO Buffers : 11`
290			`# IBUF : 2`
291			`# OBUF : 9`
292			`=========================================================================`
293
294			`Device utilization summary:`
295			`---------------------------`
296
297			`Selected Device : 3s500efg320-4`
298
299	15	leonardoar	`Number of Slices: 19 out of 4656 0%`
300	4	leonardoar	`Number of Slice Flip Flops: 29 out of 9312 0%`
301	15	leonardoar	`Number of 4 input LUTs: 17 out of 9312 0%`
302	2	leonardoar	`Number of IOs: 13`
303			`Number of bonded IOBs: 13 out of 232 5%`
304			`Number of GCLKs: 2 out of 24 8%`
305
306			`---------------------------`
307			`Partition Resource Summary:`
308			`---------------------------`
309
310			`No Partitions were found in this design.`
311
312			`---------------------------`
313
314
315			`=========================================================================`
316			`TIMING REPORT`
317
318			`NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.`
319			`FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT`
320			`GENERATED AFTER PLACE-and-ROUTE.`
321
322			`Clock Information:`
323			`------------------`
324	15	leonardoar	`-----------------------------------+------------------------+-------+`
325			`Clock Signal \| Clock buffer(FF name) \| Load \|`
326			`-----------------------------------+------------------------+-------+`
327			`baudOverSampleClk \| BUFGP \| 3 \|`
328			`baudClk \| BUFGP \| 26 \|`
329			`-----------------------------------+------------------------+-------+`
330	2	leonardoar
331			`Asynchronous Control Signals Information:`
332			`----------------------------------------`
333	15	leonardoar	`---------------------------------------------------------------+------------------------+-------+`
334			`Control Signal \| Buffer(FF name) \| Load \|`
335			`---------------------------------------------------------------+------------------------+-------+`
336			`current_s_FSM_Acst_FSM_inv(current_s_FSM_Acst_FSM_inv1_INV_0:O)\| NONE(byteReceived_0) \| 18 \|`
337			`rst \| IBUF \| 3 \|`
338			`---------------------------------------------------------------+------------------------+-------+`
339	2	leonardoar
340			`Timing Summary:`
341			`---------------`
342			`Speed Grade: -4`
343
344	15	leonardoar	`Minimum period: 4.853ns (Maximum Frequency: 206.058MHz)`
345			`Minimum input arrival time before clock: 4.569ns`
346			`Maximum output required time after clock: 4.450ns`
347	2	leonardoar	`Maximum combinational path delay: No path found`
348
349			`Timing Detail:`
350			`--------------`
351			`All values displayed in nanoseconds (ns)`
352
353			`=========================================================================`
354			`Timing constraint: Default period analysis for Clock 'baudOverSampleClk'`
355	15	leonardoar	`Clock period: 2.489ns (frequency: 401.768MHz)`
356	4	leonardoar	`Total number of paths / destination ports: 6 / 3`
357	2	leonardoar	`-------------------------------------------------------------------------`
358	15	leonardoar	`Delay: 2.489ns (Levels of Logic = 1)`
359			`Source: syncDetected (FF)`
360			`Destination: syncDetected (FF)`
361	2	leonardoar	`Source Clock: baudOverSampleClk rising`
362			`Destination Clock: baudOverSampleClk rising`
363
364	15	leonardoar	`Data Path: syncDetected to syncDetected`
365	2	leonardoar	`Gate Net`
366			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
367			`---------------------------------------- ------------`
368	15	leonardoar	`FDC:C->Q 10 0.591 0.886 syncDetected (syncDetected)`
369			`LUT4:I3->O 1 0.704 0.000 syncDetected_mux00001 (syncDetected_mux0000)`
370			`FDC:D 0.308 syncDetected`
371	2	leonardoar	`----------------------------------------`
372	15	leonardoar	`Total 2.489ns (1.603ns logic, 0.886ns route)`
373			`(64.4% logic, 35.6% route)`
374	2	leonardoar
375			`=========================================================================`
376			`Timing constraint: Default period analysis for Clock 'baudClk'`
377	15	leonardoar	`Clock period: 4.853ns (frequency: 206.058MHz)`
378			`Total number of paths / destination ports: 113 / 25`
379	2	leonardoar	`-------------------------------------------------------------------------`
380	15	leonardoar	`Delay: 4.853ns (Levels of Logic = 3)`
381			`Source: current_s_FSM_FFd7 (FF)`
382			`Destination: data_byte_0 (FF)`
383	2	leonardoar	`Source Clock: baudClk rising`
384			`Destination Clock: baudClk rising`
385
386	15	leonardoar	`Data Path: current_s_FSM_FFd7 to data_byte_0`
387	2	leonardoar	`Gate Net`
388			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
389			`---------------------------------------- ------------`
390	15	leonardoar	`FDC:C->Q 3 0.591 0.706 current_s_FSM_FFd7 (current_s_FSM_FFd7)`
391			`LUT4:I0->O 1 0.704 0.424 data_byte_mux0000<0>1_SW0 (N5)`
392			`LUT4_D:I3->O 7 0.704 0.712 data_byte_mux0000<0>1 (N01)`
393			`LUT4:I3->O 1 0.704 0.000 data_byte_mux0000<6>1 (data_byte_mux0000<6>)`
394			`FDE:D 0.308 data_byte_6`
395	2	leonardoar	`----------------------------------------`
396	15	leonardoar	`Total 4.853ns (3.011ns logic, 1.842ns route)`
397			`(62.0% logic, 38.0% route)`
398	2	leonardoar
399			`=========================================================================`
400			`Timing constraint: Default OFFSET IN BEFORE for Clock 'baudOverSampleClk'`
401			`Total number of paths / destination ports: 3 / 3`
402			`-------------------------------------------------------------------------`
403	15	leonardoar	`Offset: 3.366ns (Levels of Logic = 2)`
404	2	leonardoar	`Source: serial_in (PAD)`
405	15	leonardoar	`Destination: filterRx_FSM_FFd2 (FF)`
406	2	leonardoar	`Destination Clock: baudOverSampleClk rising`
407
408	15	leonardoar	`Data Path: serial_in to filterRx_FSM_FFd2`
409	2	leonardoar	`Gate Net`
410			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
411			`---------------------------------------- ------------`
412	15	leonardoar	`IBUF:I->O 12 1.218 1.136 serial_in_IBUF (serial_in_IBUF)`
413	2	leonardoar	`LUT2:I0->O 1 0.704 0.000 filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In)`
414			`FDC:D 0.308 filterRx_FSM_FFd2`
415			`----------------------------------------`
416	15	leonardoar	`Total 3.366ns (2.230ns logic, 1.136ns route)`
417			`(66.3% logic, 33.7% route)`
418	2	leonardoar
419			`=========================================================================`
420	15	leonardoar	`Timing constraint: Default OFFSET IN BEFORE for Clock 'baudClk'`
421			`Total number of paths / destination ports: 9 / 9`
422	2	leonardoar	`-------------------------------------------------------------------------`
423	15	leonardoar	`Offset: 4.569ns (Levels of Logic = 3)`
424	2	leonardoar	`Source: serial_in (PAD)`
425	15	leonardoar	`Destination: data_byte_7 (FF)`
426			`Destination Clock: baudClk rising`
427	2	leonardoar
428	15	leonardoar	`Data Path: serial_in to data_byte_7`
429	2	leonardoar	`Gate Net`
430			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
431			`---------------------------------------- ------------`
432	15	leonardoar	`IBUF:I->O 12 1.218 1.136 serial_in_IBUF (serial_in_IBUF)`
433			`LUT4:I0->O 1 0.704 0.499 data_byte_mux0000<7>_SW0 (N3)`
434			`LUT3:I1->O 1 0.704 0.000 data_byte_mux0000<7> (data_byte_mux0000<7>)`
435			`FDE:D 0.308 data_byte_7`
436	2	leonardoar	`----------------------------------------`
437	15	leonardoar	`Total 4.569ns (2.934ns logic, 1.635ns route)`
438			`(64.2% logic, 35.8% route)`
439	2	leonardoar
440			`=========================================================================`
441			`Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk'`
442	15	leonardoar	`Total number of paths / destination ports: 9 / 9`
443	2	leonardoar	`-------------------------------------------------------------------------`
444	15	leonardoar	`Offset: 4.450ns (Levels of Logic = 1)`
445	2	leonardoar	`Source: current_s_FSM_FFd1 (FF)`
446			`Destination: data_ready (PAD)`
447			`Source Clock: baudClk rising`
448
449			`Data Path: current_s_FSM_FFd1 to data_ready`
450			`Gate Net`
451			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
452			`---------------------------------------- ------------`
453	15	leonardoar	`FDCE:C->Q 4 0.591 0.587 current_s_FSM_FFd1 (current_s_FSM_FFd1)`
454	2	leonardoar	`OBUF:I->O 3.272 data_ready_OBUF (data_ready)`
455			`----------------------------------------`
456	15	leonardoar	`Total 4.450ns (3.863ns logic, 0.587ns route)`
457			`(86.8% logic, 13.2% route)`
458	2	leonardoar
459			`=========================================================================`
460
461
462	15	leonardoar	`Total REAL time to Xst completion: 5.00 secs`
463			`Total CPU time to Xst completion: 4.59 secs`
464	2	leonardoar
465			`-->`
466
467
468	15	leonardoar	`Total memory usage is 164420 kilobytes`
469
470	2	leonardoar	`Number of errors : 0 ( 0 filtered)`
471	15	leonardoar	`Number of warnings : 0 ( 0 filtered)`
472			`Number of infos : 1 ( 0 filtered)`
473	2	leonardoar

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