URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [serial_receiver.syr] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log


Release 13.4 - xst O.87xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
 
--> Parameter xsthdpdir set to xst
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
 
--> Reading design: serial_receiver.prj
 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT
 
 
=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "serial_receiver.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
 
---- Target Parameters
Output File Name                   : "serial_receiver"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320
 
---- Source Options
Top Module Name                    : serial_receiver
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No
 
---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES
 
---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5
 
=========================================================================
 
 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
Architecture pkgdefinitions of Entity pkgdefinitions is up to date.
Compiling vhdl file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" in Library work.
Entity  compiled.
Entity  (Architecture ) compiled.
 
=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity  in library  (architecture ).
 
 
=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity  in library  (Architecture ).
WARNING:Xst:819 - "E:/uart_block/hdl/iseProject/serial_receiver.vhd" line 86: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   
Entity  analyzed. Unit  generated.
 
 
=========================================================================
*                           HDL Synthesis                               *
=========================================================================
 
Performing bidirectional port resolution...
 
Synthesizing Unit .
    Related source file is "E:/uart_block/hdl/iseProject/serial_receiver.vhd".
    Found finite state machine  for signal .
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 10                                             |
    | Inputs             | 0                                              |
    | Outputs            | 10                                             |
    | Clock              | baudClk                   (rising_edge)        |
    | Reset              | syncDetected              (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | rx_idle                                        |
    | Power Up State     | rx_idle                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine  for signal .
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 8                                              |
    | Inputs             | 2                                              |
    | Outputs            | 4                                              |
    | Clock              | baudOverSampleClk         (rising_edge)        |
    | Reset              | rst                       (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | s0                                             |
    | Power Up State     | s0                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
    Found 8-bit tristate buffer for signal .
    Found 1-bit register for signal .
    Summary:
        inferred   2 Finite State Machine(s).
        inferred   1 D-type flip-flop(s).
        inferred   8 Tristate(s).
Unit  synthesized.
 
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# Registers                                            : 1
 1-bit register                                        : 1
# Latches                                              : 17
 1-bit latch                                           : 16
 8-bit latch                                           : 1
# Tristates                                            : 8
 1-bit tristate buffer                                 : 8
 
=========================================================================
 
=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
 
Analyzing FSM  for best encoding.
Optimizing FSM  on signal  with gray encoding.
-------------------
 State | Encoding
-------------------
 s0    | 00
 s1    | 01
 s2    | 11
 s3    | 10
-------------------
Analyzing FSM  for best encoding.
Optimizing FSM  on signal  with one-hot encoding.
-----------------------
 State   | Encoding
-----------------------
 rx_idle | 0000000001
 bit0    | 0000000010
 bit1    | 0000000100
 bit2    | 0000001000
 bit3    | 0000010000
 bit4    | 0000100000
 bit5    | 0001000000
 bit6    | 0010000000
 bit7    | 0100000000
 rx_stop | 1000000000
-----------------------
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# FSMs                                                 : 2
# Registers                                            : 1
 Flip-Flops                                            : 1
# Latches                                              : 17
 1-bit latch                                           : 16
 8-bit latch                                           : 1
 
=========================================================================
 
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:2042 - Unit serial_receiver: 8 internal tristates are replaced by logic (pull-up yes): byteReceived<0>, byteReceived<1>, byteReceived<2>, byteReceived<3>, byteReceived<4>, byteReceived<5>, byteReceived<6>, byteReceived<7>.
 
Optimizing unit  ...
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block serial_receiver, actual ratio is 0.
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers                                            : 13
 Flip-Flops                                            : 13
 
=========================================================================
 
=========================================================================
*                           Partition Report                            *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : serial_receiver.ngr
Top Level Output File Name         : serial_receiver
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No
 
Design Statistics
# IOs                              : 13
 
Cell Usage :
# BELS                             : 39
#      GND                         : 1
#      INV                         : 3
#      LUT2                        : 12
#      LUT3                        : 8
#      LUT4                        : 14
#      VCC                         : 1
# FlipFlops/Latches                : 37
#      FDC                         : 11
#      FDCE                        : 1
#      FDP                         : 1
#      LD                          : 17
#      LDE                         : 7
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 11
#      IBUF                        : 2
#      OBUF                        : 9
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 3s500efg320-4
 
 Number of Slices:                       20  out of   4656     0%
 Number of Slice Flip Flops:             29  out of   9312     0%
 Number of 4 input LUTs:                 37  out of   9312     0%
 Number of IOs:                          13
 Number of bonded IOBs:                  13  out of    232     5%
    IOB Flip Flops:                       8
 Number of GCLKs:                         2  out of     24     8%
 
---------------------------
Partition Resource Summary:
---------------------------
 
  No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------------------------------------+--------------------------------+-------+
Clock Signal                                                     | Clock buffer(FF name)          | Load  |
-----------------------------------------------------------------+--------------------------------+-------+
baudOverSampleClk                                                | BUFGP                          | 3     |
current_s_FSM_FFd8                                               | NONE(Mtridata_byteReceived<7>) | 7     |
Mtrien_byteReceived<7>_not0001(Mtrien_byteReceived<7>_not00011:O)| NONE(*)(Mtrien_byteReceived<7>)| 1     |
Mtrien_byteReceived<6>_not0001(Mtrien_byteReceived<6>_not0001:O) | NONE(*)(Mtrien_byteReceived<6>)| 1     |
Mtrien_byteReceived<5>_not0001(Mtrien_byteReceived<5>_not00011:O)| NONE(*)(Mtrien_byteReceived<5>)| 1     |
Mtrien_byteReceived<4>_not0001(Mtrien_byteReceived<4>_not0001:O) | NONE(*)(Mtrien_byteReceived<4>)| 1     |
Mtrien_byteReceived<3>_not0001(Mtrien_byteReceived<3>_not00011:O)| NONE(*)(Mtrien_byteReceived<3>)| 1     |
Mtrien_byteReceived<2>_not0001(Mtrien_byteReceived<2>_not00011:O)| NONE(*)(Mtrien_byteReceived<2>)| 1     |
Mtrien_byteReceived<1>_not0001(Mtrien_byteReceived<1>_not00011:O)| NONE(*)(Mtrien_byteReceived<1>)| 1     |
Mtrien_byteReceived<0>_not0001(Mtrien_byteReceived<0>_not00011:O)| NONE(*)(Mtrien_byteReceived<0>)| 1     |
current_s_FSM_FFd9                                               | NONE(Mtridata_byteReceived<0>) | 1     |
baudClk                                                          | BUFGP                          | 10    |
current_s_FSM_FFd1                                               | NONE(data_byte_0)              | 8     |
-----------------------------------------------------------------+--------------------------------+-------+
(*) These 8 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
 
Asynchronous Control Signals Information:
----------------------------------------
---------------------------------------------------------------+-------------------------+-------+
Control Signal                                                 | Buffer(FF name)         | Load  |
---------------------------------------------------------------+-------------------------+-------+
current_s_FSM_Acst_FSM_inv(current_s_FSM_Acst_FSM_inv1_INV_0:O)| NONE(current_s_FSM_FFd1)| 10    |
rst                                                            | IBUF                    | 3     |
---------------------------------------------------------------+-------------------------+-------+
 
Timing Summary:
---------------
Speed Grade: -4
 
   Minimum period: 2.213ns (Maximum Frequency: 451.875MHz)
   Minimum input arrival time before clock: 5.900ns
   Maximum output required time after clock: 4.745ns
   Maximum combinational path delay: No path found
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'baudOverSampleClk'
  Clock period: 2.213ns (frequency: 451.875MHz)
  Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Delay:               2.213ns (Levels of Logic = 1)
  Source:            filterRx_FSM_FFd1 (FF)
  Destination:       filterRx_FSM_FFd2 (FF)
  Source Clock:      baudOverSampleClk rising
  Destination Clock: baudOverSampleClk rising
 
  Data Path: filterRx_FSM_FFd1 to filterRx_FSM_FFd2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.591   0.610  filterRx_FSM_FFd1 (filterRx_FSM_FFd1)
     LUT2:I1->O            1   0.704   0.000  filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In)
     FDC:D                     0.308          filterRx_FSM_FFd2
    ----------------------------------------
    Total                      2.213ns (1.603ns logic, 0.610ns route)
                                       (72.4% logic, 27.6% route)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'current_s_FSM_FFd8'
  Clock period: 2.170ns (frequency: 460.829MHz)
  Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Delay:               2.170ns (Levels of Logic = 1)
  Source:            Mtridata_byteReceived<7> (LATCH)
  Destination:       Mtridata_byteReceived<7> (LATCH)
  Source Clock:      current_s_FSM_FFd8 rising
  Destination Clock: current_s_FSM_FFd8 rising
 
  Data Path: Mtridata_byteReceived<7> to Mtridata_byteReceived<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              2   0.676   0.482  Mtridata_byteReceived<7> (Mtridata_byteReceived<7>)
     LUT3:I2->O            1   0.704   0.000  Mtridata_byteReceived<7>_mux00001 (Mtridata_byteReceived<7>_mux0000)
     LDE:D                     0.308          Mtridata_byteReceived<7>
    ----------------------------------------
    Total                      2.170ns (1.688ns logic, 0.482ns route)
                                       (77.8% logic, 22.2% route)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'baudClk'
  Clock period: 1.950ns (frequency: 512.821MHz)
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Delay:               1.950ns (Levels of Logic = 0)
  Source:            current_s_FSM_FFd10 (FF)
  Destination:       current_s_FSM_FFd9 (FF)
  Source Clock:      baudClk rising
  Destination Clock: baudClk rising
 
  Data Path: current_s_FSM_FFd10 to current_s_FSM_FFd9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q             17   0.591   1.051  current_s_FSM_FFd10 (current_s_FSM_FFd10)
     FDC:D                     0.308          current_s_FSM_FFd9
    ----------------------------------------
    Total                      1.950ns (0.899ns logic, 1.051ns route)
                                       (46.1% logic, 53.9% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'baudOverSampleClk'
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset:              3.287ns (Levels of Logic = 2)
  Source:            serial_in (PAD)
  Destination:       syncDetected (FF)
  Destination Clock: baudOverSampleClk rising
 
  Data Path: serial_in to syncDetected
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   1.218   1.057  serial_in_IBUF (serial_in_IBUF)
     LUT2:I0->O            1   0.704   0.000  filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In)
     FDC:D                     0.308          filterRx_FSM_FFd2
    ----------------------------------------
    Total                      3.287ns (2.230ns logic, 1.057ns route)
                                       (67.8% logic, 32.2% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd8'
  Total number of paths / destination ports: 8 / 7
-------------------------------------------------------------------------
Offset:              5.900ns (Levels of Logic = 4)
  Source:            serial_in (PAD)
  Destination:       Mtridata_byteReceived<6> (LATCH)
  Destination Clock: current_s_FSM_FFd8 rising
 
  Data Path: serial_in to Mtridata_byteReceived<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   1.218   1.057  serial_in_IBUF (serial_in_IBUF)
     LUT3:I0->O            3   0.704   0.610  Mtridata_byteReceived<6>_mux000021 (N8)
     LUT3:I1->O            1   0.704   0.595  Mtridata_byteReceived<6>_mux0000_SW0 (N17)
     LUT4:I0->O            1   0.704   0.000  Mtridata_byteReceived<6>_mux0000 (Mtridata_byteReceived<6>_mux0000)
     LDE:D                     0.308          Mtridata_byteReceived<6>
    ----------------------------------------
    Total                      5.900ns (3.638ns logic, 2.262ns route)
                                       (61.7% logic, 38.3% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd9'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              2.408ns (Levels of Logic = 1)
  Source:            serial_in (PAD)
  Destination:       Mtridata_byteReceived<0> (LATCH)
  Destination Clock: current_s_FSM_FFd9 falling
 
  Data Path: serial_in to Mtridata_byteReceived<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            10   1.218   0.882  serial_in_IBUF (serial_in_IBUF)
     LD:D                      0.308          Mtridata_byteReceived<0>
    ----------------------------------------
    Total                      2.408ns (1.526ns logic, 0.882ns route)
                                       (63.4% logic, 36.6% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.745ns (Levels of Logic = 1)
  Source:            current_s_FSM_FFd1 (FF)
  Destination:       data_ready (PAD)
  Source Clock:      baudClk rising
 
  Data Path: current_s_FSM_FFd1 to data_ready
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            10   0.591   0.882  current_s_FSM_FFd1 (current_s_FSM_FFd1)
     OBUF:I->O                 3.272          data_ready_OBUF (data_ready)
    ----------------------------------------
    Total                      4.745ns (3.863ns logic, 0.882ns route)
                                       (81.4% logic, 18.6% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd1'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              4.368ns (Levels of Logic = 1)
  Source:            data_byte_7 (LATCH)
  Destination:       data_byte<7> (PAD)
  Source Clock:      current_s_FSM_FFd1 falling
 
  Data Path: data_byte_7 to data_byte<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.676   0.420  data_byte_7 (data_byte_7)
     OBUF:I->O                 3.272          data_byte_7_OBUF (data_byte<7>)
    ----------------------------------------
    Total                      4.368ns (3.948ns logic, 0.420ns route)
                                       (90.4% logic, 9.6% route)
 
=========================================================================
 
 
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.32 secs
 
-->
 
Total memory usage is 258164 kilobytes
 
Number of errors   :    0 (   0 filtered)
Number of warnings :   19 (   0 filtered)
Number of infos    :    9 (   0 filtered)
 

Line No.	Rev	Author	Line
1	2	leonardoar	`Release 13.4 - xst O.87xd (nt64)`
2			`Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.`
3			`--> Parameter TMPDIR set to xst/projnav.tmp`
4
5
6			`Total REAL time to Xst completion: 0.00 secs`
7			`Total CPU time to Xst completion: 0.05 secs`
8
9			`--> Parameter xsthdpdir set to xst`
10
11
12			`Total REAL time to Xst completion: 0.00 secs`
13			`Total CPU time to Xst completion: 0.05 secs`
14
15			`--> Reading design: serial_receiver.prj`
16
17			`TABLE OF CONTENTS`
18			`1) Synthesis Options Summary`
19			`2) HDL Compilation`
20			`3) Design Hierarchy Analysis`
21			`4) HDL Analysis`
22			`5) HDL Synthesis`
23			`5.1) HDL Synthesis Report`
24			`6) Advanced HDL Synthesis`
25			`6.1) Advanced HDL Synthesis Report`
26			`7) Low Level Synthesis`
27			`8) Partition Report`
28			`9) Final Report`
29			`9.1) Device utilization summary`
30			`9.2) Partition Resource Summary`
31			`9.3) TIMING REPORT`
32
33
34			`=========================================================================`
35			`* Synthesis Options Summary *`
36			`=========================================================================`
37			`---- Source Parameters`
38			`Input File Name : "serial_receiver.prj"`
39			`Input Format : mixed`
40			`Ignore Synthesis Constraint File : NO`
41
42			`---- Target Parameters`
43			`Output File Name : "serial_receiver"`
44			`Output Format : NGC`
45			`Target Device : xc3s500e-4-fg320`
46
47			`---- Source Options`
48			`Top Module Name : serial_receiver`
49			`Automatic FSM Extraction : YES`
50			`FSM Encoding Algorithm : Auto`
51			`Safe Implementation : No`
52			`FSM Style : LUT`
53			`RAM Extraction : Yes`
54			`RAM Style : Auto`
55			`ROM Extraction : Yes`
56			`Mux Style : Auto`
57			`Decoder Extraction : YES`
58			`Priority Encoder Extraction : Yes`
59			`Shift Register Extraction : YES`
60			`Logical Shifter Extraction : YES`
61			`XOR Collapsing : YES`
62			`ROM Style : Auto`
63			`Mux Extraction : Yes`
64			`Resource Sharing : YES`
65			`Asynchronous To Synchronous : NO`
66			`Multiplier Style : Auto`
67			`Automatic Register Balancing : No`
68
69			`---- Target Options`
70			`Add IO Buffers : YES`
71			`Global Maximum Fanout : 100000`
72			`Add Generic Clock Buffer(BUFG) : 24`
73			`Register Duplication : YES`
74			`Slice Packing : YES`
75			`Optimize Instantiated Primitives : NO`
76			`Use Clock Enable : Yes`
77			`Use Synchronous Set : Yes`
78			`Use Synchronous Reset : Yes`
79			`Pack IO Registers into IOBs : Auto`
80			`Equivalent register Removal : YES`
81
82			`---- General Options`
83			`Optimization Goal : Speed`
84			`Optimization Effort : 1`
85			`Keep Hierarchy : No`
86			`Netlist Hierarchy : As_Optimized`
87			`RTL Output : Yes`
88			`Global Optimization : AllClockNets`
89			`Read Cores : YES`
90			`Write Timing Constraints : NO`
91			`Cross Clock Analysis : NO`
92			`Hierarchy Separator : /`
93			`Bus Delimiter : <>`
94			`Case Specifier : Maintain`
95			`Slice Utilization Ratio : 100`
96			`BRAM Utilization Ratio : 100`
97			`Verilog 2001 : YES`
98			`Auto BRAM Packing : NO`
99			`Slice Utilization Ratio Delta : 5`
100
101			`=========================================================================`
102
103
104			`=========================================================================`
105			`* HDL Compilation *`
106			`=========================================================================`
107			`Compiling vhdl file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.`
108			`Architecture pkgdefinitions of Entity pkgdefinitions is up to date.`
109			`Compiling vhdl file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" in Library work.`
110			`Entity compiled.`
111			`Entity (Architecture ) compiled.`
112
113			`=========================================================================`
114			`* Design Hierarchy Analysis *`
115			`=========================================================================`
116			`Analyzing hierarchy for entity in library (architecture ).`
117
118
119			`=========================================================================`
120			`* HDL Analysis *`
121			`=========================================================================`
122			`Analyzing Entity in library (Architecture ).`
123	4	leonardoar	`WARNING:Xst:819 - "E:/uart_block/hdl/iseProject/serial_receiver.vhd" line 86: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:`
124	2	leonardoar
125			`Entity analyzed. Unit generated.`
126
127
128			`=========================================================================`
129			`* HDL Synthesis *`
130			`=========================================================================`
131
132			`Performing bidirectional port resolution...`
133
134			`Synthesizing Unit .`
135			`Related source file is "E:/uart_block/hdl/iseProject/serial_receiver.vhd".`
136			`Found finite state machine for signal .`
137			`-----------------------------------------------------------------------`
138			`\| States \| 10 \|`
139			`\| Transitions \| 10 \|`
140			`\| Inputs \| 0 \|`
141	4	leonardoar	`\| Outputs \| 10 \|`
142	2	leonardoar	`\| Clock \| baudClk (rising_edge) \|`
143			`\| Reset \| syncDetected (negative) \|`
144			`\| Reset type \| asynchronous \|`
145			`\| Reset State \| rx_idle \|`
146			`\| Power Up State \| rx_idle \|`
147			`\| Encoding \| automatic \|`
148			`\| Implementation \| LUT \|`
149			`-----------------------------------------------------------------------`
150			`Found finite state machine for signal .`
151			`-----------------------------------------------------------------------`
152	4	leonardoar	`\| States \| 4 \|`
153			`\| Transitions \| 8 \|`
154			`\| Inputs \| 2 \|`
155			`\| Outputs \| 4 \|`
156	2	leonardoar	`\| Clock \| baudOverSampleClk (rising_edge) \|`
157			`\| Reset \| rst (positive) \|`
158			`\| Reset type \| asynchronous \|`
159			`\| Reset State \| s0 \|`
160			`\| Power Up State \| s0 \|`
161			`\| Encoding \| automatic \|`
162			`\| Implementation \| LUT \|`
163			`-----------------------------------------------------------------------`
164	4	leonardoar	`WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
165			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
166			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
167			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
168			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
169			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
170			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
171			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
172			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
173			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
174			`INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.`
175			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
176			`INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.`
177			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
178			`INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.`
179			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
180			`INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.`
181			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
182			`INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.`
183			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
184			`INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.`
185			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
186			`INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.`
187			`WARNING:Xst:736 - Found 1-bit latch for signal > created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.`
188			`INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.`
189			`Found 8-bit tristate buffer for signal .`
190	2	leonardoar	`Found 1-bit register for signal .`
191			`Summary:`
192			`inferred 2 Finite State Machine(s).`
193			`inferred 1 D-type flip-flop(s).`
194	4	leonardoar	`inferred 8 Tristate(s).`
195	2	leonardoar	`Unit synthesized.`
196
197
198			`=========================================================================`
199			`HDL Synthesis Report`
200
201			`Macro Statistics`
202			`# Registers : 1`
203			`1-bit register : 1`
204	4	leonardoar	`# Latches : 17`
205			`1-bit latch : 16`
206			`8-bit latch : 1`
207			`# Tristates : 8`
208			`1-bit tristate buffer : 8`
209	2	leonardoar
210			`=========================================================================`
211
212			`=========================================================================`
213			`* Advanced HDL Synthesis *`
214			`=========================================================================`
215
216			`Analyzing FSM for best encoding.`
217			`Optimizing FSM on signal with gray encoding.`
218			`-------------------`
219			`State \| Encoding`
220			`-------------------`
221			`s0 \| 00`
222			`s1 \| 01`
223			`s2 \| 11`
224	4	leonardoar	`s3 \| 10`
225	2	leonardoar	`-------------------`
226			`Analyzing FSM for best encoding.`
227			`Optimizing FSM on signal with one-hot encoding.`
228			`-----------------------`
229			`State \| Encoding`
230			`-----------------------`
231			`rx_idle \| 0000000001`
232			`bit0 \| 0000000010`
233			`bit1 \| 0000000100`
234			`bit2 \| 0000001000`
235			`bit3 \| 0000010000`
236			`bit4 \| 0000100000`
237			`bit5 \| 0001000000`
238			`bit6 \| 0010000000`
239			`bit7 \| 0100000000`
240			`rx_stop \| 1000000000`
241			`-----------------------`
242
243			`=========================================================================`
244			`Advanced HDL Synthesis Report`
245
246			`Macro Statistics`
247			`# FSMs : 2`
248			`# Registers : 1`
249			`Flip-Flops : 1`
250	4	leonardoar	`# Latches : 17`
251			`1-bit latch : 16`
252			`8-bit latch : 1`
253	2	leonardoar
254			`=========================================================================`
255
256			`=========================================================================`
257			`* Low Level Synthesis *`
258			`=========================================================================`
259	4	leonardoar	`WARNING:Xst:2042 - Unit serial_receiver: 8 internal tristates are replaced by logic (pull-up yes): byteReceived<0>, byteReceived<1>, byteReceived<2>, byteReceived<3>, byteReceived<4>, byteReceived<5>, byteReceived<6>, byteReceived<7>.`
260	2	leonardoar
261			`Optimizing unit ...`
262
263			`Mapping all equations...`
264			`Building and optimizing final netlist ...`
265			`Found area constraint ratio of 100 (+ 5) on block serial_receiver, actual ratio is 0.`
266
267			`Final Macro Processing ...`
268
269			`=========================================================================`
270			`Final Register Report`
271
272			`Macro Statistics`
273			`# Registers : 13`
274			`Flip-Flops : 13`
275
276			`=========================================================================`
277
278			`=========================================================================`
279			`* Partition Report *`
280			`=========================================================================`
281
282			`Partition Implementation Status`
283			`-------------------------------`
284
285			`No Partitions were found in this design.`
286
287			`-------------------------------`
288
289			`=========================================================================`
290			`* Final Report *`
291			`=========================================================================`
292			`Final Results`
293			`RTL Top Level Output File Name : serial_receiver.ngr`
294			`Top Level Output File Name : serial_receiver`
295			`Output Format : NGC`
296			`Optimization Goal : Speed`
297			`Keep Hierarchy : No`
298
299			`Design Statistics`
300			`# IOs : 13`
301
302			`Cell Usage :`
303	4	leonardoar	`# BELS : 39`
304			`# GND : 1`
305			`# INV : 3`
306			`# LUT2 : 12`
307			`# LUT3 : 8`
308			`# LUT4 : 14`
309			`# VCC : 1`
310			`# FlipFlops/Latches : 37`
311			`# FDC : 11`
312			`# FDCE : 1`
313	2	leonardoar	`# FDP : 1`
314	4	leonardoar	`# LD : 17`
315			`# LDE : 7`
316	2	leonardoar	`# Clock Buffers : 2`
317			`# BUFGP : 2`
318			`# IO Buffers : 11`
319			`# IBUF : 2`
320			`# OBUF : 9`
321			`=========================================================================`
322
323			`Device utilization summary:`
324			`---------------------------`
325
326			`Selected Device : 3s500efg320-4`
327
328	4	leonardoar	`Number of Slices: 20 out of 4656 0%`
329			`Number of Slice Flip Flops: 29 out of 9312 0%`
330			`Number of 4 input LUTs: 37 out of 9312 0%`
331	2	leonardoar	`Number of IOs: 13`
332			`Number of bonded IOBs: 13 out of 232 5%`
333			`IOB Flip Flops: 8`
334			`Number of GCLKs: 2 out of 24 8%`
335
336			`---------------------------`
337			`Partition Resource Summary:`
338			`---------------------------`
339
340			`No Partitions were found in this design.`
341
342			`---------------------------`
343
344
345			`=========================================================================`
346			`TIMING REPORT`
347
348			`NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.`
349			`FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT`
350			`GENERATED AFTER PLACE-and-ROUTE.`
351
352			`Clock Information:`
353			`------------------`
354	4	leonardoar	`-----------------------------------------------------------------+--------------------------------+-------+`
355			`Clock Signal \| Clock buffer(FF name) \| Load \|`
356			`-----------------------------------------------------------------+--------------------------------+-------+`
357			`baudOverSampleClk \| BUFGP \| 3 \|`
358			`current_s_FSM_FFd8 \| NONE(Mtridata_byteReceived<7>) \| 7 \|`
359			`Mtrien_byteReceived<7>_not0001(Mtrien_byteReceived<7>_not00011:O)\| NONE(*)(Mtrien_byteReceived<7>)\| 1 \|`
360			`Mtrien_byteReceived<6>_not0001(Mtrien_byteReceived<6>_not0001:O) \| NONE(*)(Mtrien_byteReceived<6>)\| 1 \|`
361			`Mtrien_byteReceived<5>_not0001(Mtrien_byteReceived<5>_not00011:O)\| NONE(*)(Mtrien_byteReceived<5>)\| 1 \|`
362			`Mtrien_byteReceived<4>_not0001(Mtrien_byteReceived<4>_not0001:O) \| NONE(*)(Mtrien_byteReceived<4>)\| 1 \|`
363			`Mtrien_byteReceived<3>_not0001(Mtrien_byteReceived<3>_not00011:O)\| NONE(*)(Mtrien_byteReceived<3>)\| 1 \|`
364			`Mtrien_byteReceived<2>_not0001(Mtrien_byteReceived<2>_not00011:O)\| NONE(*)(Mtrien_byteReceived<2>)\| 1 \|`
365			`Mtrien_byteReceived<1>_not0001(Mtrien_byteReceived<1>_not00011:O)\| NONE(*)(Mtrien_byteReceived<1>)\| 1 \|`
366			`Mtrien_byteReceived<0>_not0001(Mtrien_byteReceived<0>_not00011:O)\| NONE(*)(Mtrien_byteReceived<0>)\| 1 \|`
367			`current_s_FSM_FFd9 \| NONE(Mtridata_byteReceived<0>) \| 1 \|`
368			`baudClk \| BUFGP \| 10 \|`
369			`current_s_FSM_FFd1 \| NONE(data_byte_0) \| 8 \|`
370			`-----------------------------------------------------------------+--------------------------------+-------+`
371			`(*) These 8 clock signal(s) are generated by combinatorial logic,`
372			`and XST is not able to identify which are the primary clock signals.`
373			`Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.`
374	2	leonardoar	`INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.`
375
376			`Asynchronous Control Signals Information:`
377			`----------------------------------------`
378			`---------------------------------------------------------------+-------------------------+-------+`
379			`Control Signal \| Buffer(FF name) \| Load \|`
380			`---------------------------------------------------------------+-------------------------+-------+`
381			`current_s_FSM_Acst_FSM_inv(current_s_FSM_Acst_FSM_inv1_INV_0:O)\| NONE(current_s_FSM_FFd1)\| 10 \|`
382			`rst \| IBUF \| 3 \|`
383			`---------------------------------------------------------------+-------------------------+-------+`
384
385			`Timing Summary:`
386			`---------------`
387			`Speed Grade: -4`
388
389			`Minimum period: 2.213ns (Maximum Frequency: 451.875MHz)`
390	4	leonardoar	`Minimum input arrival time before clock: 5.900ns`
391			`Maximum output required time after clock: 4.745ns`
392	2	leonardoar	`Maximum combinational path delay: No path found`
393
394			`Timing Detail:`
395			`--------------`
396			`All values displayed in nanoseconds (ns)`
397
398			`=========================================================================`
399			`Timing constraint: Default period analysis for Clock 'baudOverSampleClk'`
400			`Clock period: 2.213ns (frequency: 451.875MHz)`
401	4	leonardoar	`Total number of paths / destination ports: 6 / 3`
402	2	leonardoar	`-------------------------------------------------------------------------`
403			`Delay: 2.213ns (Levels of Logic = 1)`
404			`Source: filterRx_FSM_FFd1 (FF)`
405	4	leonardoar	`Destination: filterRx_FSM_FFd2 (FF)`
406	2	leonardoar	`Source Clock: baudOverSampleClk rising`
407			`Destination Clock: baudOverSampleClk rising`
408
409	4	leonardoar	`Data Path: filterRx_FSM_FFd1 to filterRx_FSM_FFd2`
410	2	leonardoar	`Gate Net`
411			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
412			`---------------------------------------- ------------`
413			`FDC:C->Q 3 0.591 0.610 filterRx_FSM_FFd1 (filterRx_FSM_FFd1)`
414			`LUT2:I1->O 1 0.704 0.000 filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In)`
415			`FDC:D 0.308 filterRx_FSM_FFd2`
416			`----------------------------------------`
417			`Total 2.213ns (1.603ns logic, 0.610ns route)`
418			`(72.4% logic, 27.6% route)`
419
420			`=========================================================================`
421	4	leonardoar	`Timing constraint: Default period analysis for Clock 'current_s_FSM_FFd8'`
422			`Clock period: 2.170ns (frequency: 460.829MHz)`
423			`Total number of paths / destination ports: 6 / 6`
424			`-------------------------------------------------------------------------`
425			`Delay: 2.170ns (Levels of Logic = 1)`
426			`Source: Mtridata_byteReceived<7> (LATCH)`
427			`Destination: Mtridata_byteReceived<7> (LATCH)`
428			`Source Clock: current_s_FSM_FFd8 rising`
429			`Destination Clock: current_s_FSM_FFd8 rising`
430
431			`Data Path: Mtridata_byteReceived<7> to Mtridata_byteReceived<7>`
432			`Gate Net`
433			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
434			`---------------------------------------- ------------`
435			`LDE:G->Q 2 0.676 0.482 Mtridata_byteReceived<7> (Mtridata_byteReceived<7>)`
436			`LUT3:I2->O 1 0.704 0.000 Mtridata_byteReceived<7>_mux00001 (Mtridata_byteReceived<7>_mux0000)`
437			`LDE:D 0.308 Mtridata_byteReceived<7>`
438			`----------------------------------------`
439			`Total 2.170ns (1.688ns logic, 0.482ns route)`
440			`(77.8% logic, 22.2% route)`
441
442			`=========================================================================`
443	2	leonardoar	`Timing constraint: Default period analysis for Clock 'baudClk'`
444	4	leonardoar	`Clock period: 1.950ns (frequency: 512.821MHz)`
445			`Total number of paths / destination ports: 9 / 9`
446	2	leonardoar	`-------------------------------------------------------------------------`
447	4	leonardoar	`Delay: 1.950ns (Levels of Logic = 0)`
448			`Source: current_s_FSM_FFd10 (FF)`
449			`Destination: current_s_FSM_FFd9 (FF)`
450	2	leonardoar	`Source Clock: baudClk rising`
451			`Destination Clock: baudClk rising`
452
453	4	leonardoar	`Data Path: current_s_FSM_FFd10 to current_s_FSM_FFd9`
454	2	leonardoar	`Gate Net`
455			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
456			`---------------------------------------- ------------`
457	4	leonardoar	`FDP:C->Q 17 0.591 1.051 current_s_FSM_FFd10 (current_s_FSM_FFd10)`
458			`FDC:D 0.308 current_s_FSM_FFd9`
459	2	leonardoar	`----------------------------------------`
460	4	leonardoar	`Total 1.950ns (0.899ns logic, 1.051ns route)`
461			`(46.1% logic, 53.9% route)`
462	2	leonardoar
463			`=========================================================================`
464			`Timing constraint: Default OFFSET IN BEFORE for Clock 'baudOverSampleClk'`
465			`Total number of paths / destination ports: 3 / 3`
466			`-------------------------------------------------------------------------`
467	4	leonardoar	`Offset: 3.287ns (Levels of Logic = 2)`
468	2	leonardoar	`Source: serial_in (PAD)`
469			`Destination: syncDetected (FF)`
470			`Destination Clock: baudOverSampleClk rising`
471
472			`Data Path: serial_in to syncDetected`
473			`Gate Net`
474			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
475			`---------------------------------------- ------------`
476	4	leonardoar	`IBUF:I->O 10 1.218 1.057 serial_in_IBUF (serial_in_IBUF)`
477	2	leonardoar	`LUT2:I0->O 1 0.704 0.000 filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In)`
478			`FDC:D 0.308 filterRx_FSM_FFd2`
479			`----------------------------------------`
480	4	leonardoar	`Total 3.287ns (2.230ns logic, 1.057ns route)`
481			`(67.8% logic, 32.2% route)`
482	2	leonardoar
483			`=========================================================================`
484			`Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd8'`
485	4	leonardoar	`Total number of paths / destination ports: 8 / 7`
486	2	leonardoar	`-------------------------------------------------------------------------`
487	4	leonardoar	`Offset: 5.900ns (Levels of Logic = 4)`
488	2	leonardoar	`Source: serial_in (PAD)`
489	4	leonardoar	`Destination: Mtridata_byteReceived<6> (LATCH)`
490			`Destination Clock: current_s_FSM_FFd8 rising`
491	2	leonardoar
492	4	leonardoar	`Data Path: serial_in to Mtridata_byteReceived<6>`
493	2	leonardoar	`Gate Net`
494			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
495			`---------------------------------------- ------------`
496	4	leonardoar	`IBUF:I->O 10 1.218 1.057 serial_in_IBUF (serial_in_IBUF)`
497			`LUT3:I0->O 3 0.704 0.610 Mtridata_byteReceived<6>_mux000021 (N8)`
498			`LUT3:I1->O 1 0.704 0.595 Mtridata_byteReceived<6>_mux0000_SW0 (N17)`
499			`LUT4:I0->O 1 0.704 0.000 Mtridata_byteReceived<6>_mux0000 (Mtridata_byteReceived<6>_mux0000)`
500			`LDE:D 0.308 Mtridata_byteReceived<6>`

Browse

Tools

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [serial_receiver.syr] - Blame information for rev 6