OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [serial_receiver.xst] - Blame information for rev 39

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 leonardoar
set -tmpdir "xst/projnav.tmp"
2
set -xsthdpdir "xst"
3
run
4
-ifn serial_receiver.prj
5
-ifmt mixed
6
-ofn serial_receiver
7
-ofmt NGC
8
-p xc3s500e-4-fg320
9
-top serial_receiver
10
-opt_mode Speed
11
-opt_level 1
12
-iuc NO
13
-keep_hierarchy No
14
-netlist_hierarchy As_Optimized
15
-rtlview Yes
16
-glob_opt AllClockNets
17
-read_cores YES
18
-write_timing_constraints NO
19
-cross_clock_analysis NO
20
-hierarchy_separator /
21
-bus_delimiter <>
22
-case Maintain
23
-slice_utilization_ratio 100
24
-bram_utilization_ratio 100
25
-verilog2001 YES
26
-fsm_extract YES -fsm_encoding Auto
27
-safe_implementation No
28
-fsm_style LUT
29
-ram_extract Yes
30
-ram_style Auto
31
-rom_extract Yes
32
-mux_style Auto
33
-decoder_extract YES
34
-priority_extract Yes
35
-shreg_extract YES
36
-shift_extract YES
37
-xor_collapse YES
38
-rom_style Auto
39
-auto_bram_packing NO
40
-mux_extract Yes
41
-resource_sharing YES
42
-async_to_sync NO
43
-mult_style Auto
44
-iobuf YES
45
-max_fanout 100000
46
-bufg 24
47
-register_duplication YES
48
-register_balancing No
49
-slice_packing YES
50
-optimize_primitives NO
51
-use_clock_enable Yes
52
-use_sync_set Yes
53
-use_sync_reset Yes
54
-iob Auto
55
-equivalent_register_removal YES
56
-slice_utilization_ratio_maxmargin 5

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.