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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [serial_transmitter.syr] - Blame information for rev 25

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Release 13.4 - xst O.87xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
 
-->
Parameter xsthdpdir set to xst
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
 
-->
Reading design: serial_transmitter.prj
 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT
 
 
=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "serial_transmitter.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
 
---- Target Parameters
Output File Name                   : "serial_transmitter"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320
 
---- Source Options
Top Module Name                    : serial_transmitter
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No
 
---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES
 
---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5
 
=========================================================================
 
 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.
Architecture pkgdefinitions of Entity pkgdefinitions is up to date.
Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" in Library work.
Architecture behavioral of Entity serial_transmitter is up to date.
 
=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity  in library  (architecture ).
 
 
=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity  in library  (Architecture ).
Entity  analyzed. Unit  generated.
 
 
=========================================================================
*                           HDL Synthesis                               *
=========================================================================
 
Performing bidirectional port resolution...
 
Synthesizing Unit .
    Related source file is "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd".
    Found finite state machine  for signal .
    -----------------------------------------------------------------------
    | States             | 12                                             |
    | Transitions        | 12                                             |
    | Inputs             | 0                                              |
    | Outputs            | 13                                             |
    | Clock              | baudClk                   (rising_edge)        |
    | Reset              | rst                       (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | tx_idle                                        |
    | Power Up State     | tx_idle                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
        inferred   1 Finite State Machine(s).
Unit  synthesized.
 
 
=========================================================================
HDL Synthesis Report
 
Found no macro
=========================================================================
 
=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================
 
Analyzing FSM  for best encoding.
Optimizing FSM  on signal  with one-hot encoding.
--------------------------
 State    | Encoding
--------------------------
 tx_idle  | 000000000001
 tx_start | 000000000010
 bit0     | 000000000100
 bit1     | 000000001000
 bit2     | 000000010000
 bit3     | 000000100000
 bit4     | 000001000000
 bit5     | 000010000000
 bit6     | 000100000000
 bit7     | 001000000000
 tx_stop1 | 010000000000
 tx_stop2 | 100000000000
--------------------------
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# FSMs                                                 : 1
 
=========================================================================
 
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
 
Optimizing unit  ...
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block serial_transmitter, actual ratio is 0.
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers                                            : 12
 Flip-Flops                                            : 12
 
=========================================================================
 
=========================================================================
*                           Partition Report                            *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : serial_transmitter.ngr
Top Level Output File Name         : serial_transmitter
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No
 
Design Statistics
# IOs                              : 12
 
Cell Usage :
# BELS                             : 9
#      GND                         : 1
#      LUT2                        : 1
#      LUT4                        : 6
#      VCC                         : 1
# FlipFlops/Latches                : 12
#      FDC                         : 10
#      FDCE                        : 1
#      FDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      IBUF                        : 9
#      OBUF                        : 2
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 3s500efg320-4
 
 Number of Slices:                        7  out of   4656     0%
 Number of Slice Flip Flops:             12  out of   9312     0%
 Number of 4 input LUTs:                  7  out of   9312     0%
 Number of IOs:                          12
 Number of bonded IOBs:                  12  out of    232     5%
 Number of GCLKs:                         1  out of     24     4%
 
---------------------------
Partition Resource Summary:
---------------------------
 
  No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
baudClk                            | BUFGP                  | 12    |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
rst                                | IBUF                   | 12    |
-----------------------------------+------------------------+-------+
 
Timing Summary:
---------------
Speed Grade: -4
 
   Minimum period: 1.677ns (Maximum Frequency: 596.303MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 8.036ns
   Maximum combinational path delay: 8.540ns
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'baudClk'
  Clock period: 1.677ns (frequency: 596.303MHz)
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Delay:               1.677ns (Levels of Logic = 0)
  Source:            current_s_FSM_FFd2 (FF)
  Destination:       current_s_FSM_FFd1 (FF)
  Source Clock:      baudClk rising
  Destination Clock: baudClk rising
 
  Data Path: current_s_FSM_FFd2 to current_s_FSM_FFd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.591   0.531  current_s_FSM_FFd2 (current_s_FSM_FFd2)
     FDCE:CE                   0.555          current_s_FSM_FFd1
    ----------------------------------------
    Total                      1.677ns (1.146ns logic, 0.531ns route)
                                       (68.3% logic, 31.7% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk'
  Total number of paths / destination ports: 13 / 2
-------------------------------------------------------------------------
Offset:              8.036ns (Levels of Logic = 4)
  Source:            current_s_FSM_FFd7 (FF)
  Destination:       serial_out (PAD)
  Source Clock:      baudClk rising
 
  Data Path: current_s_FSM_FFd7 to serial_out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.591   0.622  current_s_FSM_FFd7 (current_s_FSM_FFd7)
     LUT4:I0->O            1   0.704   0.595  serial_out12 (serial_out12)
     LUT4:I0->O            1   0.704   0.424  serial_out48_SW0 (N01)
     LUT4:I3->O            1   0.704   0.420  serial_out48 (serial_out_OBUF)
     OBUF:I->O                 3.272          serial_out_OBUF (serial_out)
    ----------------------------------------
    Total                      8.036ns (5.975ns logic, 2.061ns route)
                                       (74.4% logic, 25.6% route)
 
=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 8 / 1
-------------------------------------------------------------------------
Delay:               8.540ns (Levels of Logic = 5)
  Source:            data_byte<3> (PAD)
  Destination:       serial_out (PAD)
 
  Data Path: data_byte<3> to serial_out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.218   0.499  data_byte_3_IBUF (data_byte_3_IBUF)
     LUT4:I1->O            1   0.704   0.595  serial_out12 (serial_out12)
     LUT4:I0->O            1   0.704   0.424  serial_out48_SW0 (N01)
     LUT4:I3->O            1   0.704   0.420  serial_out48 (serial_out_OBUF)
     OBUF:I->O                 3.272          serial_out_OBUF (serial_out)
    ----------------------------------------
    Total                      8.540ns (6.602ns logic, 1.938ns route)
                                       (77.3% logic, 22.7% route)
 
=========================================================================
 
 
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.47 secs
 
-->
 
 
Total memory usage is 163788 kilobytes
 
Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
 

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Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [serial_transmitter.syr] - Blame information for rev 25

Line No.	Rev	Author	Line
1	15	leonardoar	`Release 13.4 - xst O.87xd (lin)`
2	2	leonardoar	`Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.`
3	15	leonardoar	`-->`
4			`Parameter TMPDIR set to xst/projnav.tmp`
5	2	leonardoar
6
7			`Total REAL time to Xst completion: 0.00 secs`
8	15	leonardoar	`Total CPU time to Xst completion: 0.06 secs`
9	2	leonardoar
10	15	leonardoar	`-->`
11			`Parameter xsthdpdir set to xst`
12	2	leonardoar
13
14			`Total REAL time to Xst completion: 0.00 secs`
15	15	leonardoar	`Total CPU time to Xst completion: 0.06 secs`
16	2	leonardoar
17	15	leonardoar	`-->`
18			`Reading design: serial_transmitter.prj`
19	2	leonardoar
20			`TABLE OF CONTENTS`
21			`1) Synthesis Options Summary`
22			`2) HDL Compilation`
23			`3) Design Hierarchy Analysis`
24			`4) HDL Analysis`
25			`5) HDL Synthesis`
26			`5.1) HDL Synthesis Report`
27			`6) Advanced HDL Synthesis`
28			`6.1) Advanced HDL Synthesis Report`
29			`7) Low Level Synthesis`
30			`8) Partition Report`
31			`9) Final Report`
32			`9.1) Device utilization summary`
33			`9.2) Partition Resource Summary`
34			`9.3) TIMING REPORT`
35
36
37			`=========================================================================`
38			`* Synthesis Options Summary *`
39			`=========================================================================`
40			`---- Source Parameters`
41			`Input File Name : "serial_transmitter.prj"`
42			`Input Format : mixed`
43			`Ignore Synthesis Constraint File : NO`
44
45			`---- Target Parameters`
46			`Output File Name : "serial_transmitter"`
47			`Output Format : NGC`
48			`Target Device : xc3s500e-4-fg320`
49
50			`---- Source Options`
51			`Top Module Name : serial_transmitter`
52			`Automatic FSM Extraction : YES`
53			`FSM Encoding Algorithm : Auto`
54			`Safe Implementation : No`
55			`FSM Style : LUT`
56			`RAM Extraction : Yes`
57			`RAM Style : Auto`
58			`ROM Extraction : Yes`
59			`Mux Style : Auto`
60			`Decoder Extraction : YES`
61			`Priority Encoder Extraction : Yes`
62			`Shift Register Extraction : YES`
63			`Logical Shifter Extraction : YES`
64			`XOR Collapsing : YES`
65			`ROM Style : Auto`
66			`Mux Extraction : Yes`
67			`Resource Sharing : YES`
68			`Asynchronous To Synchronous : NO`
69			`Multiplier Style : Auto`
70			`Automatic Register Balancing : No`
71
72			`---- Target Options`
73			`Add IO Buffers : YES`
74			`Global Maximum Fanout : 100000`
75			`Add Generic Clock Buffer(BUFG) : 24`
76			`Register Duplication : YES`
77			`Slice Packing : YES`
78			`Optimize Instantiated Primitives : NO`
79			`Use Clock Enable : Yes`
80			`Use Synchronous Set : Yes`
81			`Use Synchronous Reset : Yes`
82			`Pack IO Registers into IOBs : Auto`
83			`Equivalent register Removal : YES`
84
85			`---- General Options`
86			`Optimization Goal : Speed`
87			`Optimization Effort : 1`
88			`Keep Hierarchy : No`
89			`Netlist Hierarchy : As_Optimized`
90			`RTL Output : Yes`
91			`Global Optimization : AllClockNets`
92			`Read Cores : YES`
93			`Write Timing Constraints : NO`
94			`Cross Clock Analysis : NO`
95			`Hierarchy Separator : /`
96			`Bus Delimiter : <>`
97			`Case Specifier : Maintain`
98			`Slice Utilization Ratio : 100`
99			`BRAM Utilization Ratio : 100`
100			`Verilog 2001 : YES`
101			`Auto BRAM Packing : NO`
102			`Slice Utilization Ratio Delta : 5`
103
104			`=========================================================================`
105
106
107			`=========================================================================`
108			`* HDL Compilation *`
109			`=========================================================================`
110	15	leonardoar	`Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" in Library work.`
111			`Architecture pkgdefinitions of Entity pkgdefinitions is up to date.`
112			`Compiling vhdl file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" in Library work.`
113	2	leonardoar	`Architecture behavioral of Entity serial_transmitter is up to date.`
114
115			`=========================================================================`
116			`* Design Hierarchy Analysis *`
117			`=========================================================================`
118			`Analyzing hierarchy for entity in library (architecture ).`
119
120
121			`=========================================================================`
122			`* HDL Analysis *`
123			`=========================================================================`
124			`Analyzing Entity in library (Architecture ).`
125			`Entity analyzed. Unit generated.`
126
127
128			`=========================================================================`
129			`* HDL Synthesis *`
130			`=========================================================================`
131
132			`Performing bidirectional port resolution...`
133
134			`Synthesizing Unit .`
135	15	leonardoar	`Related source file is "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd".`
136	2	leonardoar	`Found finite state machine for signal .`
137			`-----------------------------------------------------------------------`
138			`\| States \| 12 \|`
139			`\| Transitions \| 12 \|`
140			`\| Inputs \| 0 \|`
141			`\| Outputs \| 13 \|`
142			`\| Clock \| baudClk (rising_edge) \|`
143			`\| Reset \| rst (positive) \|`
144			`\| Reset type \| asynchronous \|`
145			`\| Reset State \| tx_idle \|`
146			`\| Power Up State \| tx_idle \|`
147			`\| Encoding \| automatic \|`
148			`\| Implementation \| LUT \|`
149			`-----------------------------------------------------------------------`
150			`Summary:`
151			`inferred 1 Finite State Machine(s).`
152			`Unit synthesized.`
153
154
155			`=========================================================================`
156			`HDL Synthesis Report`
157
158			`Found no macro`
159			`=========================================================================`
160
161			`=========================================================================`
162			`* Advanced HDL Synthesis *`
163			`=========================================================================`
164
165			`Analyzing FSM for best encoding.`
166			`Optimizing FSM on signal with one-hot encoding.`
167			`--------------------------`
168			`State \| Encoding`
169			`--------------------------`
170			`tx_idle \| 000000000001`
171			`tx_start \| 000000000010`
172			`bit0 \| 000000000100`
173			`bit1 \| 000000001000`
174			`bit2 \| 000000010000`
175			`bit3 \| 000000100000`
176			`bit4 \| 000001000000`
177			`bit5 \| 000010000000`
178			`bit6 \| 000100000000`
179			`bit7 \| 001000000000`
180			`tx_stop1 \| 010000000000`
181			`tx_stop2 \| 100000000000`
182			`--------------------------`
183
184			`=========================================================================`
185			`Advanced HDL Synthesis Report`
186
187			`Macro Statistics`
188			`# FSMs : 1`
189
190			`=========================================================================`
191
192			`=========================================================================`
193			`* Low Level Synthesis *`
194			`=========================================================================`
195
196			`Optimizing unit ...`
197
198			`Mapping all equations...`
199			`Building and optimizing final netlist ...`
200			`Found area constraint ratio of 100 (+ 5) on block serial_transmitter, actual ratio is 0.`
201
202			`Final Macro Processing ...`
203
204			`=========================================================================`
205			`Final Register Report`
206
207			`Macro Statistics`
208			`# Registers : 12`
209			`Flip-Flops : 12`
210
211			`=========================================================================`
212
213			`=========================================================================`
214			`* Partition Report *`
215			`=========================================================================`
216
217			`Partition Implementation Status`
218			`-------------------------------`
219
220			`No Partitions were found in this design.`
221
222			`-------------------------------`
223
224			`=========================================================================`
225			`* Final Report *`
226			`=========================================================================`
227			`Final Results`
228			`RTL Top Level Output File Name : serial_transmitter.ngr`
229			`Top Level Output File Name : serial_transmitter`
230			`Output Format : NGC`
231			`Optimization Goal : Speed`
232			`Keep Hierarchy : No`
233
234			`Design Statistics`
235			`# IOs : 12`
236
237			`Cell Usage :`
238			`# BELS : 9`
239			`# GND : 1`
240			`# LUT2 : 1`
241			`# LUT4 : 6`
242			`# VCC : 1`
243			`# FlipFlops/Latches : 12`
244			`# FDC : 10`
245			`# FDCE : 1`
246			`# FDP : 1`
247			`# Clock Buffers : 1`
248			`# BUFGP : 1`
249			`# IO Buffers : 11`
250			`# IBUF : 9`
251			`# OBUF : 2`
252			`=========================================================================`
253
254			`Device utilization summary:`
255			`---------------------------`
256
257			`Selected Device : 3s500efg320-4`
258
259			`Number of Slices: 7 out of 4656 0%`
260			`Number of Slice Flip Flops: 12 out of 9312 0%`
261			`Number of 4 input LUTs: 7 out of 9312 0%`
262			`Number of IOs: 12`
263			`Number of bonded IOBs: 12 out of 232 5%`
264			`Number of GCLKs: 1 out of 24 4%`
265
266			`---------------------------`
267			`Partition Resource Summary:`
268			`---------------------------`
269
270			`No Partitions were found in this design.`
271
272			`---------------------------`
273
274
275			`=========================================================================`
276			`TIMING REPORT`
277
278			`NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.`
279			`FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT`
280			`GENERATED AFTER PLACE-and-ROUTE.`
281
282			`Clock Information:`
283			`------------------`
284			`-----------------------------------+------------------------+-------+`
285			`Clock Signal \| Clock buffer(FF name) \| Load \|`
286			`-----------------------------------+------------------------+-------+`
287			`baudClk \| BUFGP \| 12 \|`
288			`-----------------------------------+------------------------+-------+`
289
290			`Asynchronous Control Signals Information:`
291			`----------------------------------------`
292			`-----------------------------------+------------------------+-------+`
293			`Control Signal \| Buffer(FF name) \| Load \|`
294			`-----------------------------------+------------------------+-------+`
295			`rst \| IBUF \| 12 \|`
296			`-----------------------------------+------------------------+-------+`
297
298			`Timing Summary:`
299			`---------------`
300			`Speed Grade: -4`
301
302			`Minimum period: 1.677ns (Maximum Frequency: 596.303MHz)`
303			`Minimum input arrival time before clock: No path found`
304			`Maximum output required time after clock: 8.036ns`
305			`Maximum combinational path delay: 8.540ns`
306
307			`Timing Detail:`
308			`--------------`
309			`All values displayed in nanoseconds (ns)`
310
311			`=========================================================================`
312			`Timing constraint: Default period analysis for Clock 'baudClk'`
313			`Clock period: 1.677ns (frequency: 596.303MHz)`
314			`Total number of paths / destination ports: 11 / 11`
315			`-------------------------------------------------------------------------`
316			`Delay: 1.677ns (Levels of Logic = 0)`
317			`Source: current_s_FSM_FFd2 (FF)`
318			`Destination: current_s_FSM_FFd1 (FF)`
319			`Source Clock: baudClk rising`
320			`Destination Clock: baudClk rising`
321
322			`Data Path: current_s_FSM_FFd2 to current_s_FSM_FFd1`
323			`Gate Net`
324			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
325			`---------------------------------------- ------------`
326			`FDC:C->Q 3 0.591 0.531 current_s_FSM_FFd2 (current_s_FSM_FFd2)`
327			`FDCE:CE 0.555 current_s_FSM_FFd1`
328			`----------------------------------------`
329			`Total 1.677ns (1.146ns logic, 0.531ns route)`
330			`(68.3% logic, 31.7% route)`
331
332			`=========================================================================`
333			`Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk'`
334			`Total number of paths / destination ports: 13 / 2`
335			`-------------------------------------------------------------------------`
336			`Offset: 8.036ns (Levels of Logic = 4)`
337			`Source: current_s_FSM_FFd7 (FF)`
338			`Destination: serial_out (PAD)`
339			`Source Clock: baudClk rising`
340
341			`Data Path: current_s_FSM_FFd7 to serial_out`
342			`Gate Net`
343			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
344			`---------------------------------------- ------------`
345			`FDC:C->Q 2 0.591 0.622 current_s_FSM_FFd7 (current_s_FSM_FFd7)`
346			`LUT4:I0->O 1 0.704 0.595 serial_out12 (serial_out12)`
347			`LUT4:I0->O 1 0.704 0.424 serial_out48_SW0 (N01)`
348			`LUT4:I3->O 1 0.704 0.420 serial_out48 (serial_out_OBUF)`
349			`OBUF:I->O 3.272 serial_out_OBUF (serial_out)`
350			`----------------------------------------`
351			`Total 8.036ns (5.975ns logic, 2.061ns route)`
352			`(74.4% logic, 25.6% route)`
353
354			`=========================================================================`
355			`Timing constraint: Default path analysis`
356			`Total number of paths / destination ports: 8 / 1`
357			`-------------------------------------------------------------------------`
358			`Delay: 8.540ns (Levels of Logic = 5)`
359			`Source: data_byte<3> (PAD)`
360			`Destination: serial_out (PAD)`
361
362			`Data Path: data_byte<3> to serial_out`
363			`Gate Net`
364			`Cell:in->out fanout Delay Delay Logical Name (Net Name)`
365			`---------------------------------------- ------------`
366			`IBUF:I->O 1 1.218 0.499 data_byte_3_IBUF (data_byte_3_IBUF)`
367			`LUT4:I1->O 1 0.704 0.595 serial_out12 (serial_out12)`
368			`LUT4:I0->O 1 0.704 0.424 serial_out48_SW0 (N01)`
369			`LUT4:I3->O 1 0.704 0.420 serial_out48 (serial_out_OBUF)`
370			`OBUF:I->O 3.272 serial_out_OBUF (serial_out)`
371			`----------------------------------------`
372			`Total 8.540ns (6.602ns logic, 1.938ns route)`
373			`(77.3% logic, 22.7% route)`
374
375			`=========================================================================`
376
377
378	15	leonardoar	`Total REAL time to Xst completion: 4.00 secs`
379			`Total CPU time to Xst completion: 4.47 secs`
380	2	leonardoar
381			`-->`
382
383
384	15	leonardoar	`Total memory usage is 163788 kilobytes`
385
386	2	leonardoar	`Number of errors : 0 ( 0 filtered)`
387			`Number of warnings : 0 ( 0 filtered)`
388			`Number of infos : 0 ( 0 filtered)`
389