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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testBaud_generator.vhd] - Blame information for rev 39

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1 38 leonardoar
--! @file
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--! @brief Test baud_generator module
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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--! Use Global Definitions package
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use work.pkgDefinitions.all;
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ENTITY testBaud_generator IS
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END testBaud_generator;
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--! @brief Test baud_generator module
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--! @details Exercise the baud generator with 50Mhz clock and dividing by 434, finally checking for period of 8.68 us
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ARCHITECTURE behavior OF testBaud_generator IS
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    COMPONENT baud_generator
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    Port ( rst : in STD_LOGIC;                                                                                                          --! Reset Input
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                          clk : in  STD_LOGIC;                                                                                                          --! Clock input
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           cycle_wait : in  STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);  --! Number of cycles to wait for baud generation
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                          baud_oversample : out std_logic;                                                                              --! Oversample(8x) version of baud (Used on serial_receiver)
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           baud : out  STD_LOGIC);                                                                                                      --! Baud generation output (Used on serial_transmitter)
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    END COMPONENT;
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   --Inputs
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   signal rst : std_logic := '0';                                                                                                                                                --! Signal to connect with UUT
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   signal clk : std_logic := '0';                                                                                                                                                --! Signal to connect with UUT
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   signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');      --! Signal to connect with UUT
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        --Outputs
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   signal baud : std_logic;                                     --! Signal to connect with UUT
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        signal baud_oversample : std_logic;             --! Signal to connect with UUT
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   -- Clock period definitions (1.8432MHz)
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   constant clk_period : time := 20 ns; -- 0.543us (1.8432Mhz) 20ns (50Mhz)
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BEGIN
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        --! Instantiate the Unit Under Test (UUT)
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   uut: baud_generator PORT MAP (
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          rst => rst,
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          clk => clk,
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          cycle_wait => cycle_wait,
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                         baud_oversample => baud_oversample,
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          baud => baud
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        );
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   -- Clock process definitions
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   clk_process :process
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   begin
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                clk <= '0';
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                wait for clk_period/2;
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                clk <= '1';
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                wait for clk_period/2;
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   end process;
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   -- Stimulus process
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   stim_proc: process
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   variable t1 : time;
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        variable t2 : time;
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        variable period : time; -- 1/115200 = 8.68 us
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        begin
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      -- Test the baud generator waiting for 434 clock cycles from 50MHz clock
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                rst <= '1';
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                cycle_wait <= conv_std_logic_vector(434, (nBitsLarge)); -- 50000000/115200
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      wait for clk_period;
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                rst <= '0';
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      wait until baud = '1';
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                t1 := now;      -- Get current simulation time
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                wait until baud = '0';
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                wait until baud = '1';
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                t2 := now;      -- Get current simulation time
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                wait until baud = '0';
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                wait until baud = '1';
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                report "Current sim time=" & time'image(now);
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                period := t2 - t1;
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                -- Verify if we have the right period 1/115200 = 8.68 us
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                assert period = 8.68 us report "Wrong period expecter 8.68 us. got: "& time'image(period) severity failure;
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                -- Stop Simulation
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                assert false report "NONE. End of simulation." severity failure;
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      wait;
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   end process;
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END;

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