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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_communication_block.vhd] - Blame information for rev 37

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--! Test baud_generator module
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use Global Definitions package
use work.pkgDefinitions.all;
 
ENTITY testUart_communication_block IS
END testUart_communication_block;
 
ARCHITECTURE behavior OF testUart_communication_block IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT uart_communication_blocks
    Port ( rst : in  STD_LOGIC;                                                                                                                 --! Global reset
           clk : in  STD_LOGIC;                                                                                                                 --! Global clock
                          cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0);        --! Number of cycles to wait in order to generate desired baud
           byte_tx : in  STD_LOGIC_VECTOR ((nBits-1) downto 0);                          --! Byte to transmit
           byte_rx : out  STD_LOGIC_VECTOR ((nBits-1) downto 0);                         --! Byte to receive
           data_sent_tx : out  STD_LOGIC;                                                                                               --! Indicate that byte has been sent
           data_received_rx : out  STD_LOGIC;                                                                           --! Indicate that we got a byte
                          serial_out : out std_logic;                                                                                                   --! Uart serial out
                          serial_in : in std_logic;                                                                                                     --! Uart serial in
           start_tx : in  STD_LOGIC);                                                                                                   --! Initiate transmission
    END COMPONENT;
 
 
   --Inputs
   signal rst : std_logic := '0';                                                                                                                                                        --! Signal to connect with UUT
   signal clk : std_logic := '0';                                                                                                                                                        --! Signal to connect with UUT
   signal cycle_wait_baud : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT
   signal byte_tx : std_logic_vector((nBits-1) downto 0) := (others => '0');                                      --! Signal to connect with UUT
   signal serial_in : std_logic := '0';                                                                                                                                  --! Signal to connect with UUT
   signal start_tx : std_logic := '0';                                                                                                                                           --! Signal to connect with UUT
 
        --Outputs
   signal byte_rx : std_logic_vector((nBits-1) downto 0);                                                                                        --! Signal to connect with UUT
   signal data_sent_tx : std_logic;                                                                                                                                                     --! Signal to connect with UUT
   signal data_received_rx : std_logic;                                                                                                                                 --! Signal to connect with UUT
   signal serial_out : std_logic;                                                                                                                                                       --! Signal to connect with UUT
 
   -- Clock period definitions   
        constant clk_period : time := 20 ns; -- 0.543us (1.8432Mhz) 20ns (50Mhz)
 
BEGIN
 
        --! Instantiate the Unit Under Test (UUT)
   uut: uart_communication_blocks PORT MAP (
          rst => rst,
          clk => clk,
          cycle_wait_baud => cycle_wait_baud,
          byte_tx => byte_tx,
          byte_rx => byte_rx,
          data_sent_tx => data_sent_tx,
          data_received_rx => data_received_rx,
          serial_out => serial_out,
          serial_in => serial_in,
          start_tx => start_tx
        );
 
   -- Clock process definitions
   clk_process :process
   begin
                clk <= '0';
                wait for clk_period/2;
                clk <= '1';
                wait for clk_period/2;
   end process;
 
 
   -- Stimulus process
   stim_proc: process
   begin
      -- Setup communication blocks
                rst <= '1';
                serial_in <= '1'; -- Idle..
                cycle_wait_baud <= conv_std_logic_vector(434, (nBitsLarge));
                start_tx <= '0';
      wait for 2 ns;
                rst <= '0';
 
                -- Send data..
                start_tx <= '1';
                byte_tx <= "01010101";
                wait until data_sent_tx = '1';
 
      wait for clk_period*3;
                start_tx <= '0';
                wait for clk_period*3;
 
                start_tx <= '1';
                byte_tx <= "11000100";
                wait until data_sent_tx = '1';
 
                wait for clk_period*3;
                start_tx <= '0';
                wait for clk_period*3;
 
                -- Receive data...
                -- Receive 0x55 value (01010101)
                serial_in <= '0'; -- Start bit
                wait for 8.68 us;
 
                serial_in <= '1';
      wait for 8.68 us;
                serial_in <= '0';
      wait for 8.68 us;
                serial_in <= '1';
      wait for 8.68 us;
                serial_in <= '0';
      wait for 8.68 us;
                serial_in <= '1';
      wait for 8.68 us;
                serial_in <= '0';
      wait for 8.68 us;
                serial_in <= '1';
      wait for 8.68 us;
                serial_in <= '0';
      wait for 8.68 us;
 
                -- Stop bit here
                serial_in <= '1';
                wait for clk_period*200;
 
                -- Receive 0xC4 value (11000100)
                serial_in <= '0'; -- Start bit
                wait for 8.68 us;
 
                serial_in <= '0';
      wait for 8.68 us;
                serial_in <= '0';
      wait for 8.68 us;
                serial_in <= '1';
      wait for 8.68 us;
                serial_in <= '0';
      wait for 8.68 us;
                serial_in <= '0';
      wait for 8.68 us;
                serial_in <= '0';
      wait for 8.68 us;
                serial_in <= '1';
      wait for 8.68 us;
                serial_in <= '1';
      wait for 8.68 us;
 
                -- Stop bit here
                serial_in <= '1';
                wait for clk_period*200;
 
 
 
      -- Stop Simulation
                assert false report "NONE. End of simulation." severity failure;
 
   end process;
 
END;

Line No.	Rev	Author	Line
1	11	leonardoar	`--! Test baud_generator module`
2			`LIBRARY ieee;`
3			`USE ieee.std_logic_1164.ALL;`
4	12	leonardoar	`use ieee.std_logic_unsigned.all;`
5			`use ieee.std_logic_arith.all;`
6	11	leonardoar
7			`--! Use Global Definitions package`
8			`use work.pkgDefinitions.all;`
9
10			`ENTITY testUart_communication_block IS`
11			`END testUart_communication_block;`
12
13			`ARCHITECTURE behavior OF testUart_communication_block IS`
14
15			`-- Component Declaration for the Unit Under Test (UUT)`
16
17			`COMPONENT uart_communication_blocks`
18	37	leonardoar	`Port ( rst : in STD_LOGIC; --! Global reset`
19			`clk : in STD_LOGIC; --! Global clock`
20			`cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0); --! Number of cycles to wait in order to generate desired baud`
21			`byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to transmit`
22			`byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to receive`
23			`data_sent_tx : out STD_LOGIC; --! Indicate that byte has been sent`
24			`data_received_rx : out STD_LOGIC; --! Indicate that we got a byte`
25			`serial_out : out std_logic; --! Uart serial out`
26			`serial_in : in std_logic; --! Uart serial in`
27			`start_tx : in STD_LOGIC); --! Initiate transmission`
28	11	leonardoar	`END COMPONENT;`
29
30
31			`--Inputs`
32	37	leonardoar	`signal rst : std_logic := '0'; --! Signal to connect with UUT`
33			`signal clk : std_logic := '0'; --! Signal to connect with UUT`
34			`signal cycle_wait_baud : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0'); --! Signal to connect with UUT`
35			`signal byte_tx : std_logic_vector((nBits-1) downto 0) := (others => '0'); --! Signal to connect with UUT`
36			`signal serial_in : std_logic := '0'; --! Signal to connect with UUT`
37			`signal start_tx : std_logic := '0'; --! Signal to connect with UUT`
38	11	leonardoar
39			`--Outputs`
40	37	leonardoar	`signal byte_rx : std_logic_vector((nBits-1) downto 0); --! Signal to connect with UUT`
41			`signal data_sent_tx : std_logic; --! Signal to connect with UUT`
42			`signal data_received_rx : std_logic; --! Signal to connect with UUT`
43			`signal serial_out : std_logic; --! Signal to connect with UUT`
44	11	leonardoar
45			`-- Clock period definitions`
46	32	leonardoar	`constant clk_period : time := 20 ns; -- 0.543us (1.8432Mhz) 20ns (50Mhz)`
47	11	leonardoar
48			`BEGIN`
49
50	36	leonardoar	`--! Instantiate the Unit Under Test (UUT)`
51	11	leonardoar	`uut: uart_communication_blocks PORT MAP (`
52			`rst => rst,`
53			`clk => clk,`
54			`cycle_wait_baud => cycle_wait_baud,`
55			`byte_tx => byte_tx,`
56			`byte_rx => byte_rx,`
57			`data_sent_tx => data_sent_tx,`
58			`data_received_rx => data_received_rx,`
59			`serial_out => serial_out,`
60			`serial_in => serial_in,`
61			`start_tx => start_tx`
62			`);`
63
64			`-- Clock process definitions`
65			`clk_process :process`
66			`begin`
67			`clk <= '0';`
68			`wait for clk_period/2;`
69			`clk <= '1';`
70			`wait for clk_period/2;`
71			`end process;`
72
73
74			`-- Stimulus process`
75			`stim_proc: process`
76			`begin`
77			`-- Setup communication blocks`
78			`rst <= '1';`
79	12	leonardoar	`serial_in <= '1'; -- Idle..`
80	32	leonardoar	`cycle_wait_baud <= conv_std_logic_vector(434, (nBitsLarge));`
81	12	leonardoar	`start_tx <= '0';`
82	11	leonardoar	`wait for 2 ns;`
83			`rst <= '0';`
84	12	leonardoar
85			`-- Send data..`
86			`start_tx <= '1';`
87			`byte_tx <= "01010101";`
88			`wait until data_sent_tx = '1';`
89	11	leonardoar
90	12	leonardoar	`wait for clk_period*3;`
91			`start_tx <= '0';`
92			`wait for clk_period*3;`
93
94			`start_tx <= '1';`
95			`byte_tx <= "11000100";`
96			`wait until data_sent_tx = '1';`
97
98			`wait for clk_period*3;`
99			`start_tx <= '0';`
100			`wait for clk_period*3;`
101
102			`-- Receive data...`
103			`-- Receive 0x55 value (01010101)`
104			`serial_in <= '0'; -- Start bit`
105			`wait for 8.68 us;`
106
107			`serial_in <= '1';`
108			`wait for 8.68 us;`
109			`serial_in <= '0';`
110			`wait for 8.68 us;`
111			`serial_in <= '1';`
112			`wait for 8.68 us;`
113			`serial_in <= '0';`
114			`wait for 8.68 us;`
115			`serial_in <= '1';`
116			`wait for 8.68 us;`
117			`serial_in <= '0';`
118			`wait for 8.68 us;`
119			`serial_in <= '1';`
120			`wait for 8.68 us;`
121			`serial_in <= '0';`
122			`wait for 8.68 us;`
123
124			`-- Stop bit here`
125			`serial_in <= '1';`
126	32	leonardoar	`wait for clk_period*200;`
127	12	leonardoar
128			`-- Receive 0xC4 value (11000100)`
129			`serial_in <= '0'; -- Start bit`
130			`wait for 8.68 us;`
131
132			`serial_in <= '0';`
133			`wait for 8.68 us;`
134			`serial_in <= '0';`
135			`wait for 8.68 us;`
136			`serial_in <= '1';`
137			`wait for 8.68 us;`
138			`serial_in <= '0';`
139			`wait for 8.68 us;`
140			`serial_in <= '0';`
141			`wait for 8.68 us;`
142			`serial_in <= '0';`
143			`wait for 8.68 us;`
144			`serial_in <= '1';`
145			`wait for 8.68 us;`
146			`serial_in <= '1';`
147			`wait for 8.68 us;`
148
149			`-- Stop bit here`
150			`serial_in <= '1';`
151	32	leonardoar	`wait for clk_period*200;`
152	12	leonardoar
153
154	11	leonardoar
155	12	leonardoar	`-- Stop Simulation`
156			`assert false report "NONE. End of simulation." severity failure;`
157
158	11	leonardoar	`end process;`
159
160			`END;`

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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_communication_block.vhd] - Blame information for rev 37