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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_wishbone_slave.vhd] - Blame information for rev 18

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Line No. Rev Author Line
1 16 leonardoar 
--! Test uart_wishbone_slave (Main test module)
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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--! Use Global Definitions package
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use work.pkgDefinitions.all;
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ENTITY testUart_wishbone_slave IS
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END testUart_wishbone_slave;
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ARCHITECTURE behavior OF testUart_wishbone_slave IS
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    -- Component Declaration for the Unit Under Test (UUT)
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    COMPONENT uart_wishbone_slave
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    PORT(
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         RST_I : IN  std_logic;
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         CLK_I : IN  std_logic;
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         ADR_I0 : IN  std_logic_vector(1 downto 0);
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         DAT_I0 : IN  std_logic_vector(31 downto 0);
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         DAT_O0 : OUT  std_logic_vector(31 downto 0);
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         WE_I : IN  std_logic;
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         STB_I : IN  std_logic;
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         ACK_O : OUT  std_logic;
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         serial_in : IN  std_logic;
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         serial_out : OUT  std_logic
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        );
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    END COMPONENT;
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   --Inputs
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   signal RST_I : std_logic := '0';
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   signal CLK_I : std_logic := '0';
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   signal ADR_I0 : std_logic_vector(1 downto 0) := (others => '0');
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   signal DAT_I0 : std_logic_vector(31 downto 0) := (others => '0');
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   signal WE_I : std_logic := '0';
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   signal STB_I : std_logic := '0';
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   signal serial_in : std_logic := '0';
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        --Outputs
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   signal DAT_O0 : std_logic_vector(31 downto 0);
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   signal ACK_O : std_logic;
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   signal serial_out : std_logic;
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   -- Clock period definitions (1.8432MHz)
48 18 leonardoar 
   constant CLK_I_period : time := 20 ns; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
49 16 leonardoar 
 
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BEGIN
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        -- Instantiate the Unit Under Test (UUT)
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   uut: uart_wishbone_slave PORT MAP (
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          RST_I => RST_I,
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          CLK_I => CLK_I,
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          ADR_I0 => ADR_I0,
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          DAT_I0 => DAT_I0,
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          DAT_O0 => DAT_O0,
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          WE_I => WE_I,
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          STB_I => STB_I,
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          ACK_O => ACK_O,
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          serial_in => serial_in,
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          serial_out => serial_out
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        );
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   -- Clock process definitions
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   CLK_I_process :process
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   begin
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                CLK_I <= '0';
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                wait for CLK_I_period/2;
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                CLK_I <= '1';
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                wait for CLK_I_period/2;
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   end process;
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   -- Stimulus process
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   stim_proc: process
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   begin
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      -- Reset the slave
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                RST_I <= '1';
81 18 leonardoar 
      wait for CLK_I_period;
82 16 leonardoar 
                RST_I <= '0';
83 18 leonardoar 
                wait for CLK_I_period;
84 16 leonardoar 
 
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      -- Configure the clock...
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                ADR_I0 <= "00";
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                WE_I <= '1';
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                STB_I <= '1';
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                DAT_I0 <= conv_std_logic_vector(50000000, (nBitsLarge));
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                wait until ACK_O = '1';
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                WE_I <= '0';
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                STB_I <= '0';
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                ADR_I0 <= (others => 'U');
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                wait for CLK_I_period;
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                -- Configure the Baud...
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                ADR_I0 <= "01";
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                WE_I <= '1';
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                STB_I <= '1';
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                DAT_I0 <= conv_std_logic_vector(115200, (nBitsLarge));
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                wait until ACK_O = '1';
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                WE_I <= '0';
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                STB_I <= '0';
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                ADR_I0 <= (others => 'U');
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                wait for CLK_I_period;
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                -- Ask to send some data...(0xC4)
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                ADR_I0 <= "10";
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                WE_I <= '1';
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                STB_I <= '1';
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                DAT_I0 <= x"000000C4";
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                wait until ACK_O = '1';
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                WE_I <= '0';
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                STB_I <= '0';
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                ADR_I0 <= (others => 'U');
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                wait for CLK_I_period;
117 18 leonardoar 
 
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                -- Ask to send some data...(0xC4)
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                ADR_I0 <= "11";
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                WE_I <= '1';
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                STB_I <= '1';
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123 17 leonardoar 
                -- Receive data...
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                -- Receive 0x55 value (01010101)
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                serial_in <= '0'; -- Start bit
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                wait for 8.68 us;
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                serial_in <= '1';
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      wait for 8.68 us;
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                serial_in <= '0';
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      wait for 8.68 us;
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                serial_in <= '1';
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      wait for 8.68 us;
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                serial_in <= '0';
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      wait for 8.68 us;
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                serial_in <= '1';
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      wait for 8.68 us;
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                serial_in <= '0';
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      wait for 8.68 us;
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                serial_in <= '1';
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      wait for 8.68 us;
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                serial_in <= '0';
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      wait for 8.68 us;
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                -- Stop bit here
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                serial_in <= '1';
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                wait for CLK_I_period*20;
148 18 leonardoar 
 
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                wait until ACK_O = '1';
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                WE_I <= '0';
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                STB_I <= '0';
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                wait for CLK_I_period;
153 16 leonardoar 
 
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      -- Stop Simulation
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                assert false report "NONE. End of simulation." severity failure;
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   end process;
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END;

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