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--! uart control unit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgDefinitions.all;
 
entity uart_control is
    Port ( rst : in  std_logic;                                                                                                         -- Global reset
           clk : in  std_logic;                                                                                                         -- Global clock
                          WE    : in std_logic;                                                                                                         -- Write enable
           reg_addr : in  std_logic_vector (1 downto 0);                                         -- Register address
                          start : in std_logic;                                                                                                         -- Start (Strobe)
                          done : out std_logic;                                                                                                         -- Done (ACK)
           DAT_I : in  std_logic_vector ((nBitsLarge-1) downto 0);               -- Data Input (Wishbone)
           DAT_O : out  std_logic_vector ((nBitsLarge-1) downto 0);              -- Data output (Wishbone)
                          baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0);    -- Signal to control the baud rate frequency
                          data_byte_tx : out std_logic_vector((nBits-1) downto 0);               -- 1 Byte to be send to serial_transmitter
                          data_byte_rx : in std_logic_vector((nBits-1) downto 0);        -- 1 Byte to be received by serial_receiver
           tx_data_sent : in  std_logic;                                                                                        -- Signal comming from serial_transmitter
                          tx_start : out std_logic;                                                                                             -- Signal to start sending serial data...
                          rst_comm_blocks : out std_logic;                                                                              -- Reset Communication blocks
           rx_data_ready : in  std_logic);                                                                              -- Signal comming from serial_receiver
end uart_control;
 
architecture Behavioral of uart_control is
signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
signal received_byte : std_logic_vector((nBits-1) downto 0);
signal byte_to_transmit : std_logic_vector((nBits-1) downto 0);
 
signal sigDivRst : std_logic;
signal sigDivDone : std_logic;
signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);
signal sigDivNumerator : std_logic_vector((nBitsLarge-1) downto 0);
signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0);
 
-- Signals used to control the configuration
signal startConfigBaud : std_logic;
signal startConfigClk : std_logic;
signal startDataSend : std_logic;
signal commBlocksInitiated : std_logic;
signal finishedDataSend : std_logic;
signal doneWriteReg : std_logic;
signal startReadReg : std_logic;
 
-- Divisor component
component divisor is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           quotient : out  STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
                          reminder : out  STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
           numerator : in  STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
           divident : in  STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
           done : out  STD_LOGIC);
end component;
 
begin
        -- Instantiate block for calculate division
        uDiv : divisor port map (
                rst => sigDivRst,
                clk => clk,
                quotient => sigDivQuotient,
                reminder => open,       -- Indicates that this port will not be connected to anything
                numerator => sigDivNumerator,
                divident => sigDivDividend,
                done => sigDivDone
        );
 
        -- Process to handle the of writting the registers
        process (clk)
        begin
                -- On the wishbone specification we should handle the reset synchronously
                if rising_edge(clk) then
                        if rst = '1' then
                                config_clk <= (others => '0');
                                config_baud <= (others => '0');
                                byte_to_transmit <= (others => '0');
                                startConfigBaud <= '0';
                                startConfigClk <= '0';
                                startDataSend <= '0';
                                doneWriteReg <= '0';
                        elsif (WE and start) = '1'      then
                                case reg_addr is
                                        when "00" =>
                                                config_clk <= DAT_I;
                                                startConfigClk <= '1';
                                                startDataSend <= '0';
                                                startConfigBaud <= '0';
                                        when "01" =>
                                                config_baud <= DAT_I;
                                                startConfigBaud <= '1';
                                                startDataSend <= '0';
                                                startConfigClk <= '0';
                                        when "10" =>
                                                -- If we have an overrun, discard the byte
                                                if finishedDataSend = '1' then
                                                        byte_to_transmit <= DAT_I((nBits-1) downto 0);
                                                else
                                                        byte_to_transmit <= byte_to_transmit;
                                                end if;
                                                startConfigBaud <= '0';
                                                startConfigClk <= '0';
                                                startDataSend <= '1';
                                        when others =>
                                                startConfigBaud <= '0';
                                                startConfigClk <= '0';
                                                startDataSend <= '0';
                                end case;
                        end if;
                end if;
        end process;
 
        -- Process to handle the reading of registers
        process (clk)
        begin
                -- On the wishbone specification we should handle the reset synchronously
                if rising_edge(clk) then
                        if rst = '1' then
                                DAT_O <= (others => 'Z');
                                startReadReg <= '0';
                        elsif ((WE = '0') and (start = '1')) then
                                startReadReg <= '1';
                                case reg_addr is
                                        when "00" =>
                                                DAT_O <= config_clk;
                                        when "01" =>
                                                DAT_O <= config_baud;
                                        when "10" =>
                                                DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & byte_to_transmit;
                                        when "11" =>
                                                DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & received_byte;
                                        when others =>
                                                null;
                                end case;
                        end if;
                end if;
        end process;
 
        -- Process that stores the data that comes from the serial receiver block
        process (rx_data_ready)
        begin
                if rising_edge(rx_data_ready) then
                        received_byte <= data_byte_rx;
                else
                        received_byte <= received_byte;
                end if;
        end process;
 
        -- Process to send data over the serial transmitter
        process (startDataSend, commBlocksInitiated, clk)
        variable cont_steps : integer range 0 to 3;
        begin
                if (startDataSend = '0' and commBlocksInitiated = '0') then
                        data_byte_tx <= (others => '0');
                        tx_start <= '0';
                        finishedDataSend <= '1';
                elsif rising_edge(clk) then
                        if cont_steps < 3 then
                                cont_steps := cont_steps + 1;
                        else
                                cont_steps := 3;
                        end if;
 
                        case cont_steps is
                                when 1 =>
                                        data_byte_tx <= byte_to_transmit;
                                        tx_start <= '0';
                                when 2 =>
                                        tx_start <= '1';
                                when others =>
                                        null;
                        end case;
 
                        if tx_data_sent = '1' then
                                finishedDataSend <= '1';
                        else
                                finishedDataSend <= '0';
                        end if;
 
                end if;
        end process;
 
        -- Process to send the ACK signal, remember that optimally this ACK should be as fast as possible
        -- to avoid locking the bus, on this case if you send a more bytes then you can transmit the ideal
        -- is to create an error flag to indicate overrun.
        -- On this case on any attempt of reading or writting on registers we will be lock on 1 cycle
        process (clk, rst, startConfigBaud, startConfigClk, startDataSend, startReadReg )
        variable joinSignal : std_logic_vector(3 downto 0);
        variable cont_steps : integer range 0 to 3;
        begin
                if rising_edge(clk) then
                        if rst = '1' then
                                done <= '1';
                                cont_steps := 0;
                        else
                                joinSignal := startConfigBaud & startConfigClk & startDataSend & startReadReg;
                                if (joinSignal = "0000") then
                                        done <= '1';
                                else
                                        case cont_steps is
                                                when 0 =>
                                                        if start = '1' then
                                                                done <= '0';
                                                        end if;
                                                when others =>
                                                        done <= '1';
                                        end case;
 
                                        if cont_steps < 2 then
                                                cont_steps := cont_steps + 1;
                                        else
                                                cont_steps := 0;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        -- Process to calculate the amount of cycles to wait (clock_speed / desired_baud), and initiate the board
        process (startConfigBaud,startConfigClk, clk)
        variable cont_steps : integer range 0 to 3;
        begin
                if (startConfigBaud and startConfigClk) = '0' then
                        sigDivRst <= '1';
                        cont_steps := 0;
                        baud_wait <= (others => '0');
                        commBlocksInitiated <= '0';
                elsif rising_edge(clk) then
                        if cont_steps < 3 then
                                cont_steps := cont_steps + 1;
                        else
                                cont_steps := 3;
                        end if;
 
                        case cont_steps is
                                when 1 =>
                                        sigDivNumerator <= config_clk;
                                        sigDivDividend <= config_baud;
                                        sigDivRst <= '1';
                                when 2 =>
                                        sigDivRst <= '0';
                                when others =>
                                        null;
                        end case;
 
                        -- Enable the communication block when the baud is calculated
                        if sigDivDone = '1' then
                                rst_comm_blocks <= '0';
                                baud_wait <= sigDivQuotient;
                                commBlocksInitiated <= '1';
                        else
                                baud_wait <= (others => '0');
                                rst_comm_blocks <= '1';
                                commBlocksInitiated <= '0';
                        end if;
                end if;
        end process;
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	9	leonardoar	`--! uart control unit`
2			`library IEEE;`
3	22	leonardoar	`use IEEE.STD_LOGIC_1164.ALL;`
4			`use ieee.std_logic_unsigned.all;`
5			`use ieee.std_logic_arith.all;`
6	9	leonardoar
7			`--! Use CPU Definitions package`
8			`use work.pkgDefinitions.all;`
9
10			`entity uart_control is`
11	13	leonardoar	`Port ( rst : in std_logic; -- Global reset`
12			`clk : in std_logic; -- Global clock`
13			`WE : in std_logic; -- Write enable`
14			`reg_addr : in std_logic_vector (1 downto 0); -- Register address`
15	10	leonardoar	`start : in std_logic; -- Start (Strobe)`
16			`done : out std_logic; -- Done (ACK)`
17	13	leonardoar	`DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)`
18			`DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)`
19			`baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency`
20	10	leonardoar	`data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter`
21			`data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver`
22	13	leonardoar	`tx_data_sent : in std_logic; -- Signal comming from serial_transmitter`
23	14	leonardoar	`tx_start : out std_logic; -- Signal to start sending serial data...`
24	13	leonardoar	`rst_comm_blocks : out std_logic; -- Reset Communication blocks`
25			`rx_data_ready : in std_logic); -- Signal comming from serial_receiver`
26	9	leonardoar	`end uart_control;`
27
28			`architecture Behavioral of uart_control is`
29			`signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);`
30			`signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);`
31	22	leonardoar	`signal received_byte : std_logic_vector((nBits-1) downto 0);`
32			`signal byte_to_transmit : std_logic_vector((nBits-1) downto 0);`
33	9	leonardoar
34			`signal sigDivRst : std_logic;`
35			`signal sigDivDone : std_logic;`
36			`signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);`
37			`signal sigDivNumerator : std_logic_vector((nBitsLarge-1) downto 0);`
38	22	leonardoar	`signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0);`
39
40			`-- Signals used to control the configuration`
41			`signal startConfigBaud : std_logic;`
42			`signal startConfigClk : std_logic;`
43			`signal startDataSend : std_logic;`
44			`signal commBlocksInitiated : std_logic;`
45			`signal finishedDataSend : std_logic;`
46			`signal doneWriteReg : std_logic;`
47			`signal startReadReg : std_logic;`
48	9	leonardoar
49			`-- Divisor component`
50			`component divisor is`
51			`Port ( rst : in STD_LOGIC;`
52			`clk : in STD_LOGIC;`
53			`quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);`
54			`reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);`
55			`numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);`
56			`divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);`
57			`done : out STD_LOGIC);`
58			`end component;`
59
60			`begin`
61			`-- Instantiate block for calculate division`
62			`uDiv : divisor port map (`
63			`rst => sigDivRst,`
64			`clk => clk,`
65			`quotient => sigDivQuotient,`
66	16	leonardoar	`reminder => open, -- Indicates that this port will not be connected to anything`
67	9	leonardoar	`numerator => sigDivNumerator,`
68			`divident => sigDivDividend,`
69			`done => sigDivDone`
70			`);`
71
72	22	leonardoar	`-- Process to handle the of writting the registers`
73			`process (clk)`
74	10	leonardoar	`begin`
75	22	leonardoar	`-- On the wishbone specification we should handle the reset synchronously`
76			`if rising_edge(clk) then`
77			`if rst = '1' then`
78			`config_clk <= (others => '0');`
79			`config_baud <= (others => '0');`
80			`byte_to_transmit <= (others => '0');`
81			`startConfigBaud <= '0';`
82			`startConfigClk <= '0';`
83			`startDataSend <= '0';`
84			`doneWriteReg <= '0';`
85			`elsif (WE and start) = '1' then`
86			`case reg_addr is`
87			`when "00" =>`
88			`config_clk <= DAT_I;`
89			`startConfigClk <= '1';`
90			`startDataSend <= '0';`
91			`startConfigBaud <= '0';`
92			`when "01" =>`
93			`config_baud <= DAT_I;`
94			`startConfigBaud <= '1';`
95			`startDataSend <= '0';`
96			`startConfigClk <= '0';`
97			`when "10" =>`
98			`-- If we have an overrun, discard the byte`
99			`if finishedDataSend = '1' then`
100			`byte_to_transmit <= DAT_I((nBits-1) downto 0);`
101			`else`
102			`byte_to_transmit <= byte_to_transmit;`
103			`end if;`
104			`startConfigBaud <= '0';`
105			`startConfigClk <= '0';`
106			`startDataSend <= '1';`
107			`when others =>`
108			`startConfigBaud <= '0';`
109			`startConfigClk <= '0';`
110			`startDataSend <= '0';`
111			`end case;`
112			`end if;`
113			`end if;`
114	10	leonardoar	`end process;`
115
116	22	leonardoar	`-- Process to handle the reading of registers`
117			`process (clk)`
118			`begin`
119			`-- On the wishbone specification we should handle the reset synchronously`
120			`if rising_edge(clk) then`
121			`if rst = '1' then`
122			`DAT_O <= (others => 'Z');`
123			`startReadReg <= '0';`
124			`elsif ((WE = '0') and (start = '1')) then`
125			`startReadReg <= '1';`
126			`case reg_addr is`
127			`when "00" =>`
128			`DAT_O <= config_clk;`
129			`when "01" =>`
130			`DAT_O <= config_baud;`
131			`when "10" =>`
132			`DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & byte_to_transmit;`
133			`when "11" =>`
134			`DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & received_byte;`
135			`when others =>`
136			`null;`
137			`end case;`
138			`end if;`
139			`end if;`
140			`end process;`
141
142			`-- Process that stores the data that comes from the serial receiver block`
143			`process (rx_data_ready)`
144			`begin`
145			`if rising_edge(rx_data_ready) then`
146			`received_byte <= data_byte_rx;`
147			`else`
148			`received_byte <= received_byte;`
149			`end if;`
150			`end process;`
151
152			`-- Process to send data over the serial transmitter`
153			`process (startDataSend, commBlocksInitiated, clk)`
154			`variable cont_steps : integer range 0 to 3;`
155			`begin`
156			`if (startDataSend = '0' and commBlocksInitiated = '0') then`
157			`data_byte_tx <= (others => '0');`
158			`tx_start <= '0';`
159			`finishedDataSend <= '1';`
160			`elsif rising_edge(clk) then`
161			`if cont_steps < 3 then`
162			`cont_steps := cont_steps + 1;`
163			`else`
164			`cont_steps := 3;`
165			`end if;`
166
167			`case cont_steps is`
168			`when 1 =>`
169			`data_byte_tx <= byte_to_transmit;`
170			`tx_start <= '0';`
171			`when 2 =>`
172			`tx_start <= '1';`
173			`when others =>`
174			`null;`
175			`end case;`
176
177			`if tx_data_sent = '1' then`
178			`finishedDataSend <= '1';`
179			`else`
180			`finishedDataSend <= '0';`
181			`end if;`
182
183			`end if;`
184			`end process;`
185
186			`-- Process to send the ACK signal, remember that optimally this ACK should be as fast as possible`
187			`-- to avoid locking the bus, on this case if you send a more bytes then you can transmit the ideal`
188			`-- is to create an error flag to indicate overrun.`
189			`-- On this case on any attempt of reading or writting on registers we will be lock on 1 cycle`
190			`process (clk, rst, startConfigBaud, startConfigClk, startDataSend, startReadReg )`
191			`variable joinSignal : std_logic_vector(3 downto 0);`
192			`variable cont_steps : integer range 0 to 3;`
193			`begin`
194			`if rising_edge(clk) then`
195			`if rst = '1' then`
196			`done <= '1';`
197			`cont_steps := 0;`
198			`else`
199			`joinSignal := startConfigBaud & startConfigClk & startDataSend & startReadReg;`
200			`if (joinSignal = "0000") then`
201	10	leonardoar	`done <= '1';`
202	22	leonardoar	`else`
203			`case cont_steps is`
204			`when 0 =>`
205			`if start = '1' then`
206			`done <= '0';`
207			`end if;`
208			`when others =>`
209			`done <= '1';`
210			`end case;`
211	10	leonardoar
212	22	leonardoar	`if cont_steps < 2 then`
213			`cont_steps := cont_steps + 1;`
214	10	leonardoar	`else`
215	22	leonardoar	`cont_steps := 0;`
216	10	leonardoar	`end if;`
217	22	leonardoar	`end if;`
218			`end if;`
219			`end if;`
220			`end process;`
221
222			`-- Process to calculate the amount of cycles to wait (clock_speed / desired_baud), and initiate the board`
223			`process (startConfigBaud,startConfigClk, clk)`
224			`variable cont_steps : integer range 0 to 3;`
225			`begin`
226			`if (startConfigBaud and startConfigClk) = '0' then`
227			`sigDivRst <= '1';`
228			`cont_steps := 0;`
229			`baud_wait <= (others => '0');`
230			`commBlocksInitiated <= '0';`
231			`elsif rising_edge(clk) then`
232			`if cont_steps < 3 then`
233			`cont_steps := cont_steps + 1;`
234			`else`
235			`cont_steps := 3;`
236			`end if;`
237
238			`case cont_steps is`
239			`when 1 =>`
240			`sigDivNumerator <= config_clk;`
241			`sigDivDividend <= config_baud;`
242			`sigDivRst <= '1';`
243			`when 2 =>`
244			`sigDivRst <= '0';`
245			`when others =>`
246			`null;`
247			`end case;`
248
249			`-- Enable the communication block when the baud is calculated`
250			`if sigDivDone = '1' then`
251			`rst_comm_blocks <= '0';`
252			`baud_wait <= sigDivQuotient;`
253			`commBlocksInitiated <= '1';`
254			`else`
255			`baud_wait <= (others => '0');`
256			`rst_comm_blocks <= '1';`
257			`commBlocksInitiated <= '0';`
258			`end if;`
259			`end if;`
260	9	leonardoar	`end process;`
261
262			`end Behavioral;`
263

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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [uart_control.vhd] - Blame information for rev 22