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--! uart control unit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgDefinitions.all;
 
entity uart_control is
    Port ( rst : in  std_logic;                                                                                                         -- Global reset
           clk : in  std_logic;                                                                                                         -- Global clock
                          WE    : in std_logic;                                                                                                         -- Write enable
           reg_addr : in  std_logic_vector (1 downto 0);                                         -- Register address
                          start : in std_logic;                                                                                                         -- Start (Strobe)
                          done : out std_logic;                                                                                                         -- Done (ACK)
           DAT_I : in  std_logic_vector ((nBitsLarge-1) downto 0);               -- Data Input (Wishbone)
           DAT_O : out  std_logic_vector ((nBitsLarge-1) downto 0);              -- Data output (Wishbone)
                          baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0);    -- Signal to control the baud rate frequency
                          data_byte_tx : out std_logic_vector((nBits-1) downto 0);               -- 1 Byte to be send to serial_transmitter
                          data_byte_rx : in std_logic_vector((nBits-1) downto 0);        -- 1 Byte to be received by serial_receiver
           tx_data_sent : in  std_logic;                                                                                        -- Signal comming from serial_transmitter
                          tx_start : out std_logic;                                                                                             -- Signal to start sending serial data...
                          rst_comm_blocks : out std_logic;                                                                              -- Reset Communication blocks
           rx_data_ready : in  std_logic);                                                                              -- Signal comming from serial_receiver
end uart_control;
 
architecture Behavioral of uart_control is
signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
signal received_byte : std_logic_vector((nBits-1) downto 0);
signal byte_to_transmit : std_logic_vector((nBits-1) downto 0);
 
signal sigDivRst : std_logic;
signal sigDivDone : std_logic;
signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);
signal sigDivNumerator : std_logic_vector((nBitsLarge-1) downto 0);
signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0);
 
-- Signals used to control the configuration
signal startConfigBaud : std_logic;
signal startConfigClk : std_logic;
signal startDataSend : std_logic;
signal commBlocksInitiated : std_logic;
signal doneWriteReg : std_logic;
signal startReadReg : std_logic;
signal alreadyConfBaud : std_logic;
signal alreadyConfClk : std_logic;
 
-- Divisor component
component divisor is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           quotient : out  STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
                          reminder : out  STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
           numerator : in  STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
           divident : in  STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
           done : out  STD_LOGIC);
end component;
 
begin
        -- Instantiate block for calculate division
        uDiv : divisor port map (
                rst => sigDivRst,
                clk => clk,
                quotient => sigDivQuotient,
                reminder => open,       -- Indicates that this port will not be connected to anything
                numerator => sigDivNumerator,
                divident => sigDivDividend,
                done => sigDivDone
        );
 
        -- Process to handle the of writting the registers
        process (clk)
        begin
                -- On the wishbone specification we should handle the reset synchronously
                if rising_edge(clk) then
                        if rst = '1' then
                                config_clk <= (others => '0');
                                config_baud <= (others => '0');
                                byte_to_transmit <= (others => '0');
                                startConfigBaud <= '0';
                                startConfigClk <= '0';
                                startDataSend <= '0';
                                doneWriteReg <= '0';
                                alreadyConfClk <= '0';
                                alreadyConfBaud <= '0';
                        elsif (WE and start) = '1'      then
                                case reg_addr is
                                        when "00" =>
                                                config_clk <= DAT_I;
                                                startConfigClk <= '1';
                                                startDataSend <= '0';
                                                startConfigBaud <= '0';
                                                alreadyConfClk <= '1';
                                        when "01" =>
                                                config_baud <= DAT_I;
                                                startConfigBaud <= '1';
                                                startDataSend <= '0';
                                                startConfigClk <= '0';
                                                alreadyConfBaud <= '1';
                                        when "10" =>
                                                -- If we have an overrun, discard the byte
                                                byte_to_transmit <= DAT_I((nBits-1) downto 0);
                                                startConfigBaud <= '0';
                                                startConfigClk <= '0';
                                                startDataSend <= '1';
                                        when others =>
                                                startConfigBaud <= '0';
                                                startConfigClk <= '0';
                                                startDataSend <= '0';
                                end case;
                        end if;
                end if;
        end process;
 
        -- Process to handle the reading of registers
        process (clk)
        begin
                -- On the wishbone specification we should handle the reset synchronously
                if rising_edge(clk) then
                        if rst = '1' then
                                DAT_O <= (others => 'Z');
                                startReadReg <= '0';
                        elsif ((WE = '0') and (start = '1')) then
                                startReadReg <= '1';
                                case reg_addr is
                                        when "00" =>
                                                DAT_O <= config_clk;
                                        when "01" =>
                                                DAT_O <= config_baud;
                                        when "10" =>
                                                DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & byte_to_transmit;
                                        when "11" =>
                                                DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & received_byte;
                                        when others =>
                                                null;
                                end case;
                        end if;
                end if;
        end process;
 
        -- Process that stores the data that comes from the serial receiver block
        process (rx_data_ready)
        begin
                if rising_edge(rx_data_ready) then
                        received_byte <= data_byte_rx;
                else
                        received_byte <= received_byte;
                end if;
        end process;
 
        -- Process to send data over the serial transmitter
        process (clk)
        variable cont_steps : integer range 0 to 3;
        begin
                if rising_edge(clk) then
                        if (rst = '1') then
                                cont_steps := 0;
                        else
                                if commBlocksInitiated = '1' and startDataSend = '1' then
                                        case cont_steps is
                                                when 0 =>
                                                        data_byte_tx <= byte_to_transmit;
                                                        tx_start <= '0';
                                                when 1 =>
                                                        tx_start <= '1';
                                                when others =>
                                                        null;
                                        end case;
                                        if cont_steps < 3 then
                                                cont_steps := cont_steps + 1;
                                        else
                                                cont_steps := 3;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        -- Process to send the ACK signal, remember that optimally this ACK should be as fast as possible
        -- to avoid locking the bus, on this case if you send a more bytes then you can transmit the ideal
        -- is to create an error flag to indicate overrun.
        -- On this case on any attempt of reading or writting on registers we will be lock on 1 cycle
        process (clk, rst, startConfigBaud, startConfigClk, startDataSend, startReadReg )
        variable joinSignal : std_logic_vector(3 downto 0);
        variable cont_steps : integer range 0 to 3;
        begin
                if rising_edge(clk) then
                        if rst = '1' then
                                done <= '1';
                                cont_steps := 0;
                        else
                                joinSignal := startConfigBaud & startConfigClk & startDataSend & startReadReg;
                                if (joinSignal = "0000") then
                                        done <= '1';
                                else
                                        case cont_steps is
                                                when 0 =>
                                                        if start = '1' then
                                                                done <= '0';
                                                        end if;
                                                when others =>
                                                        done <= '1';
                                        end case;
 
                                        if cont_steps < 2 then
                                                cont_steps := cont_steps + 1;
                                        else
                                                cont_steps := 0;
                                        end if;
                                end if;
                        end if;
                end if;
        end process;
 
        -- Process to calculate the amount of cycles to wait (clock_speed / desired_baud), and initiate the board
        process (startConfigBaud,startConfigClk, clk)
        variable cont_steps : integer range 0 to 3;
        begin
                if (alreadyConfClk and alreadyConfBaud) = '0' then
                        sigDivRst <= '1';
                        cont_steps := 0;
                        baud_wait <= (others => '0');
                        commBlocksInitiated <= '0';
                elsif rising_edge(clk) then
                        if cont_steps < 3 then
                                cont_steps := cont_steps + 1;
                        else
                                cont_steps := 3;
                        end if;
 
                        case cont_steps is
                                when 1 =>
                                        sigDivNumerator <= config_clk;
                                        sigDivDividend <= config_baud;
                                        sigDivRst <= '1';
                                when 2 =>
                                        sigDivRst <= '0';
                                when others =>
                                        null;
                        end case;
 
                        -- Enable the communication block when the baud is calculated
                        if sigDivDone = '1' then
                                rst_comm_blocks <= '0';
                                baud_wait <= sigDivQuotient;
                                commBlocksInitiated <= '1';
                        else
                                baud_wait <= (others => '0');
                                rst_comm_blocks <= '1';
                                commBlocksInitiated <= '0';
                        end if;
                end if;
        end process;
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	9	leonardoar	`--! uart control unit`
2			`library IEEE;`
3	22	leonardoar	`use IEEE.STD_LOGIC_1164.ALL;`
4			`use ieee.std_logic_unsigned.all;`
5			`use ieee.std_logic_arith.all;`
6	9	leonardoar
7			`--! Use CPU Definitions package`
8			`use work.pkgDefinitions.all;`
9
10			`entity uart_control is`
11	13	leonardoar	`Port ( rst : in std_logic; -- Global reset`
12			`clk : in std_logic; -- Global clock`
13			`WE : in std_logic; -- Write enable`
14			`reg_addr : in std_logic_vector (1 downto 0); -- Register address`
15	10	leonardoar	`start : in std_logic; -- Start (Strobe)`
16			`done : out std_logic; -- Done (ACK)`
17	13	leonardoar	`DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)`
18			`DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)`
19			`baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency`
20	10	leonardoar	`data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter`
21			`data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver`
22	13	leonardoar	`tx_data_sent : in std_logic; -- Signal comming from serial_transmitter`
23	14	leonardoar	`tx_start : out std_logic; -- Signal to start sending serial data...`
24	13	leonardoar	`rst_comm_blocks : out std_logic; -- Reset Communication blocks`
25			`rx_data_ready : in std_logic); -- Signal comming from serial_receiver`
26	9	leonardoar	`end uart_control;`
27
28			`architecture Behavioral of uart_control is`
29			`signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);`
30			`signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);`
31	22	leonardoar	`signal received_byte : std_logic_vector((nBits-1) downto 0);`
32			`signal byte_to_transmit : std_logic_vector((nBits-1) downto 0);`
33	9	leonardoar
34			`signal sigDivRst : std_logic;`
35			`signal sigDivDone : std_logic;`
36			`signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);`
37			`signal sigDivNumerator : std_logic_vector((nBitsLarge-1) downto 0);`
38	22	leonardoar	`signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0);`
39
40			`-- Signals used to control the configuration`
41			`signal startConfigBaud : std_logic;`
42			`signal startConfigClk : std_logic;`
43			`signal startDataSend : std_logic;`
44			`signal commBlocksInitiated : std_logic;`
45			`signal doneWriteReg : std_logic;`
46	23	leonardoar	`signal startReadReg : std_logic;`
47			`signal alreadyConfBaud : std_logic;`
48			`signal alreadyConfClk : std_logic;`
49	9	leonardoar
50			`-- Divisor component`
51			`component divisor is`
52			`Port ( rst : in STD_LOGIC;`
53			`clk : in STD_LOGIC;`
54			`quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);`
55			`reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);`
56			`numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);`
57			`divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);`
58			`done : out STD_LOGIC);`
59			`end component;`
60
61			`begin`
62			`-- Instantiate block for calculate division`
63			`uDiv : divisor port map (`
64			`rst => sigDivRst,`
65			`clk => clk,`
66			`quotient => sigDivQuotient,`
67	16	leonardoar	`reminder => open, -- Indicates that this port will not be connected to anything`
68	9	leonardoar	`numerator => sigDivNumerator,`
69			`divident => sigDivDividend,`
70			`done => sigDivDone`
71			`);`
72
73	22	leonardoar	`-- Process to handle the of writting the registers`
74			`process (clk)`
75	10	leonardoar	`begin`
76	22	leonardoar	`-- On the wishbone specification we should handle the reset synchronously`
77			`if rising_edge(clk) then`
78			`if rst = '1' then`
79			`config_clk <= (others => '0');`
80			`config_baud <= (others => '0');`
81			`byte_to_transmit <= (others => '0');`
82			`startConfigBaud <= '0';`
83			`startConfigClk <= '0';`
84			`startDataSend <= '0';`
85			`doneWriteReg <= '0';`
86	23	leonardoar	`alreadyConfClk <= '0';`
87			`alreadyConfBaud <= '0';`
88	22	leonardoar	`elsif (WE and start) = '1' then`
89			`case reg_addr is`
90			`when "00" =>`
91			`config_clk <= DAT_I;`
92			`startConfigClk <= '1';`
93			`startDataSend <= '0';`
94			`startConfigBaud <= '0';`
95	23	leonardoar	`alreadyConfClk <= '1';`
96	22	leonardoar	`when "01" =>`
97			`config_baud <= DAT_I;`
98			`startConfigBaud <= '1';`
99			`startDataSend <= '0';`
100			`startConfigClk <= '0';`
101	23	leonardoar	`alreadyConfBaud <= '1';`
102	22	leonardoar	`when "10" =>`
103			`-- If we have an overrun, discard the byte`
104	23	leonardoar	`byte_to_transmit <= DAT_I((nBits-1) downto 0);`
105	22	leonardoar	`startConfigBaud <= '0';`
106			`startConfigClk <= '0';`
107			`startDataSend <= '1';`
108			`when others =>`
109			`startConfigBaud <= '0';`
110			`startConfigClk <= '0';`
111			`startDataSend <= '0';`
112			`end case;`
113			`end if;`
114			`end if;`
115	10	leonardoar	`end process;`
116
117	22	leonardoar	`-- Process to handle the reading of registers`
118			`process (clk)`
119			`begin`
120			`-- On the wishbone specification we should handle the reset synchronously`
121			`if rising_edge(clk) then`
122			`if rst = '1' then`
123			`DAT_O <= (others => 'Z');`
124			`startReadReg <= '0';`
125			`elsif ((WE = '0') and (start = '1')) then`
126			`startReadReg <= '1';`
127			`case reg_addr is`
128			`when "00" =>`
129			`DAT_O <= config_clk;`
130			`when "01" =>`
131			`DAT_O <= config_baud;`
132			`when "10" =>`
133			`DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & byte_to_transmit;`
134			`when "11" =>`
135			`DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & received_byte;`
136			`when others =>`
137			`null;`
138			`end case;`
139			`end if;`
140			`end if;`
141			`end process;`
142
143			`-- Process that stores the data that comes from the serial receiver block`
144			`process (rx_data_ready)`
145			`begin`
146			`if rising_edge(rx_data_ready) then`
147			`received_byte <= data_byte_rx;`
148			`else`
149			`received_byte <= received_byte;`
150			`end if;`
151			`end process;`
152
153			`-- Process to send data over the serial transmitter`
154	23	leonardoar	`process (clk)`
155	22	leonardoar	`variable cont_steps : integer range 0 to 3;`
156			`begin`
157	23	leonardoar	`if rising_edge(clk) then`
158			`if (rst = '1') then`
159			`cont_steps := 0;`
160			`else`
161			`if commBlocksInitiated = '1' and startDataSend = '1' then`
162			`case cont_steps is`
163			`when 0 =>`
164			`data_byte_tx <= byte_to_transmit;`
165			`tx_start <= '0';`
166			`when 1 =>`
167			`tx_start <= '1';`
168			`when others =>`
169			`null;`
170			`end case;`
171			`if cont_steps < 3 then`
172			`cont_steps := cont_steps + 1;`
173			`else`
174			`cont_steps := 3;`
175			`end if;`
176			`end if;`
177	22	leonardoar	`end if;`
178			`end if;`
179			`end process;`
180
181			`-- Process to send the ACK signal, remember that optimally this ACK should be as fast as possible`
182			`-- to avoid locking the bus, on this case if you send a more bytes then you can transmit the ideal`
183			`-- is to create an error flag to indicate overrun.`
184			`-- On this case on any attempt of reading or writting on registers we will be lock on 1 cycle`
185			`process (clk, rst, startConfigBaud, startConfigClk, startDataSend, startReadReg )`
186			`variable joinSignal : std_logic_vector(3 downto 0);`
187			`variable cont_steps : integer range 0 to 3;`
188			`begin`
189			`if rising_edge(clk) then`
190			`if rst = '1' then`
191			`done <= '1';`
192			`cont_steps := 0;`
193			`else`
194			`joinSignal := startConfigBaud & startConfigClk & startDataSend & startReadReg;`
195			`if (joinSignal = "0000") then`
196	10	leonardoar	`done <= '1';`
197	22	leonardoar	`else`
198			`case cont_steps is`
199			`when 0 =>`
200			`if start = '1' then`
201			`done <= '0';`
202			`end if;`
203			`when others =>`
204			`done <= '1';`
205			`end case;`
206	10	leonardoar
207	22	leonardoar	`if cont_steps < 2 then`
208			`cont_steps := cont_steps + 1;`
209	10	leonardoar	`else`
210	22	leonardoar	`cont_steps := 0;`
211	10	leonardoar	`end if;`
212	22	leonardoar	`end if;`
213			`end if;`
214			`end if;`
215			`end process;`
216
217			`-- Process to calculate the amount of cycles to wait (clock_speed / desired_baud), and initiate the board`
218			`process (startConfigBaud,startConfigClk, clk)`
219			`variable cont_steps : integer range 0 to 3;`
220			`begin`
221	23	leonardoar	`if (alreadyConfClk and alreadyConfBaud) = '0' then`
222	22	leonardoar	`sigDivRst <= '1';`
223			`cont_steps := 0;`
224			`baud_wait <= (others => '0');`
225			`commBlocksInitiated <= '0';`
226			`elsif rising_edge(clk) then`
227			`if cont_steps < 3 then`
228			`cont_steps := cont_steps + 1;`
229			`else`
230			`cont_steps := 3;`
231			`end if;`
232
233			`case cont_steps is`
234			`when 1 =>`
235			`sigDivNumerator <= config_clk;`
236			`sigDivDividend <= config_baud;`
237			`sigDivRst <= '1';`
238			`when 2 =>`
239			`sigDivRst <= '0';`
240			`when others =>`
241			`null;`
242			`end case;`
243
244			`-- Enable the communication block when the baud is calculated`
245			`if sigDivDone = '1' then`
246			`rst_comm_blocks <= '0';`
247			`baud_wait <= sigDivQuotient;`
248			`commBlocksInitiated <= '1';`
249			`else`
250			`baud_wait <= (others => '0');`
251			`rst_comm_blocks <= '1';`
252			`commBlocksInitiated <= '0';`
253			`end if;`
254			`end if;`
255	9	leonardoar	`end process;`
256
257			`end Behavioral;`
258

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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [uart_control.vhd] - Blame information for rev 23