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[/] [uart_fiber/] [trunk/] [Version2/] [main.vhd] - Blame information for rev 8

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1 8 chipmaker7 
 
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.std_logic_unsigned.all;
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--use IEEE.NUMERIC_STD.ALL;
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entity main is
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    Port ( iCLK : in  STD_LOGIC;
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           RX : out  STD_LOGIC;
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           TX : in  STD_LOGIC;
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           optic_out : out  STD_LOGIC;
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           optic_in : in  STD_LOGIC;
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                          setting : in  STD_LOGIC_VECTOR(1 downto 0)
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                          --baud_div1 : in STD_LOGIC_VECTOR(3 downto 0);
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                          --period1 : in STD_LOGIC_VECTOR(3 downto 0)
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           --RX2 : out  STD_LOGIC;
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           --TX2 : in  STD_LOGIC;
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           --optic_out2 : out  STD_LOGIC;
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           --optic_in2 : in  STD_LOGIC;
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                          --led1 : out  STD_LOGIC;
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                          --led2 : out  STD_LOGIC;
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                          --led3 : out  STD_LOGIC;
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                          --led4 : out  STD_LOGIC
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                          );
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end main;
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architecture Behavioral of main is
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COMPONENT TX_to_spdif_full
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        PORT(
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                iCLK : IN std_logic;
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                TX : IN std_logic;
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                OPTIC_OUT : OUT std_logic;
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                period01 : in STD_LOGIC_VECTOR(6 downto 0);
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                periodA : in STD_LOGIC_VECTOR(6 downto 0);
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                period10 : in STD_LOGIC_VECTOR(6 downto 0);
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                period : in STD_LOGIC_VECTOR(6 downto 0);
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                baud_div : in STD_LOGIC_VECTOR(6 downto 0)
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                );
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        END COMPONENT;
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COMPONENT spdif_to_RX
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        PORT(
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                iCLK : IN std_logic;
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                OPTIC_IN : IN std_logic;
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                RX : OUT std_logic;
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                periodA : in STD_LOGIC_VECTOR(6 downto 0);
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                period10 : in STD_LOGIC_VECTOR(6 downto 0)
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                );
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        END COMPONENT;
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COMPONENT q_period is
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    PORT ( period : in  STD_LOGIC_VECTOR (6 downto 0);
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           period01 : out  STD_LOGIC_VECTOR (6 downto 0);
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           periodA : out  STD_LOGIC_VECTOR (6 downto 0);
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           period10 : out  STD_LOGIC_VECTOR (6 downto 0)
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                          );
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END COMPONENT;
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--signal nled1 : STD_LOGIC_VECTOR(3 downto 0);
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--constant period : STD_LOGIC_VECTOR(6 downto 0) := ('0','1','0','1','0','0','0'); --40
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--constant baud_div : STD_LOGIC_VECTOR(6 downto 0) := ('0','0','0','1','0','0','0'); --1
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signal period01 :STD_LOGIC_VECTOR(6 downto 0);
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signal periodA :STD_LOGIC_VECTOR(6 downto 0);
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signal period10 :STD_LOGIC_VECTOR(6 downto 0);
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signal period : STD_LOGIC_VECTOR(6 downto 0);--normally 40
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signal baud_div : STD_LOGIC_VECTOR(6 downto 0);--normally 1
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begin
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--led1<=not nled1(3);
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--led2<=not nled1(2);
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--led3<=not nled1(1);
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--led4<=not nled1(0);
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--period<=((6 downto 4=>'0')&period1);
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--baud_div<=((6 downto 4=>'0')&baud_div1);
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process
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begin
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        if(setting=('0','0'))then
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        period<=('0','1','0','1','0','0','0');
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        --period<=to_stdlogicvector("40");
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        baud_div<=('0','0','0','0','0','0','1');
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        elsif (setting=('0','0'))then
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        period<=('0','1','0','0','0','0','1');
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        baud_div<=('0','0','0','0','0','1','0');
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        elsif (setting=('0','0'))then
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        period<=('0','1','0','0','1','0','0');
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        baud_div<=('0','0','1','0','0','0','0');
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        else
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        period<=('0','1','0','0','0','1','0');
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        baud_div<=('0','0','0','1','1','1','0');
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        end if;
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end process;
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q_period_inst:q_period
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 Port map (period=>period,
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                                period01=>period01,
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                                periodA=>periodA,
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                                period10=>period10
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                                );
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TX_to_spdif_full_inst:TX_to_spdif_full
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    Port map ( iCLK=> iCLK,
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              TX => TX,
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                                  optic_out => optic_out,
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                                  period01=>period01,
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                                  periodA=>periodA,
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                                  period10=>period10,
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                                  period=>period,
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                                  baud_div=>baud_div
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                                  );
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spdif_to_RX_inst:spdif_to_RX
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    Port map ( iCLK=>iCLK,
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                                        optic_in => optic_in,
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                                        RX => RX,
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                                        periodA=>periodA,
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                                        period10=>period10
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                                  );
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end Behavioral;
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