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[/] [uart_fiber/] [trunk/] [Version3/] [TX_to_spdif_full.vhd] - Blame information for rev 16

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1 16 chipmaker7 
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.std_logic_unsigned.all;
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--use IEEE.NUMERIC_STD.ALL;
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entity TX_to_spdif_full is
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    Port ( iCLK : in  STD_LOGIC;
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           TX : in  STD_LOGIC;
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           optic_out : out  STD_LOGIC;
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                          period01 : in STD_LOGIC_VECTOR(6 downto 0);
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                          periodA : in STD_LOGIC_VECTOR(6 downto 0);
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                          period10 : in STD_LOGIC_VECTOR(6 downto 0);
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                          period : in STD_LOGIC_VECTOR(6 downto 0);
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                          baud_div : in STD_LOGIC_VECTOR(6 downto 0)
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                          );
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end TX_to_spdif_full;
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architecture Behavioral of TX_to_spdif_full is
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--output flip-flop
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signal optic_flop:STD_LOGIC:='0';
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--optic stage
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signal optic_cnt : STD_LOGIC_VECTOR(6 downto 0):=(0=>'1',others=>'0');     --count 1 to Fosc/fiber bitrate
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signal optic_bit:STD_LOGIC;
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--input stage
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signal tx_cnt : STD_LOGIC_VECTOR(6 downto 0);            --count 1 to Fosc/fiber bitrate
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signal tx_bit:STD_LOGIC:='1';                                                           --bit received on TX
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signal start_detected : STD_LOGIC:='0';
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signal bit_position : STD_LOGIC_VECTOR(3 downto 0);--value 0-9 (bit position from start to stop)
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--baud division
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signal baud_div_cnt : STD_LOGIC_VECTOR(6 downto 0);--fiber bitrate / TX bitrate
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begin
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optic_out<=optic_flop;  --output (fiber optic)
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--generate signal on fiber optic
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optic_stage:process (iCLK)
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begin
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if (iCLK'event and iCLK = '1') then
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        if(optic_cnt = period) then
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                optic_cnt<=(0=>'1',others=>'0');
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        else
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                optic_cnt<=optic_cnt+1;
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        end if;
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        if((optic_cnt=periodA) or
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        ((optic_cnt=period10 or optic_cnt=period01) and optic_bit='1')) then
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                optic_flop<=not optic_flop;--other edge
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        end if;
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        if(optic_cnt=period)then
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                optic_flop<='1';                                --rising edge
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        end if;
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        if(optic_cnt=period) then
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                        optic_bit<=tx_bit;              --reload input at fiber baud rate
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        end if;
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end if;
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end process;
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--Synchronize input (TX pin) with local clock
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input_stage: process (iCLK,TX)
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begin
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if (iCLK'event and iCLK = '1') then
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        if(start_detected='0') then
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                if(TX='0') then
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                        start_detected<='1';
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                        tx_cnt<=(0=>'1',others=>'0');
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                        bit_position<=(others=>'0');
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                        baud_div_cnt<=(0=>'1',others=>'0');
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                end if;
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        else                                                                                    --start detected=1
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                if(baud_div_cnt=baud_div)then           --multiply with baud div
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                        if(tx_cnt=periodA)then
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                                tx_bit<=TX;                                             --sample every bit time (n+0.5 bit time from start)
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                        elsif(tx_cnt=period10)then
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                                if(tx_bit='1' and bit_position=9 and baud_div>2)then
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                                        start_detected<='0';             --resync early stop length >=3/4 period
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                                end if;
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                        elsif(tx_cnt=period)then
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                                if(bit_position/=9)then
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                                        bit_position<=bit_position+1;
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                                end if;
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                                if(bit_position=9 and tx_bit='1') then --stop bit
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                                        bit_position<=(others=>'0');
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                                        if(TX='1')then
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                                                start_detected<='0';     --resync
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                                        end if;
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                                end if;
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                        end if;
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                        if(tx_cnt=period)then
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                                tx_cnt<=(0=>'1',others=>'0');
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                        else
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                                tx_cnt<=tx_cnt+1;
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                        end if;
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                        baud_div_cnt<=(0=>'1',others=>'0');
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                else
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                        baud_div_cnt<=baud_div_cnt+1;
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                end if;--baud_div
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        end if;--start detected
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end if;--clk event
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end process;
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end Behavioral;
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