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[/] [uart_fiber/] [trunk/] [Version3/] [main.vhd] - Blame information for rev 15

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
--use IEEE.NUMERIC_STD.ALL;
 
 
entity main is
    Port ( iCLK : in  STD_LOGIC;
           RX : out  STD_LOGIC;
           TX : in  STD_LOGIC;
           optic_out : out  STD_LOGIC;
           optic_in : in  STD_LOGIC;
 
                          setting : in  STD_LOGIC_VECTOR(1 downto 0)
 
 
                          );
end main;
 
architecture Behavioral of main is
 
 
 
 
COMPONENT TX_to_spdif_full
        PORT(
                iCLK : IN std_logic;
                TX : IN std_logic;
                OPTIC_OUT : OUT std_logic;
                period01 : in STD_LOGIC_VECTOR(6 downto 0);
                periodA : in STD_LOGIC_VECTOR(6 downto 0);
                period10 : in STD_LOGIC_VECTOR(6 downto 0);
                period : in STD_LOGIC_VECTOR(6 downto 0);
                baud_div : in STD_LOGIC_VECTOR(6 downto 0)
 
 
                );
        END COMPONENT;
COMPONENT spdif_to_RX
        PORT(
                iCLK : IN std_logic;
                OPTIC_IN : IN std_logic;
                RX : OUT std_logic;
 
                periodA : in STD_LOGIC_VECTOR(6 downto 0);
                period10 : in STD_LOGIC_VECTOR(6 downto 0)
 
 
 
                );
        END COMPONENT;
 
 
COMPONENT q_period is
    PORT ( period : in  STD_LOGIC_VECTOR (6 downto 0);
           period01 : out  STD_LOGIC_VECTOR (6 downto 0);
           periodA : out  STD_LOGIC_VECTOR (6 downto 0);
           period10 : out  STD_LOGIC_VECTOR (6 downto 0)
                          );
END COMPONENT;
 
 
signal period01 :STD_LOGIC_VECTOR(6 downto 0);
signal periodA :STD_LOGIC_VECTOR(6 downto 0);
signal period10 :STD_LOGIC_VECTOR(6 downto 0);
 
signal period : STD_LOGIC_VECTOR(6 downto 0);
signal baud_div : STD_LOGIC_VECTOR(6 downto 0);
 
 
 
 
begin
 
process(setting)
 
begin
 
        if(setting(1 downto 0)="00")then--2.5Mb/s
        period<=('0','0','1','0','1','0','0');--20
        baud_div<=(0=>'1',others=>'0');--1
        elsif(setting(1 downto 0)="01")then--1.25Mb/s
        period<=('0','0','1','0','1','0','0');--20
        baud_div<=(1=>'1',others=>'0');--2
        else--115207 b/s
        --period<=('0','1','1','1','1','1','0');--62
        --baud_div<=('0','0','0','0','1','1','1');--7
        period<=('0','0','1','0','1','0','0');--20
        baud_div<=('0','0','0','0','1','0','1');--5
        end if;
 
end process;
 
 
 
 
 
q_period_inst:q_period
 Port map (period=>period,
                                period01=>period01,
                                periodA=>periodA,
                                period10=>period10
                                );
 
TX_to_spdif_full_inst:TX_to_spdif_full
    Port map ( iCLK=> iCLK,
              TX => TX,
                                  optic_out => optic_out,
                                  period01=>period01,
                                  periodA=>periodA,
                                  period10=>period10,
                                  period=>period,
                                  baud_div=>baud_div
                                  );
spdif_to_RX_inst:spdif_to_RX
    Port map ( iCLK=>iCLK,
                                        optic_in => optic_in,
                                        RX => RX,
                                        periodA=>periodA,
                                        period10=>period10
 
 
                                  );
 
 
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	15	chipmaker7
2			`library IEEE;`
3			`use IEEE.STD_LOGIC_1164.ALL;`
4
5			`use IEEE.STD_LOGIC_ARITH.ALL;`
6			`use IEEE.std_logic_unsigned.all;`
7			`--use IEEE.NUMERIC_STD.ALL;`
8
9
10			`entity main is`
11			`Port ( iCLK : in STD_LOGIC;`
12			`RX : out STD_LOGIC;`
13			`TX : in STD_LOGIC;`
14			`optic_out : out STD_LOGIC;`
15			`optic_in : in STD_LOGIC;`
16
17			`setting : in STD_LOGIC_VECTOR(1 downto 0)`
18
19
20			`);`
21			`end main;`
22
23			`architecture Behavioral of main is`
24
25
26
27
28			`COMPONENT TX_to_spdif_full`
29			`PORT(`
30			`iCLK : IN std_logic;`
31			`TX : IN std_logic;`
32			`OPTIC_OUT : OUT std_logic;`
33			`period01 : in STD_LOGIC_VECTOR(6 downto 0);`
34			`periodA : in STD_LOGIC_VECTOR(6 downto 0);`
35			`period10 : in STD_LOGIC_VECTOR(6 downto 0);`
36			`period : in STD_LOGIC_VECTOR(6 downto 0);`
37			`baud_div : in STD_LOGIC_VECTOR(6 downto 0)`
38
39
40			`);`
41			`END COMPONENT;`
42			`COMPONENT spdif_to_RX`
43			`PORT(`
44			`iCLK : IN std_logic;`
45			`OPTIC_IN : IN std_logic;`
46			`RX : OUT std_logic;`
47
48			`periodA : in STD_LOGIC_VECTOR(6 downto 0);`
49			`period10 : in STD_LOGIC_VECTOR(6 downto 0)`
50
51
52
53			`);`
54			`END COMPONENT;`
55
56
57			`COMPONENT q_period is`
58			`PORT ( period : in STD_LOGIC_VECTOR (6 downto 0);`
59			`period01 : out STD_LOGIC_VECTOR (6 downto 0);`
60			`periodA : out STD_LOGIC_VECTOR (6 downto 0);`
61			`period10 : out STD_LOGIC_VECTOR (6 downto 0)`
62			`);`
63			`END COMPONENT;`
64
65
66			`signal period01 :STD_LOGIC_VECTOR(6 downto 0);`
67			`signal periodA :STD_LOGIC_VECTOR(6 downto 0);`
68			`signal period10 :STD_LOGIC_VECTOR(6 downto 0);`
69
70			`signal period : STD_LOGIC_VECTOR(6 downto 0);`
71			`signal baud_div : STD_LOGIC_VECTOR(6 downto 0);`
72
73
74
75
76			`begin`
77
78			`process(setting)`
79
80			`begin`
81
82			`if(setting(1 downto 0)="00")then--2.5Mb/s`
83			`period<=('0','0','1','0','1','0','0');--20`
84			`baud_div<=(0=>'1',others=>'0');--1`
85			`elsif(setting(1 downto 0)="01")then--1.25Mb/s`
86			`period<=('0','0','1','0','1','0','0');--20`
87			`baud_div<=(1=>'1',others=>'0');--2`
88			`else--115207 b/s`
89			`--period<=('0','1','1','1','1','1','0');--62`
90			`--baud_div<=('0','0','0','0','1','1','1');--7`
91			`period<=('0','0','1','0','1','0','0');--20`
92			`baud_div<=('0','0','0','0','1','0','1');--5`
93			`end if;`
94
95			`end process;`
96
97
98
99
100
101			`q_period_inst:q_period`
102			`Port map (period=>period,`
103			`period01=>period01,`
104			`periodA=>periodA,`
105			`period10=>period10`
106			`);`
107
108			`TX_to_spdif_full_inst:TX_to_spdif_full`
109			`Port map ( iCLK=> iCLK,`
110			`TX => TX,`
111			`optic_out => optic_out,`
112			`period01=>period01,`
113			`periodA=>periodA,`
114			`period10=>period10,`
115			`period=>period,`
116			`baud_div=>baud_div`
117			`);`
118			`spdif_to_RX_inst:spdif_to_RX`
119			`Port map ( iCLK=>iCLK,`
120			`optic_in => optic_in,`
121			`RX => RX,`
122			`periodA=>periodA,`
123			`period10=>period10`
124
125
126			`);`
127
128
129
130			`end Behavioral;`
131

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[/] [uart_fiber/] [trunk/] [Version3/] [main.vhd] - Blame information for rev 15