1 |
3 |
aborga |
-------------------------------------------------------------------------------
|
2 |
|
|
-- --
|
3 |
|
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-- --
|
4 |
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-- --
|
5 |
|
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-- --
|
6 |
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-------------------------------------------------------------------------------
|
7 |
|
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--
|
8 |
|
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-- unit name: register_tx_handler
|
9 |
|
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--
|
10 |
15 |
aborga |
-- author: Mauro Predonzani (predmauro@libero.it)
|
11 |
3 |
aborga |
--
|
12 |
|
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-- date: 20/02/2009 $: created
|
13 |
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--
|
14 |
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-- version: $Rev 1.0 $:
|
15 |
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--
|
16 |
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-- description:
|
17 |
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--
|
18 |
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-- the module acquires byte
|
19 |
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-- and decodes the data as follows:
|
20 |
|
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--
|
21 |
|
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-- reghnd_addr_wwo_i= 1 (with)
|
22 |
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-- -----------------------------------------------------
|
23 |
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-- | ADDRESS | DATA |
|
24 |
|
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-- -----------------------------------------------------
|
25 |
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-- | 15-08 | 07-00 | 31-24 | 23-16 | 15-08 | 07-00 |
|
26 |
|
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-- | full_add_ram_i | reghnd_full_data_ram_i |
|
27 |
|
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-- -----------------------------------------------------
|
28 |
|
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-- BYTE NUM | BYTEO | BYTE1 | BYTE2 | BYTE3 | BYTE4 | BYTE5 |
|
29 |
|
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-- -----------------------------------------------------
|
30 |
|
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--
|
31 |
|
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-- reghnd_addr_wwo_i= 0 (without)
|
32 |
|
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-- ---------------------------------
|
33 |
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-- | DATA |
|
34 |
|
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-- ---------------------------------
|
35 |
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-- | 31-24 | 23-16 | 15-08 | 07-00 |
|
36 |
|
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-- | reghnd_full_data_ram_i |
|
37 |
|
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-- ---------------------------------
|
38 |
|
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-- BYTE NUM | BYTE0 | BYTE1 | BYTE2 | BYTE3 |
|
39 |
|
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-- ---------------------------------
|
40 |
|
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--
|
41 |
|
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-- number of register cells: 2^16
|
42 |
|
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-- data word lenght: 32 bits
|
43 |
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--
|
44 |
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--
|
45 |
19 |
aborga |
-- dependencies: uart_wrapper
|
46 |
3 |
aborga |
-- uart_lbus_slave
|
47 |
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-- gh_uart_16550
|
48 |
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--
|
49 |
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-- references: <reference one>
|
50 |
|
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-- <reference two> ...
|
51 |
|
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--
|
52 |
|
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-- modified by: $Author:: $:
|
53 |
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--
|
54 |
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-------------------------------------------------------------------------------
|
55 |
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-- last changes: 2010-06-09 enable/disable TX address byte -- Mauro Predonzani
|
56 |
|
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-- <extended description>
|
57 |
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-------------------------------------------------------------------------------
|
58 |
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-- TODO:
|
59 |
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--
|
60 |
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--
|
61 |
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--
|
62 |
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--
|
63 |
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-------------------------------------------------------------------------------
|
64 |
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|
65 |
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--=============================================================================
|
66 |
|
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-- Libraries
|
67 |
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--=============================================================================
|
68 |
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|
69 |
|
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library ieee ;
|
70 |
|
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use ieee.std_logic_1164.all ;
|
71 |
|
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use ieee.std_logic_arith.all;
|
72 |
|
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use ieee.std_logic_unsigned.all;
|
73 |
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|
74 |
|
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--=============================================================================
|
75 |
|
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-- Entity declaration for ada_register_handler
|
76 |
|
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--=============================================================================
|
77 |
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|
78 |
|
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entity register_tx_handler is
|
79 |
|
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port(
|
80 |
|
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reghnd_clk : in std_logic; -- system clock
|
81 |
|
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reghnd_rst : in std_logic; -- system reset
|
82 |
|
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reghnd_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
|
83 |
|
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reghnd_full_data_ram_i : in std_logic_vector(31 downto 0); -- 32 bits full data
|
84 |
|
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reghnd_full_add_ram_i : in std_logic_vector(15 downto 0); -- 16 bits full addr
|
85 |
|
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reghnd_stb_data_ram_rdy_i : in std_logic; -- strobe ram data ready
|
86 |
|
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reghnd_data_acq_gh16550_i : in std_logic; -- data acquired from gh16550
|
87 |
|
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reghnd_wr_enable_i : in std_logic; -- enable the tx process
|
88 |
|
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reghnd_txrdy_n_gh16550_i : in std_logic; -- gh16550 ready to trasmit
|
89 |
|
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reghnd_wr_enable_o : out std_logic; -- enable the tx process
|
90 |
|
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reghnd_output_rdy_o : out std_logic; -- Read data ready
|
91 |
|
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reghnd_pdata_o : out std_logic_vector(7 downto 0); -- 8 bits parallel
|
92 |
|
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reghnd_stb_acq_ram_o : out std_logic -- strobe data/address acquired (1 acquired - 0 not acquired)
|
93 |
|
|
);
|
94 |
|
|
end entity;
|
95 |
|
|
|
96 |
|
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--=============================================================================
|
97 |
|
|
-- architecture declaration
|
98 |
|
|
--=============================================================================
|
99 |
|
|
|
100 |
|
|
architecture tx_handler of register_tx_handler is
|
101 |
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|
102 |
|
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
103 |
|
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-- Components declaration
|
104 |
|
|
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
105 |
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|
106 |
|
|
|
107 |
|
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--
|
108 |
|
|
-- Internal signal declaration
|
109 |
|
|
--
|
110 |
|
|
|
111 |
|
|
signal s_rst : std_logic; -- global reset
|
112 |
|
|
signal s_clk : std_logic; -- uart to parallel interface clock
|
113 |
|
|
signal s_tick : std_logic_vector (1 downto 0);
|
114 |
|
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signal v_tx_stream : std_logic_vector(47 downto 0);
|
115 |
|
|
--
|
116 |
|
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-- State Machine states
|
117 |
|
|
--
|
118 |
|
|
|
119 |
|
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type t_reg_decoder is (IDLE, READ_RAM, BYTE0, BYTE1, BYTE2, BYTE3, BYTE4, BYTE5 );
|
120 |
|
|
signal s_reg_decoder : t_reg_decoder;
|
121 |
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|
122 |
|
|
--=============================================================================
|
123 |
|
|
-- architecture begin
|
124 |
|
|
--=============================================================================
|
125 |
|
|
|
126 |
|
|
begin
|
127 |
|
|
|
128 |
|
|
s_rst <= reghnd_rst;
|
129 |
|
|
s_clk <= reghnd_clk;
|
130 |
|
|
|
131 |
|
|
p_tx_handler : process(s_rst, s_clk)
|
132 |
|
|
begin
|
133 |
|
|
if s_rst = '1' then -- reset
|
134 |
|
|
reghnd_wr_enable_o <= '0';
|
135 |
|
|
reghnd_output_rdy_o <= '0';
|
136 |
|
|
reghnd_pdata_o <= (others => '0');
|
137 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
138 |
|
|
s_tick <= "00";
|
139 |
|
|
v_tx_stream <= (others => '0');
|
140 |
|
|
s_reg_decoder <= IDLE;
|
141 |
|
|
elsif Rising_edge(s_clk) then
|
142 |
|
|
case s_reg_decoder is
|
143 |
|
|
when IDLE => -- IDLE state
|
144 |
|
|
reghnd_wr_enable_o <= '0';
|
145 |
|
|
reghnd_output_rdy_o <= '0';
|
146 |
|
|
reghnd_pdata_o <= (others => '0');
|
147 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
148 |
|
|
s_tick <= "00";
|
149 |
|
|
if reghnd_txrdy_n_gh16550_i = '0' and reghnd_stb_data_ram_rdy_i = '1' then -- check if BYTE0 is ready
|
150 |
|
|
s_reg_decoder <= READ_RAM;
|
151 |
|
|
else
|
152 |
|
|
s_reg_decoder <= IDLE;
|
153 |
|
|
end if;
|
154 |
|
|
when READ_RAM =>
|
155 |
|
|
if s_tick = "00" then -- only first time in this cycle acq the byte
|
156 |
|
|
v_tx_stream (47 downto 32) <= reghnd_full_add_ram_i;
|
157 |
|
|
v_tx_stream (31 downto 0) <= reghnd_full_data_ram_i;
|
158 |
|
|
reghnd_pdata_o <= (others => '0');
|
159 |
|
|
reghnd_stb_acq_ram_o <= '1';
|
160 |
|
|
s_tick <= "01";
|
161 |
|
|
reghnd_wr_enable_o <= '0';
|
162 |
|
|
elsif reghnd_wr_enable_i = '0' then
|
163 |
|
|
s_reg_decoder <= IDLE;
|
164 |
|
|
reghnd_pdata_o <= (others => '0');
|
165 |
|
|
s_tick <= "00";
|
166 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
167 |
|
|
reghnd_wr_enable_o <= '0';
|
168 |
|
|
elsif reghnd_txrdy_n_gh16550_i = '0' and reghnd_wr_enable_i = '1' then -- if uart is lbus and gh16550 is ready then tx BYTE0
|
169 |
|
|
if reghnd_addr_wwo_i = '1' then
|
170 |
|
|
s_reg_decoder <= BYTE0;
|
171 |
|
|
reghnd_pdata_o <= v_tx_stream (47 downto 40);
|
172 |
|
|
else
|
173 |
|
|
s_reg_decoder <= BYTE2;
|
174 |
|
|
reghnd_pdata_o <= v_tx_stream (31 downto 24);
|
175 |
|
|
end if;
|
176 |
|
|
s_tick <= "00";
|
177 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
178 |
|
|
reghnd_wr_enable_o <= '1'; -- inizio la trasmissione
|
179 |
|
|
else
|
180 |
|
|
reghnd_pdata_o <= v_tx_stream (47 downto 40);
|
181 |
|
|
s_reg_decoder <= READ_RAM;
|
182 |
|
|
s_tick <= "01";
|
183 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
184 |
|
|
reghnd_wr_enable_o <= '0';
|
185 |
|
|
end if;
|
186 |
|
|
when BYTE0 => -- send byte 0 ADDRESS higher
|
187 |
|
|
reghnd_wr_enable_o <= '1';
|
188 |
|
|
if s_tick = "00" then -- only first time in this cycle acq the byte
|
189 |
|
|
s_reg_decoder <= BYTE0;
|
190 |
|
|
reghnd_output_rdy_o <= '1';
|
191 |
|
|
reghnd_pdata_o <= v_tx_stream (47 downto 40);
|
192 |
|
|
if reghnd_data_acq_gh16550_i = '1' then
|
193 |
|
|
s_tick <= "01";
|
194 |
|
|
else
|
195 |
|
|
s_tick <= "00";
|
196 |
|
|
end if;
|
197 |
|
|
elsif s_tick = "01" then
|
198 |
|
|
s_tick <= "11";
|
199 |
|
|
s_reg_decoder <= BYTE0;
|
200 |
|
|
reghnd_output_rdy_o <= '1';
|
201 |
|
|
reghnd_pdata_o <= v_tx_stream (47 downto 40);
|
202 |
|
|
elsif s_tick = "11" then
|
203 |
|
|
s_tick <= "10";
|
204 |
|
|
s_reg_decoder <= BYTE0;
|
205 |
|
|
reghnd_output_rdy_o <= '1';
|
206 |
|
|
reghnd_pdata_o <= v_tx_stream (47 downto 40);
|
207 |
|
|
elsif reghnd_txrdy_n_gh16550_i = '0' and reghnd_wr_enable_i = '1' then -- if uart is lbus and gh16550 is ready then tx BYTE0
|
208 |
|
|
s_reg_decoder <= BYTE1;
|
209 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
210 |
|
|
reghnd_pdata_o <= v_tx_stream (39 downto 32);
|
211 |
|
|
reghnd_output_rdy_o <= '0';
|
212 |
|
|
s_tick <= "00";
|
213 |
|
|
else
|
214 |
|
|
s_reg_decoder <= BYTE0;
|
215 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
216 |
|
|
reghnd_pdata_o <= v_tx_stream (39 downto 32);
|
217 |
|
|
reghnd_output_rdy_o <= '0';
|
218 |
|
|
s_tick <= "10";
|
219 |
|
|
end if;
|
220 |
|
|
when BYTE1 => -- send byte 1 ADDRESS lower
|
221 |
|
|
reghnd_wr_enable_o <= '1';
|
222 |
|
|
if s_tick = "00" then -- only first time in this cycle acq the byte
|
223 |
|
|
s_reg_decoder <= BYTE1;
|
224 |
|
|
reghnd_output_rdy_o <= '1';
|
225 |
|
|
reghnd_pdata_o <= v_tx_stream (39 downto 32);
|
226 |
|
|
if reghnd_data_acq_gh16550_i = '1' then
|
227 |
|
|
s_tick <= "01";
|
228 |
|
|
else
|
229 |
|
|
s_tick <= "00";
|
230 |
|
|
end if;
|
231 |
|
|
elsif s_tick = "01" then
|
232 |
|
|
s_tick <= "11";
|
233 |
|
|
s_reg_decoder <= BYTE1;
|
234 |
|
|
reghnd_output_rdy_o <= '1';
|
235 |
|
|
reghnd_pdata_o <= v_tx_stream (39 downto 32);
|
236 |
|
|
elsif s_tick = "11" then
|
237 |
|
|
s_tick <= "10";
|
238 |
|
|
s_reg_decoder <= BYTE1;
|
239 |
|
|
reghnd_output_rdy_o <= '1';
|
240 |
|
|
reghnd_pdata_o <= v_tx_stream (39 downto 32);
|
241 |
|
|
elsif reghnd_txrdy_n_gh16550_i = '0' and reghnd_wr_enable_i = '1' then -- if uart is lbus and gh16550 is ready then tx BYTE0
|
242 |
|
|
s_reg_decoder <= BYTE2;
|
243 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
244 |
|
|
reghnd_pdata_o <= v_tx_stream (31 downto 24);
|
245 |
|
|
reghnd_output_rdy_o <= '0';
|
246 |
|
|
s_tick <= "00";
|
247 |
|
|
else
|
248 |
|
|
s_reg_decoder <= BYTE1;
|
249 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
250 |
|
|
reghnd_pdata_o <= v_tx_stream (31 downto 24);
|
251 |
|
|
reghnd_output_rdy_o <= '0';
|
252 |
|
|
s_tick <= "10";
|
253 |
|
|
end if;
|
254 |
|
|
when BYTE2 => -- send byte 2 DATA1
|
255 |
|
|
reghnd_wr_enable_o <= '1';
|
256 |
|
|
if s_tick = "00" then -- only first time in this cycle acq the byte
|
257 |
|
|
s_reg_decoder <= BYTE2;
|
258 |
|
|
reghnd_output_rdy_o <= '1';
|
259 |
|
|
reghnd_pdata_o <= v_tx_stream (31 downto 24);
|
260 |
|
|
if reghnd_data_acq_gh16550_i = '1' then
|
261 |
|
|
s_tick <= "01";
|
262 |
|
|
else
|
263 |
|
|
s_tick <= "00";
|
264 |
|
|
end if;
|
265 |
|
|
elsif s_tick = "01" then
|
266 |
|
|
s_tick <= "11";
|
267 |
|
|
s_reg_decoder <= BYTE2;
|
268 |
|
|
reghnd_output_rdy_o <= '1';
|
269 |
|
|
reghnd_pdata_o <= v_tx_stream (31 downto 24);
|
270 |
|
|
elsif s_tick = "11" then
|
271 |
|
|
s_tick <= "10";
|
272 |
|
|
s_reg_decoder <= BYTE2;
|
273 |
|
|
reghnd_output_rdy_o <= '1';
|
274 |
|
|
reghnd_pdata_o <= v_tx_stream (31 downto 24);
|
275 |
|
|
elsif reghnd_txrdy_n_gh16550_i = '0' and reghnd_wr_enable_i = '1' then -- if uart is lbus and gh16550 is ready then tx BYTE0
|
276 |
|
|
s_reg_decoder <= BYTE3;
|
277 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
278 |
|
|
reghnd_pdata_o <= v_tx_stream (23 downto 16);
|
279 |
|
|
reghnd_output_rdy_o <= '0';
|
280 |
|
|
s_tick <= "00";
|
281 |
|
|
else
|
282 |
|
|
s_reg_decoder <= BYTE2;
|
283 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
284 |
|
|
reghnd_pdata_o <= v_tx_stream (23 downto 16);
|
285 |
|
|
reghnd_output_rdy_o <= '0';
|
286 |
|
|
s_tick <= "10";
|
287 |
|
|
end if;
|
288 |
|
|
when BYTE3 => -- send byte 3 DATA2
|
289 |
|
|
reghnd_wr_enable_o <= '1';
|
290 |
|
|
if s_tick = "00" then -- only first time in this cycle acq the byte
|
291 |
|
|
s_reg_decoder <= BYTE3;
|
292 |
|
|
reghnd_output_rdy_o <= '1';
|
293 |
|
|
reghnd_pdata_o <= v_tx_stream (23 downto 16);
|
294 |
|
|
if reghnd_data_acq_gh16550_i = '1' then
|
295 |
|
|
s_tick <= "01";
|
296 |
|
|
else
|
297 |
|
|
s_tick <= "00";
|
298 |
|
|
end if;
|
299 |
|
|
elsif s_tick = "01" then
|
300 |
|
|
s_tick <= "11";
|
301 |
|
|
s_reg_decoder <= BYTE3;
|
302 |
|
|
reghnd_output_rdy_o <= '1';
|
303 |
|
|
reghnd_pdata_o <= v_tx_stream (23 downto 16);
|
304 |
|
|
elsif s_tick = "11" then
|
305 |
|
|
s_tick <= "10";
|
306 |
|
|
s_reg_decoder <= BYTE3;
|
307 |
|
|
reghnd_output_rdy_o <= '1';
|
308 |
|
|
reghnd_pdata_o <= v_tx_stream (23 downto 16);
|
309 |
|
|
elsif reghnd_txrdy_n_gh16550_i = '0' and reghnd_wr_enable_i = '1' then -- if uart is lbus and gh16550 is ready then tx BYTE0
|
310 |
|
|
s_reg_decoder <= BYTE4;
|
311 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
312 |
|
|
reghnd_pdata_o <= v_tx_stream (15 downto 8);
|
313 |
|
|
reghnd_output_rdy_o <= '0';
|
314 |
|
|
s_tick <= "00";
|
315 |
|
|
else
|
316 |
|
|
s_reg_decoder <= BYTE3;
|
317 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
318 |
|
|
reghnd_pdata_o <= v_tx_stream (15 downto 8);
|
319 |
|
|
reghnd_output_rdy_o <= '0';
|
320 |
|
|
s_tick <= "10";
|
321 |
|
|
end if;
|
322 |
|
|
when BYTE4 => -- send byte 4 DATA3
|
323 |
|
|
reghnd_wr_enable_o <= '1';
|
324 |
|
|
if s_tick = "00" then -- only first time in this cycle acq the byte
|
325 |
|
|
s_reg_decoder <= BYTE4;
|
326 |
|
|
reghnd_output_rdy_o <= '1';
|
327 |
|
|
reghnd_pdata_o <= v_tx_stream (15 downto 8);
|
328 |
|
|
if reghnd_data_acq_gh16550_i = '1' then
|
329 |
|
|
s_tick <= "01";
|
330 |
|
|
else
|
331 |
|
|
s_tick <= "00";
|
332 |
|
|
end if;
|
333 |
|
|
elsif s_tick = "01" then
|
334 |
|
|
s_tick <= "11";
|
335 |
|
|
s_reg_decoder <= BYTE4;
|
336 |
|
|
reghnd_output_rdy_o <= '1';
|
337 |
|
|
reghnd_pdata_o <= v_tx_stream (15 downto 8);
|
338 |
|
|
elsif s_tick = "11" then
|
339 |
|
|
s_tick <= "10";
|
340 |
|
|
s_reg_decoder <= BYTE4;
|
341 |
|
|
reghnd_output_rdy_o <= '1';
|
342 |
|
|
reghnd_pdata_o <= v_tx_stream (15 downto 8);
|
343 |
|
|
elsif reghnd_txrdy_n_gh16550_i = '0' and reghnd_wr_enable_i = '1' then -- if uart is lbus and gh16550 is ready then tx BYTE0
|
344 |
|
|
s_reg_decoder <= BYTE5;
|
345 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
346 |
|
|
reghnd_pdata_o <= v_tx_stream (7 downto 0);
|
347 |
|
|
reghnd_output_rdy_o <= '0';
|
348 |
|
|
s_tick <= "00";
|
349 |
|
|
else
|
350 |
|
|
s_reg_decoder <= BYTE4;
|
351 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
352 |
|
|
reghnd_pdata_o <= v_tx_stream (7 downto 0);
|
353 |
|
|
reghnd_output_rdy_o <= '0';
|
354 |
|
|
s_tick <= "10";
|
355 |
|
|
end if;
|
356 |
|
|
when BYTE5 => -- send byte 5 DATA4
|
357 |
|
|
reghnd_wr_enable_o <= '1';
|
358 |
|
|
if s_tick = "00" then -- only first time in this cycle acq the byte
|
359 |
|
|
s_reg_decoder <= BYTE5;
|
360 |
|
|
reghnd_output_rdy_o <= '1';
|
361 |
|
|
reghnd_pdata_o <= v_tx_stream (7 downto 0);
|
362 |
|
|
if reghnd_data_acq_gh16550_i = '1' then
|
363 |
|
|
s_tick <= "01";
|
364 |
|
|
else
|
365 |
|
|
s_tick <= "00";
|
366 |
|
|
end if;
|
367 |
|
|
elsif s_tick = "01" then
|
368 |
|
|
s_tick <= "11";
|
369 |
|
|
s_reg_decoder <= BYTE5;
|
370 |
|
|
reghnd_output_rdy_o <= '1';
|
371 |
|
|
reghnd_pdata_o <= v_tx_stream (7 downto 0);
|
372 |
|
|
elsif s_tick = "11" then
|
373 |
|
|
s_tick <= "10";
|
374 |
|
|
s_reg_decoder <= BYTE5;
|
375 |
|
|
reghnd_output_rdy_o <= '0';
|
376 |
|
|
reghnd_pdata_o <= v_tx_stream (7 downto 0);
|
377 |
|
|
elsif reghnd_txrdy_n_gh16550_i = '0' and reghnd_wr_enable_i = '1' and reghnd_stb_data_ram_rdy_i = '1' then -- if uart is lbus and gh16550 is ready then tx BYTE0
|
378 |
|
|
s_reg_decoder <= READ_RAM;
|
379 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
380 |
|
|
reghnd_pdata_o <= (others => '0');
|
381 |
|
|
reghnd_output_rdy_o <= '0';
|
382 |
|
|
s_tick <= "00";
|
383 |
|
|
elsif reghnd_txrdy_n_gh16550_i = '0' then -- if uart is lbus and gh16550 is ready then tx BYTE0
|
384 |
|
|
s_reg_decoder <= IDLE;
|
385 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
386 |
|
|
reghnd_pdata_o <= (others => '0');
|
387 |
|
|
reghnd_output_rdy_o <= '0';
|
388 |
|
|
s_tick <= "00";
|
389 |
|
|
else
|
390 |
|
|
s_reg_decoder <= BYTE5;
|
391 |
|
|
reghnd_stb_acq_ram_o <= '0';
|
392 |
|
|
reghnd_pdata_o <= (others => '0');
|
393 |
|
|
s_tick <= "10";
|
394 |
|
|
end if;
|
395 |
|
|
when others =>
|
396 |
|
|
s_reg_decoder <= IDLE;
|
397 |
|
|
end case;
|
398 |
|
|
end if;
|
399 |
|
|
end process p_tx_handler;
|
400 |
|
|
|
401 |
|
|
|
402 |
|
|
end tx_handler;
|
403 |
|
|
|
404 |
|
|
--=============================================================================
|
405 |
|
|
-- architecture end
|
406 |
|
|
--=============================================================================
|