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-- --
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-- --
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-- --
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-- --
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-------------------------------------------------------------------------------
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--
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-- unit name: UART_16550_wrapper
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--
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-- author: Andrea Borga (andrea.borga@nikhef.it)
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-- Mauro Predonzani (mauro.predonzani@elettra.trieste.it)
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--
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-- date: $26/01/2009 $: created
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--
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-- version: $Rev 0 $:
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--
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-- description: <file content, behaviour, purpose, special usage notes...>
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-- <further description>
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--
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-- dependencies: gh_uart_16550
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-- register_rx_handler
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-- register_tx_handler
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-- uart_lbus_slave
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--
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--
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--
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-- references: <reference one>
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-- <reference two> ...
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--
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-- modified by: $Author:: $:
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--
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-------------------------------------------------------------------------------
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-- changes: 2010-05-06 Mauro Predonzani
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-- set ECHO MODE on/off
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-- 2010-06-09 Mauro Predonzani
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-- enable/disable TX address byte
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-- 2011-08-18 Andrea Borga
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-- added soft FIFO reset release after init
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-- 2011-08-18 Andrea Borga
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-- renamed entity to a more generic UART_16550_wrapper
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-- (instead of Lantronix_wrapper)
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-- <extended description>
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-------------------------------------------------------------------------------
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-- TODO:
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--
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--
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--
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-------------------------------------------------------------------------------
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--=============================================================================
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-- Libraries
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--=============================================================================
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--=============================================================================
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-- Entity declaration for ada_uart_16550_wrapper
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--=============================================================================
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entity uart_16550_wrapper is
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port(
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-- general purpose
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sys_clk_i : in std_logic; -- system clock
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sys_rst_i : in std_logic; -- system reset
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-- TX/RX process command line
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echo_en_i : in std_logic; -- Echo enable (byte by byte) enable/disable = 1/0
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tx_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
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-- serial I/O side
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lantronix_output_i : in std_logic; -- Lantronix Serial data OUTPUT signal
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lantronix_input_o : out std_logic; -- Lantronix Serial data INPUT signal
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cp_b : inout std_logic_vector(2 downto 0); -- general purpose IO pins
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-- parallel I/O side
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s_br_clk_uart_o : out std_logic; -- br_clk clock probe signal
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-- RX part/control
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v_rx_add_o : out std_logic_vector(15 downto 0); -- 16 bits full addr ram input
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v_rx_data_o : out std_logic_vector(31 downto 0); -- 32 bits full data ram input
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s_rx_rdy_o : out std_logic; -- add/data ready to be write into RAM
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s_rx_stb_read_data_i : in std_logic; -- strobe signal from RAM ...
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-- TX part/control
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s_tx_proc_rqst_i : in std_logic; -- stream TX process request 1/0 tx enable/disable
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v_tx_add_ram_i : in std_logic_vector(15 downto 0); -- 16 bits full addr ram output
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v_tx_data_ram_i : in std_logic_vector(31 downto 0); -- 32 bits full data ram output
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s_tx_ram_data_rdy_i : in std_logic; -- ram output data ready and stable
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s_tx_stb_ram_data_acq_o : out std_logic -- strobe ram data/address output acquired 1/0 acquired/not acquired
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);
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end entity;
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--=============================================================================
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-- architecture declaration
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--=============================================================================
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architecture a of uart_16550_wrapper is
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-- Components declaration
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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component gh_uart_16550 is
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port(
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clk : in std_logic; -- UART clock (toward logic)
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BR_clk : in std_logic; -- Baudrate generator clock TX and RX
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rst : in std_logic; -- Reset
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rst_buffer : in std_logic; -- Reset for FIFO and TX and RX
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CS : in std_logic; -- Chip select -> 1 Cycle long CS strobe = 1 data transaction (w/r)
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WR : in std_logic; -- WRITE when HIGH with CS high | READ when LOW with CS high
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ADD : in std_logic_vector(2 downto 0); -- ADDRESS BUS
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D : in std_logic_vector(7 downto 0); -- Input DATA BUS and CONTROL BUS
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sRX : in std_logic; -- Lantronix's OUTPUT
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CTSn : in std_logic := '1';
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DSRn : in std_logic := '1';
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RIn : in std_logic := '1';
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DCDn : in std_logic := '1';
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sTX : out std_logic; -- Lantronix's INPUT
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DTRn : out std_logic;
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RTSn : out std_logic;
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OUT1n : out std_logic;
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OUT2n : out std_logic;
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TXRDYn : out std_logic; -- Tx FIFO not Full
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RXRDYn : out std_logic; -- Rx FIFO Data Ready
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IRQ : out std_logic;
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B_CLK : out std_logic; -- 16x Baudrate clock output
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RD : out std_logic_vector(7 downto 0) -- Output DATA BUS
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);
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end component;
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component uart_lbus is
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generic (
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c_bus_width : natural := 8
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);
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port (
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lbus_clk : in std_logic; -- local bus clock
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lbus_rst : in std_logic; -- local bus reset
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lbus_rst_buffer : out std_logic; -- Reset for FIFO and TX and RX
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lbus_txrdy_n : in std_logic; -- Tx data ready
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lbus_rxrdy_n : in std_logic; -- Rx data ready
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lbus_cs : out std_logic; -- Chip Select
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lbus_wr : out std_logic; -- Write/Read (1/0)
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lbus_init : out std_logic; -- Initialization process flag
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lbus_add : out std_logic_vector(2 downto 0); -- local bus address
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lbus_data : out std_logic_vector(c_bus_width-1 downto 0); -- local bus data
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s_tx_proc_rqst_i : in std_logic; -- tx process request from RAM
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v_lbus_state : out std_logic_vector(2 downto 0); -- flag indicator of lbus_state
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s_cs_rd_c : out std_logic; -- CS signal from caused by read cycle
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s_wr_rd_c : out std_logic; -- WR signal from caused by read cycle
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s_new_byte_rdy : in std_logic; -- new byte(8bit)ready and stable to be transmitted
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s_data_tx : in std_logic; -- 6 bytes will be trasmitted
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reghnd_rd_rdy : in std_logic; -- 6 byte RX ready but not yet written in RAM (1/0=>data ready/not ready)
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echo_en_i : in std_logic -- echo enable command enable/disable = 1/0
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);
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end component;
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component register_rx_handler
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port(
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reghnd_clk : in std_logic; -- system clock
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reghnd_rst : in std_logic; -- system reset
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reghnd_data_in : in std_logic_vector(7 downto 0); -- 8 bits fragments
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reghnd_data_cs_rd : in std_logic; -- cs strobe of gh16550 during a read process
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reghnd_data_wr_rd : in std_logic; -- wr state of gh16550 during a read process
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reghnd_rd_rdy : out std_logic; -- Read data ready
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reghnd_full_add : out std_logic_vector(15 downto 0); -- 16 bits RAM address
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reghnd_full_data : out std_logic_vector(31 downto 0); -- 32 bits RAM data
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reghnd_full_cs : in std_logic -- strobe data/address acquired (1 acquired - 0 not acquired)
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);
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end component;
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component register_tx_handler
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port(
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reghnd_clk : in std_logic; -- system clock
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reghnd_rst : in std_logic; -- system reset
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reghnd_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
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reghnd_full_data_ram_i : in std_logic_vector(31 downto 0); -- 32 bits full data
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reghnd_full_add_ram_i : in std_logic_vector(15 downto 0); -- 16 bits full addr
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reghnd_stb_data_ram_rdy_i : in std_logic; -- strobe ram data ready
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reghnd_data_acq_gh16550_i : in std_logic; -- data acquired from gh16550
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reghnd_wr_enable_i : in std_logic; -- enable the tx process
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reghnd_txrdy_n_gh16550_i : in std_logic; -- gh16550 ready to trasmit
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reghnd_wr_enable_o : out std_logic; -- enable the tx process
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reghnd_output_rdy_o : out std_logic; -- Read data ready
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reghnd_pdata_o : out std_logic_vector(7 downto 0); -- 8 bits parallel
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reghnd_stb_acq_ram_o : out std_logic -- strobe data/address acquired (1 acquired - 0 not acquired)
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);
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end component;
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--
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-- Internal signal declaration
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--
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signal s_rst : std_logic; -- global reset
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signal s_rst_buffer : std_logic; -- soft reset for FIFO and TX and RX uart FSM
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signal s_clk : std_logic; -- uart to parallel interface clock
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signal s_clk_n : std_logic; -- uart to parallel interface clock
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signal s_br_clk : std_logic; -- uart serializer clock
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signal s_open : std_logic_vector(32 downto 0) := (others => '0'); -- unused pins
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signal s_cs : std_logic; -- chip select (data strobe)
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signal s_wr : std_logic; -- read/write on data bus
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signal lbus_init : std_logic; -- register initialization
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signal lbus_add : std_logic_vector(2 downto 0); -- local bus arbiter address bus
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signal lbus_data : std_logic_vector(7 downto 0); -- local bus arbiter data bus
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signal uart_txrdy_n : std_logic; -- tx FIFO Data Ready
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signal uart_rxrdy_n : std_logic; -- rx FIFO Data Ready
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signal uart_add_bus : std_logic_vector(2 downto 0); -- address bus
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signal uart_data_bus : std_logic_vector(7 downto 0); -- data bus
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signal uart_rd : std_logic_vector(7 downto 0); -- UART Rx output data bus
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signal v_write_bus_latch : std_logic_vector(7 downto 0); -- WRITE data bus latched
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signal v_read_bus_latch : std_logic_vector(7 downto 0); -- READ data bus latched
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--------------------------------------------------------------------------------------------------
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-- v_lcr structure:
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--
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-- 0-1 : number of bits
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-- 00 -> 5 | 01 -> 6 | 10 -> 7 | 11 -> 8
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-- 2 : number of stop bits
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-- 0 -> 1bit | 1 -> 2bits
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-- 3 : parity bit
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-- 0 -> no party | 1 -> parity
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-- 4 : parity type
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-- 0 -> odd | 1 -> even
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-- 5 : sticky parity (NOT IMPLEMENTED)
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-- 6 : set break
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-- 0 -> normal operation
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-- 1 -> serial output is forced to logic 0
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-- (Spacing State, which will cause a Break interrupt in the receiver)
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-- 7 : Divisor Latch (baud rate generator) Access bit
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-- 0 -> set Baud rate divisor
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-- 1 -> access FIFO registers
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--
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--------------------------------------------------------------------------------------------------
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signal v_lcr : std_logic_vector(7 downto 0); -- Line Control Register
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--------------------------------------------------------------------------------------------------
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-- v_fcr structure:
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--
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-- 0 : FIFO enable
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-- X -> FIFOs are always enabled
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-- 1 : RECEIVER FIFO reset active HIGH
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-- 2 : TRANSMITTER FIFO reset active HIGH
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-- 3 : DMA mode
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-- 0 -> Mode 0 (Supports single transfer DMA)
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-- 1 -> Mode 1 (Supports multiple transfers)
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-- 4-5 : Reserved bits
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-- 6-7 : Receiver FIFO trigger level
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-- 00 -> 1 | 01 -> 4 | 10 -> 8 | 11 -> 14 Bytes
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--
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--------------------------------------------------------------------------------------------------
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signal v_fcr : std_logic_vector(7 downto 0); -- FIFO Control Register
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--------------------------------------------------------------------------------------------------
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-- v_lsr structure:
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--
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-- 0 : Data Ready
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-- 0 -> Receive FIFO is empty
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-- 1 -> at lest one character is in the receive FIFO
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-- 1 : Overrun Error
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-- 0 -> no error
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-- 1 -> Receive FIFO was full, additional character received but was lost
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-- 2 : Parity Error
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-- 0 -> no error
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-- 1 -> top character in FIFO received with parity error
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-- -> Receiver Line Status Interrupt
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-- 3 : Framing Error
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-- 0 -> no error
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-- 1 -> top character in FIFO received without a valid stop bit
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-- -> Receiver Line Status Interrupt
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-- 4 : Break Interrupt
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-- 0 -> No Interrupt
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-- 1 -> break condition (uart_srx -> '0' for a character period)
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-- -> Receiver Line Status Interrupt
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-- 5 : Transmitter Holding Register
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-- 0 -> Transmitter FIFO not Empty
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-- 1 -> Transmitter FIFO Empty if enabled
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-- -> Transmitter Holding Empty Interrupt
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-- 6 : Transmitter Empty
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-- 0 -> not 1
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-- 1 -> Transmitter FIFO and Transmitter Shift Register Empty.
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-- 7 : Error in receive FIFO
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-- 0 -> not 1
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-- 1 -> at least one error (parity, framing or break) in receive FIFO.
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-- -> cleared upon reading the register
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--
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--------------------------------------------------------------------------------------------------
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signal v_lsr : std_logic_vector(7 downto 0); -- Line Status Register
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--------------------------------------------------------------------------------------------------
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-- v_iir structure:
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--
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-- 0 : Interrupt pending
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-- 0 -> Interrupt pending
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-- 1 -> No Interrupt pending
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-- 3-1 :
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-- 010 -> Receiver Data Available ( Rx FIFO trigger level reached)
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--
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--------------------------------------------------------------------------------------------------
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signal v_iir : std_logic_vector(7 downto 0); -- Interrupt Identification Register
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--------------------------------------------------------------------------------------------------
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-- Baud Rate Generator:
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-- Baud rate division ratio = (s_br_clk /(baudrate x 16))
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--
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-- Baud rate division ratio (16 bits) = c_divisor_msb (8 bits) + c_divisor_lsb (8 bits)
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--
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-- Set useing: LCR bit 7 -> 1
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--------------------------------------------------------------------------------------------------
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-- signal c_divisor_lsb : std_logic_vector(7 downto 0); -- Divisor Latch LSB (Baud Rate Generator)
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-- signal c_divisor_msb : std_logic_vector(7 downto 0); -- Divisor Latch MSB (Baud Rate Generator)
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324 |
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325 |
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signal v_unused_write : std_logic_vector(7 downto 0); -- Unused registers
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326 |
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signal v_unused_read : std_logic_vector(7 downto 0); -- Unused registers
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327 |
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328 |
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signal v_lbus_state : std_logic_vector(2 downto 0);
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329 |
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signal s_reading_proc : std_logic;
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330 |
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signal s_cs_rd_c : std_logic;
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331 |
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signal s_wr_rd_c : std_logic;
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332 |
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signal s_writing_proc : std_logic;
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333 |
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signal v_data8_ram : std_logic_vector (7 downto 0);
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334 |
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signal s_data8_ram_rdy : std_logic;
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335 |
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signal s_wr_enable_o : std_logic;
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336 |
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signal s_not_ready : std_logic;
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337 |
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338 |
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--=============================================================================
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339 |
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-- architecture begin
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340 |
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--=============================================================================
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341 |
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342 |
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begin
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343 |
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344 |
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s_clk <= sys_clk_i; -- 14,xxx MHz main clock single ended buffer and division by one
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345 |
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-- and 1 Mbit/s with Lantronix
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346 |
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s_clk_n <= not s_clk;
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347 |
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s_rst <= sys_rst_i;
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348 |
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s_br_clk <= s_clk;
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349 |
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350 |
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s_reading_proc <= v_lbus_state(1);
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351 |
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s_writing_proc <= v_lbus_state(2);
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352 |
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353 |
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s_rx_rdy_o <= s_not_ready;
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354 |
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355 |
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--**************************************************************************
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356 |
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-- UART read/write bus access
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357 |
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--
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358 |
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--**************************************************************************
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359 |
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-- read:
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360 |
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-- write:
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361 |
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-- r/w:
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362 |
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363 |
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p_uart_RW_bus : process(s_rst, s_clk)
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364 |
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begin
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365 |
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if s_rst = '1' then
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366 |
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uart_data_bus <= (others => '0');
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367 |
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uart_add_bus <= (others => '0');
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368 |
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v_unused_write <= (others => '0');
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369 |
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v_unused_read <= (others => '0');
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370 |
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v_fcr <= (others => '0');
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371 |
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v_lcr <= (others => '0');
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372 |
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v_lsr <= (others => '0');
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373 |
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elsif Rising_edge(s_clk) then
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374 |
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uart_add_bus <= lbus_add;
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375 |
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case v_lbus_state is
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376 |
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when "001" => -- init
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377 |
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case uart_add_bus (2 downto 0) is
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378 |
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when O"0" => uart_data_bus <= lbus_data; -- init Divisor latch lsb
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379 |
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when O"1" => uart_data_bus <= lbus_data; -- init Divisor latch msb
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380 |
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when O"2" => uart_data_bus <= lbus_data;
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381 |
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v_fcr <= lbus_data; -- FIFO Control Register
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382 |
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when O"3" => uart_data_bus <= lbus_data;
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383 |
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v_lcr <= lbus_data; -- Line Control Register
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384 |
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when others => null;
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385 |
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end case;
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386 |
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when "100" => -- write
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387 |
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case uart_add_bus (2 downto 0) is
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388 |
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when O"0" => uart_data_bus <= v_write_bus_latch; -- write TRANSMITTER FIFO
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389 |
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when O"1" => uart_data_bus <= lbus_data; -- Interrupt Enable Register
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390 |
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when O"2" => uart_data_bus <= lbus_data;
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391 |
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v_fcr <= lbus_data; -- FIFO Control Register
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392 |
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when O"3" => uart_data_bus <= lbus_data;
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393 |
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v_lcr <= lbus_data; -- Line Control Register
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394 |
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when O"4" => uart_data_bus <= v_unused_write; -- Modem Control Register
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395 |
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when O"7" => uart_data_bus <= v_unused_write; -- Scretch Register
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396 |
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when others => null;
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397 |
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end case;
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398 |
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when "010" => -- read
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399 |
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case uart_add_bus (2 downto 0) is
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400 |
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when O"0" => uart_data_bus <= v_read_bus_latch; --uart_rd; -- read RECEIVER FIFO
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401 |
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when O"1" => v_unused_read <= uart_data_bus; -- Interrupt Enable Register
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402 |
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when O"2" => v_iir <= uart_data_bus; -- Interrupt Identification Register
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403 |
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when O"3" => v_unused_read <= uart_data_bus; -- Line Control Register
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404 |
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when O"4" => v_unused_read <= uart_data_bus; -- Modem Control Register
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405 |
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when O"5" => v_lsr <= uart_data_bus; -- Line Status Register
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406 |
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when O"6" => v_unused_read <= uart_data_bus; -- Modem Status Register
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407 |
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when O"7" => v_unused_read <= uart_data_bus; -- Scratch Register
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408 |
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when others => null;
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409 |
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end case;
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410 |
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when others => -- idle
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411 |
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case uart_add_bus (2 downto 0) is
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412 |
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when O"0" => uart_data_bus <= (others => '0'); --uart_rd; -- read RECEIVER FIFO
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413 |
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when O"1" => v_unused_read <= uart_data_bus; -- Interrupt Enable Register
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414 |
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when O"2" => v_iir <= uart_data_bus; -- Interrupt Identification Register
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415 |
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when O"3" => v_unused_read <= uart_data_bus; -- Line Control Register
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416 |
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when O"4" => v_unused_read <= uart_data_bus; -- Modem Control Register
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417 |
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when O"5" => v_lsr <= uart_data_bus; -- Line Status Register
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418 |
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when O"6" => v_unused_read <= uart_data_bus; -- Modem Status Register
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419 |
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when O"7" => v_unused_read <= uart_data_bus; -- Scratch Register
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420 |
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when others => null;
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421 |
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end case;
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422 |
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end case;
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423 |
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end if;
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424 |
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end process p_uart_RW_bus;
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425 |
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426 |
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--**************************************************************************
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427 |
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-- UART register latch update
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428 |
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--**************************************************************************
|
429 |
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-- read:
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430 |
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-- write:
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431 |
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-- r/w:
|
432 |
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|
433 |
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p_uart_read_latch : process(s_rst, s_reading_proc)
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434 |
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begin
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435 |
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if s_rst = '1' then
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436 |
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v_read_bus_latch <= (others => '0');
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437 |
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elsif rising_edge (s_reading_proc) then
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438 |
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if s_cs = '0' and s_wr = '0' then
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439 |
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v_read_bus_latch <= uart_rd;
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440 |
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end if;
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441 |
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end if;
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442 |
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end process p_uart_read_latch;
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443 |
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444 |
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p_uart_write_latch : process(s_rst, s_data8_ram_rdy)
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445 |
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begin
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446 |
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if s_rst = '1' then
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447 |
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v_write_bus_latch <= (others => '0');
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448 |
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elsif rising_edge (s_data8_ram_rdy) then
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449 |
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if s_cs = '0' and s_wr = '1'then
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450 |
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v_write_bus_latch <= v_data8_ram;
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451 |
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end if;
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452 |
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end if;
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453 |
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end process p_uart_write_latch;
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454 |
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455 |
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-- p_uart_read_latch : process(s_rst, s_clk_n)
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456 |
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-- begin
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457 |
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-- if s_rst = '1' then
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458 |
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-- v_read_bus_latch <= (others => '0');
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459 |
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-- elsif rising_edge (s_clk_n) then
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460 |
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-- if s_reading_proc = '1' and s_cs = '0' and s_wr = '0' then
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461 |
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-- v_read_bus_latch <= uart_rd;
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462 |
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-- else
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463 |
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-- v_read_bus_latch <= uart_rd;
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464 |
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-- end if;
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465 |
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-- end if;
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466 |
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-- end process p_uart_read_latch;
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467 |
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468 |
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-- p_uart_write_latch : process(s_rst, s_clk_n)
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469 |
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-- begin
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470 |
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-- if s_rst = '1' then
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471 |
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-- v_write_bus_latch <= (others => '0');
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472 |
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-- elsif rising_edge (s_clk_n) then
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473 |
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-- if s_data8_ram_rdy = '1' and s_cs = '0' and s_wr = '1' then
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474 |
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-- v_write_bus_latch <= v_data8_ram;
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475 |
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-- else
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476 |
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-- v_write_bus_latch <= (others => '0');
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477 |
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-- end if;
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478 |
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-- end if;
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479 |
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-- end process p_uart_write_latch;
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480 |
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|
481 |
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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482 |
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-- Components mapping
|
483 |
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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484 |
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|
485 |
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cmp_uart : gh_uart_16550
|
486 |
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port map (
|
487 |
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clk => s_clk, -- uart clock
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488 |
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BR_clk => s_br_clk, -- Baudrate generator clock TX and RX
|
489 |
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rst => s_rst, -- Reset
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490 |
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rst_buffer => s_rst_buffer, -- soft fifo release reset after init
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491 |
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CS => s_cs, -- Chip select -> 1 Cycle long CS strobe = 1 data transaction (w/r)
|
492 |
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WR => s_wr, -- WRITE when HIGH with CS high | READ when LOW with CS high
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493 |
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ADD => uart_add_bus, -- ADDRESS BUS
|
494 |
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D => uart_data_bus, -- Input DATA BUS and CONTROL BUS
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495 |
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sRX => lantronix_output_i, -- Lantronix's OUTPUT
|
496 |
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CTSn => '1', -- not used
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497 |
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DSRn => '1', -- not used
|
498 |
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RIn => '1', -- not used
|
499 |
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DCDn => '1', -- not used
|
500 |
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|
501 |
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sTX => lantronix_input_o, -- Lantronix's INPUT
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502 |
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DTRn => open, -- not used
|
503 |
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RTSn => open, -- not used
|
504 |
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OUT1n => open, -- not used
|
505 |
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OUT2n => open, -- not used
|
506 |
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TXRDYn => uart_txrdy_n, -- Tx FIFO not Fully
|
507 |
|
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RXRDYn => uart_rxrdy_n, -- Rx FIFO Data Ready
|
508 |
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|
509 |
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IRQ => open, -- not used
|
510 |
|
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B_CLK => s_br_clk_uart_o, -- br_clk clock probe signal
|
511 |
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RD => uart_rd -- read data
|
512 |
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);
|
513 |
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|
514 |
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cmp_uart_lbus : uart_lbus
|
515 |
|
|
port map (
|
516 |
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lbus_clk => s_clk, -- uart clock
|
517 |
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lbus_rst => s_rst, -- system reset
|
518 |
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lbus_rst_buffer => s_rst_buffer, -- soft UART FIFO reset
|
519 |
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lbus_txrdy_n => uart_txrdy_n, -- Tx data ready
|
520 |
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lbus_rxrdy_n => uart_rxrdy_n, -- Rx data ready
|
521 |
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lbus_cs => s_cs, -- Chip Select gh16550
|
522 |
|
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lbus_wr => s_wr, -- Write/Read (1/0) gh16550
|
523 |
|
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lbus_init => lbus_init, -- Initialization process flag
|
524 |
|
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lbus_add => lbus_add, -- local bus address
|
525 |
|
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lbus_data => lbus_data, -- local bus data
|
526 |
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s_tx_proc_rqst_i => s_tx_proc_rqst_i, -- tx process request from RAM
|
527 |
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v_lbus_state => v_lbus_state, -- flag indicator of lbus_state
|
528 |
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s_cs_rd_c => s_cs_rd_c, -- CS signal from caused by read cycle
|
529 |
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s_wr_rd_c => s_wr_rd_c, -- WR signal from caused by read cycle
|
530 |
|
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s_new_byte_rdy => s_data8_ram_rdy, -- new byte(8bit)ready and stable to be transmitted
|
531 |
|
|
s_data_tx => s_wr_enable_o, -- 6 bytes will be trasmitted
|
532 |
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reghnd_rd_rdy => s_not_ready, -- 6 byte ready but not yet written in RAM (1/0=>data ready/not ready)
|
533 |
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echo_en_i => echo_en_i -- echo enable command enable/disable = 1/0
|
534 |
|
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);
|
535 |
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|
536 |
|
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cmp_register_rx_handler: register_rx_handler
|
537 |
|
|
port map(
|
538 |
|
|
reghnd_clk => s_clk, -- system clock
|
539 |
|
|
reghnd_rst => s_rst, -- system reset
|
540 |
|
|
reghnd_data_in => v_read_bus_latch, -- 8 bits handler input from gh16550 RD through latch
|
541 |
|
|
reghnd_data_cs_rd => s_cs_rd_c, -- cs strobe of gh16550 during a read process
|
542 |
|
|
reghnd_data_wr_rd => s_wr_rd_c, -- wr state of gh16550 during a read process
|
543 |
|
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reghnd_rd_rdy => s_not_ready, -- data and address ready and stable at handler output
|
544 |
|
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reghnd_full_add => v_rx_add_o, -- 16 bits full addr ram input
|
545 |
|
|
reghnd_full_data => v_rx_data_o, -- 32 bits full data ram input
|
546 |
|
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reghnd_full_cs => s_rx_stb_read_data_i -- strobe data/address acquired (1 acquired - 0 not acquired)
|
547 |
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);
|
548 |
|
|
|
549 |
|
|
cmp_register_tx_handler: register_tx_handler
|
550 |
|
|
port map(
|
551 |
|
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reghnd_clk => s_clk, -- system clock
|
552 |
|
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reghnd_rst => s_rst, -- system reset
|
553 |
|
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reghnd_addr_wwo_i => tx_addr_wwo_i, -- control of TX process With or WithOut address W/WO=(1/0)
|
554 |
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reghnd_full_data_ram_i => v_tx_data_ram_i, -- 32 bits full data ram output
|
555 |
|
|
reghnd_full_add_ram_i => v_tx_add_ram_i, -- 16 bits full addr ram output
|
556 |
|
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reghnd_stb_data_ram_rdy_i => s_tx_ram_data_rdy_i, -- strobe ram output data ready and stable
|
557 |
|
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reghnd_data_acq_gh16550_i => s_cs, -- data acquired from gh16550
|
558 |
|
|
reghnd_wr_enable_i => s_writing_proc, -- enable the tx process
|
559 |
|
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reghnd_txrdy_n_gh16550_i => uart_txrdy_n, -- gh16550 ready to trasmit
|
560 |
|
|
reghnd_wr_enable_o => s_wr_enable_o, -- enable the tx process
|
561 |
|
|
reghnd_output_rdy_o => s_data8_ram_rdy, -- output data(8) ready
|
562 |
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|
reghnd_pdata_o => v_data8_ram, -- 8 bits parallel
|
563 |
|
|
reghnd_stb_acq_ram_o => s_tx_stb_ram_data_acq_o -- strobe data/address acquired (1 acquired - 0 not acquired)
|
564 |
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);
|
565 |
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|
566 |
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|
end a;
|
567 |
|
|
|
568 |
|
|
--=============================================================================
|
569 |
|
|
-- architecture end
|
570 |
|
|
--=============================================================================
|