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-------------------------------------------------------------------------------
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-- --
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-- --
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-- --
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-- --
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-------------------------------------------------------------------------------
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--
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-- unit name: uart_lbus (UART Control)
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--
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-- author: Andrea Borga (andrea.borga@nikhef.nl)
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aborga |
-- Mauro Predonzani (predmauro@libero.it)
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3 |
aborga |
--
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-- date: $26/01/2009 $: created
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--
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-- version: $Rev 0 $:
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--
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-- description: <file content, behaviour, purpose, special usage notes...>
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-- <further description>
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--
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aborga |
-- dependencies: uart_wrapper
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aborga |
-- gh_uart_16550
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-- register_rx_handler
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-- register_tx_handler
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--
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-- references: <reference one>
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-- <reference two> ...
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--
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-- modified by: $Author:: $:
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-- 18/08/2011 Andrea Borga
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-- modified UART_WRITE to improve stability
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--
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-------------------------------------------------------------------------------
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-- last changes: <date> <initials> <log>
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-- <extended description>
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-------------------------------------------------------------------------------
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-- TODO:
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-- check the address range (range violation prevention)
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--
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--
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-------------------------------------------------------------------------------
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--=============================================================================
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-- Libraries
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--=============================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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--=============================================================================
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-- Entity declaration for ada_uart_lbus
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--=============================================================================
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entity uart_lbus is
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generic (
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c_bus_width : natural := 8
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);
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port (
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lbus_clk : in std_logic; -- local bus clock
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lbus_rst : in std_logic; -- local bus reset
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lbus_rst_buffer : out std_logic; -- soft reset for UART fifos
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lbus_txrdy_n : in std_logic; -- Tx data ready
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lbus_rxrdy_n : in std_logic; -- Rx data ready
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lbus_cs : out std_logic; -- Chip Select
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lbus_wr : out std_logic; -- Write/Read (1/0)
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lbus_init : out std_logic; -- Initialization process flag
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lbus_add : out std_logic_vector(2 downto 0); -- local bus address
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lbus_data : out std_logic_vector(c_bus_width-1 downto 0); -- local bus data
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s_tx_proc_rqst_i : in std_logic; -- tx process request from RAM
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v_lbus_state : out std_logic_vector(2 downto 0); -- flag indicator of lbus_state
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s_cs_rd_c : out std_logic; -- CS signal from caused by read cycle
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s_wr_rd_c : out std_logic; -- WR signal from caused by read cycle
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s_new_byte_rdy : in std_logic; -- new byte(8bit) is ready and stable to be transmitted
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s_data_tx : in std_logic; -- trasmitting byte of RAM address/data
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reghnd_rd_rdy : in std_logic; -- 6 byte ready RX but not yet written in RAM (1/0=>data ready/not ready)
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echo_en_i : in std_logic -- echo enable command enable/disable = 1/0
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);
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end uart_lbus;
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--=============================================================================
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-- architecture declaration
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--=============================================================================
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architecture slave of uart_lbus is
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-- Components declaration
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-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-- component gh_edge_det is
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-- port(
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-- clk : in std_logic;
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-- rst : in std_logic;
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-- d : in std_logic;
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-- re : out std_logic; -- rising edge (need sync source at d)
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-- fe : out std_logic; -- falling edge (need sync source at d)
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-- sre : out std_logic; -- sync'd rising edge
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-- sfe : out std_logic -- sync'd falling edge
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-- );
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-- end component;
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--
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-- Internal signal declaration
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--
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signal v_data_gen : std_logic_vector(7 downto 0); -- test data generator
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signal s_data_toggle : std_logic; -- toggles between two data patterns AA and 55
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signal v_data_num : std_logic_vector(19 downto 0); -- number of data to send
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signal s_wr_rd : std_logic; -- wr for READ state process
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signal v_add_rd : std_logic_vector(2 downto 0);
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signal s_tx_term : std_logic; -- transmission teminating strobe
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signal s_tx_send_data : std_logic; -- data to send strobe
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signal s_cs_wr : std_logic; -- cs for WRITE state process
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signal s_wr_wr : std_logic; -- wr for WRITE state process
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signal v_add_wr : std_logic_vector(2 downto 0);
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signal v_add : std_logic_vector(2 downto 0);
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signal v_data : std_logic_vector(c_bus_width-1 downto 0);
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signal s_init_done : std_logic; -- initialization done flag
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signal s_write_msb : std_logic;
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signal s_tick_delay : std_logic; -- delays termination by 1 cycle (needed for lbus init)
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signal v_tick_delay_1 : std_logic_vector(1 downto 0); -- delays termination by 1 cycle (needed for RW_lbus)
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signal s_cs_init : std_logic; -- cs for INIT state process
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signal s_wr_init : std_logic; -- wr for INIT state process
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signal v_add_init : std_logic_vector(2 downto 0);
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signal v_data_init : std_logic_vector(c_bus_width-1 downto 0);
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signal v_fcr_init : std_logic_vector(7 downto 0); -- local FIFO Control Register O"2"
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signal v_lcr_init : std_logic_vector(7 downto 0); -- local Line Control Register O"3"
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signal v_lsr_init : std_logic_vector(7 downto 0); -- local Line Status Register O"5"
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signal s_cs_rd : std_logic;
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--
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-- State Machine states
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--
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type t_uart_state is (IDLE, INIT, UART_READ, UART_WRITE);
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signal s_slave_state : t_uart_state;
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type t_uart_init is (IDLE, WRITE_FCR, WRITE_LCR, WRITE_DIVLTC, ENB_FIFO, ENB_UART);
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signal s_slave_init : t_uart_init;
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--=============================================================================
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-- architecture begin
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--=============================================================================
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signal lbus_clk_n : std_logic;
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begin
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--
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-- Internal signals
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--
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lbus_clk_n <= not lbus_clk;
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s_cs_rd_c <= s_cs_rd;
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s_wr_rd_c <= s_wr_rd;
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lbus_add <= v_add_init or v_add_wr or v_add_rd;
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lbus_data <= v_data_init; -- or v_data_wr;
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lbus_init <= not s_init_done; -- init signal
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lbus_cs <= s_cs_init or s_cs_wr or s_cs_rd; -- CS uart signal
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lbus_wr <= s_wr_init or s_wr_wr or s_wr_rd; -- R/W control UART signal
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--**************************************************************************
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-- UART local bus slave
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-- (state transitions)
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--**************************************************************************
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-- read: lbus_clk
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-- write:
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-- r/w: s_slave_state
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p_uart_state: process (lbus_clk_n)
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begin
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if Rising_edge(lbus_clk_n) then
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if lbus_rst = '1' then -- Sync RESET
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s_slave_state <= IDLE;
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s_cs_wr <= '0';
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s_wr_wr <= '0';
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s_cs_rd <= '0';
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s_wr_rd <= '0';
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v_add_wr <= (others => '0');
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v_add_rd <= (others => '0');
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v_tick_delay_1 <= "00";
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v_lbus_state <= "000";
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lbus_rst_buffer <= '1'; -- rest UART FIFO
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else
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case s_slave_state is
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when IDLE => -- uart IDLE
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s_cs_rd <= '0';
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s_wr_rd <= '0';
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s_cs_wr <= '0';
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s_wr_wr <= '0';
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v_tick_delay_1 <= "00";
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if s_init_done = '0' then
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s_slave_state <= INIT;
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v_lbus_state <= "001";
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else
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lbus_rst_buffer <= '0'; -- release UART FIFO after init
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if s_tx_proc_rqst_i = '1' and lbus_txrdy_n = '0' then -- and reghnd_rd_rdy = '0' then
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v_lbus_state <= "100";
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s_slave_state <= UART_WRITE;
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elsif s_tx_proc_rqst_i = '0' and lbus_rxrdy_n = '0' and lbus_txrdy_n = '0' and reghnd_rd_rdy = '0' then
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s_slave_state <= UART_READ;
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v_lbus_state <= "010";
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else
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s_slave_state <= IDLE;
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v_lbus_state <= "000";
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end if;
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end if;
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when INIT => -- uart INIT
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v_lbus_state <= "001";
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if s_init_done = '0' then
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s_slave_state <= INIT;
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else
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s_slave_state <= IDLE;
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end if;
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when UART_READ => -- uart READ
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v_lbus_state <= "010";
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s_cs_wr <= '0';
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s_wr_wr <= '0';
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if lbus_rxrdy_n = '0' then
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if v_tick_delay_1 = "00" then
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if echo_en_i = '1' then -- ECHO is enable
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v_tick_delay_1 <= "01";
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elsif echo_en_i = '0' then -- ECHO is disable
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v_tick_delay_1 <= "11";
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end if;
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s_cs_rd <= '1';
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s_wr_rd <= '0';
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s_slave_state <= UART_READ;
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elsif v_tick_delay_1 = "01" then -- will be executed in a READ cycle only if ECHO is enable
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v_tick_delay_1 <= "10";
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v_add_rd <= O"0";
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s_cs_rd <= '0';
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s_wr_rd <= '1';
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s_slave_state <= UART_READ;
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elsif v_tick_delay_1 = "10" then -- will be executed in a READ cycle only if ECHO is enable
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v_tick_delay_1 <= "11";
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v_add_rd <= O"0";
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s_cs_rd <= '1';
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s_wr_rd <= '1';
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s_slave_state <= UART_READ;
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elsif v_tick_delay_1 = "11" then -- will be executed in every READ cycle
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v_tick_delay_1 <= "00";
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v_add_rd <= O"0";
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s_cs_rd <= '0';
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s_wr_rd <= '0';
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s_slave_state <= IDLE;
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end if;
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else
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s_cs_rd <= '0';
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s_wr_rd <= '0';
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s_slave_state <= IDLE;
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end if;
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when UART_WRITE => -- uart WRITE
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v_lbus_state <= "100";
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if v_tick_delay_1 = "00" then
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if s_new_byte_rdy = '1' then
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v_tick_delay_1 <= "01";
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s_cs_wr <= '0';
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s_wr_wr <= '1';
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else
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v_tick_delay_1 <= "00";
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if s_tx_proc_rqst_i = '0' and s_data_tx = '0' then
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s_slave_state <= IDLE;
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else
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s_slave_state <= UART_WRITE;
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end if;
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end if;
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elsif v_tick_delay_1 ="01" then
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v_tick_delay_1 <= "11";
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s_cs_wr <= '1';
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s_wr_wr <= '1';
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v_add_wr <= O"0";
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s_slave_state <= UART_WRITE;
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elsif v_tick_delay_1 ="11" then
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if s_new_byte_rdy = '1' then
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v_tick_delay_1 <= "11";
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s_cs_wr <= '0';
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s_wr_wr <= '1';
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v_add_wr <= O"0";
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s_slave_state <= UART_WRITE;
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else
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v_tick_delay_1 <= "00";
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s_cs_wr <= '0';
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s_wr_wr <= '1';
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v_add_wr <= O"0";
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s_slave_state <= UART_WRITE;
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end if;
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else
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s_cs_rd <= '0';
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s_wr_rd <= '0';
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s_slave_state <= IDLE;
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end if;
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when others => -- uart OTHERS
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s_slave_state <= IDLE;
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end case;
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end if;
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end if;
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end process p_uart_state;
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313 |
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--**************************************************************************
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314 |
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-- UART local bus slave
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315 |
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-- (initialization)
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316 |
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--**************************************************************************
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317 |
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-- read:
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318 |
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-- write:
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319 |
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-- r/w:
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320 |
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321 |
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p_init_lbus : process (lbus_clk, lbus_rst) -- uart initialization process
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322 |
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begin -- process
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323 |
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if lbus_rst = '1' then
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s_slave_init <= IDLE;
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v_add_init <= O"7";
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v_data_init <= (others => '0');
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v_lcr_init <= (others => '0');
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v_fcr_init <= (others => '0');
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s_tick_delay <= '0';
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s_write_msb <= '0';
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331 |
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s_cs_init <= '0';
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332 |
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s_wr_init <= '0';
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333 |
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s_init_done <= '0';
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334 |
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elsif Rising_edge(lbus_clk) then
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335 |
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case s_slave_init is
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336 |
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when IDLE => -- init IDLE
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337 |
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if s_init_done = '0' and s_write_msb = '0' then
|
338 |
|
|
s_cs_init <= '1';
|
339 |
|
|
s_wr_init <= '1';
|
340 |
|
|
s_slave_init <= WRITE_FCR;
|
341 |
|
|
else
|
342 |
|
|
s_slave_init <= IDLE;
|
343 |
|
|
end if;
|
344 |
|
|
when WRITE_FCR => -- init WRITE_FCR
|
345 |
|
|
v_add_init <= O"2";
|
346 |
|
|
v_fcr_init <= "00000000"; -- DMA mode 0 init FIFO Control Register
|
347 |
|
|
v_data_init <= "00000000"; -- DMA mode 0 write FIFO Control Register
|
348 |
|
|
-- v_fcr_init <= "00001000"; -- DMA mode 1 init FIFO Control Register
|
349 |
|
|
-- v_data_init <= "00001000"; -- DMA mode 1 write FIFO Control Register
|
350 |
|
|
s_slave_init <= WRITE_LCR;
|
351 |
|
|
when WRITE_LCR => -- init WRITE_LCR
|
352 |
|
|
v_add_init <= O"3";
|
353 |
|
|
v_lcr_init <= "10000011"; -- init FIFO Control Register
|
354 |
|
|
v_data_init <= "10000011"; -- write FIFO Control Register
|
355 |
|
|
s_slave_init <= WRITE_DIVLTC;
|
356 |
|
|
when WRITE_DIVLTC => -- init WRITE_DIVLTC
|
357 |
|
|
if s_write_msb = '0' then
|
358 |
|
|
v_add_init <= O"0"; -- init Divisor Latch lsb
|
359 |
7 |
aborga |
v_data_init <= "00000010"; -- DEC 2 Baudrate = 921600 bps @ 29,4912 MHz
|
360 |
3 |
aborga |
s_write_msb <= '1';
|
361 |
|
|
s_slave_init <= WRITE_DIVLTC;
|
362 |
|
|
else
|
363 |
|
|
v_add_init <= O"1"; -- init Divisor Latch msb
|
364 |
|
|
v_data_init <= "00000000";
|
365 |
|
|
s_slave_init <= ENB_FIFO;
|
366 |
|
|
end if;
|
367 |
|
|
when ENB_FIFO => -- init ENB_FIFO
|
368 |
|
|
if s_tick_delay = '0' then
|
369 |
|
|
s_tick_delay <= '1';
|
370 |
|
|
v_add_init <= O"3";
|
371 |
|
|
v_lcr_init <= "00000011"; -- Enable FIFO access
|
372 |
|
|
v_data_init <= "00000011";
|
373 |
|
|
else
|
374 |
|
|
v_add_init <= (others => '0');
|
375 |
|
|
v_data_init <= (others => '0');
|
376 |
|
|
s_tick_delay <= '0';
|
377 |
|
|
s_slave_init <= ENB_UART;
|
378 |
|
|
end if;
|
379 |
|
|
when ENB_UART => -- init ENB_UART
|
380 |
|
|
if s_tick_delay = '0' then
|
381 |
|
|
s_tick_delay <= '1';
|
382 |
|
|
s_init_done <= '1'; -- terminate init
|
383 |
|
|
s_cs_init <= '0';
|
384 |
|
|
s_wr_init <= '0';
|
385 |
|
|
v_data_init <= "00000000";
|
386 |
|
|
else
|
387 |
|
|
s_tick_delay <= '0';
|
388 |
|
|
s_init_done <= '1';
|
389 |
|
|
s_slave_init <= IDLE;
|
390 |
|
|
end if;
|
391 |
|
|
when others =>
|
392 |
|
|
s_slave_init <= IDLE;
|
393 |
|
|
end case;
|
394 |
|
|
end if;
|
395 |
|
|
end process;
|
396 |
|
|
|
397 |
|
|
|
398 |
|
|
|
399 |
|
|
|
400 |
|
|
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
401 |
|
|
-- Components mapping
|
402 |
|
|
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
403 |
|
|
|
404 |
|
|
-- cmp_cs_rd_edge : gh_edge_det
|
405 |
|
|
-- port map (
|
406 |
|
|
-- clk => lbus_clk,
|
407 |
|
|
-- rst => lbus_rst,
|
408 |
|
|
-- d => s_cs_rd,
|
409 |
|
|
-- sre => s_cs_rd_edge);
|
410 |
|
|
|
411 |
|
|
-- cmp_wr_rd_edge : gh_edge_det
|
412 |
|
|
-- port map (
|
413 |
|
|
-- clk => lbus_clk,
|
414 |
|
|
-- rst => lbus_rst,
|
415 |
|
|
-- d => s_wr_rd,
|
416 |
|
|
-- sre => s_wr_rd_edge);
|
417 |
|
|
|
418 |
|
|
-- cmp_cs_wr_edge : gh_edge_det
|
419 |
|
|
-- port map (
|
420 |
|
|
-- clk => lbus_clk,
|
421 |
|
|
-- rst => lbus_rst,
|
422 |
|
|
-- d => s_cs_wr,
|
423 |
|
|
-- sre => s_cs_wr_edge);
|
424 |
|
|
--
|
425 |
|
|
-- cmp_wr_wr_edge : gh_edge_det
|
426 |
|
|
-- port map (
|
427 |
|
|
-- clk => lbus_clk,
|
428 |
|
|
-- rst => lbus_rst,
|
429 |
|
|
-- d => s_wr_wr,
|
430 |
|
|
-- sre => s_wr_wr_edge);
|
431 |
|
|
|
432 |
|
|
end slave;
|
433 |
|
|
|
434 |
|
|
--=============================================================================
|
435 |
|
|
-- architecture end
|
436 |
|
|
--=============================================================================
|
437 |
|
|
|
438 |
|
|
|