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[/] [uart_fpga_slow_control/] [trunk/] [code/] [gh_fifo_async16_sr.vhd] - Blame information for rev 3

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1 3 aborga 
---------------------------------------------------------------------
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--      Filename:       gh_fifo_async_sr.vhd
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--
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--
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--      Description:
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--              an Asynchronous FIFO,
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--                 using "Style #2" gray code address compare
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--
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--      Copyright (c) 2006, 2008 by George Huber
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--              an OpenCores.org Project
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--              free to use, but see documentation for conditions
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--
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--      Revision        History:
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--      Revision        Date            Author          Comment
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--      --------        ----------      ---------       -----------
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--      1.0             12/23/06        h lefevre       Initial revision
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--      1.1             09/20/08        hlefevre        add simulation init
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--                                                        (to '0') to ram data
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--
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--------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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USE ieee.std_logic_arith.all;
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entity gh_fifo_async16_sr is
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        GENERIC (add_width: INTEGER :=3; -- min value is 2 (4 memory locations)
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                 data_width: INTEGER :=8 ); -- size of data bus
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        port (
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                clk_WR : in STD_LOGIC; -- write clock
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                clk_RD : in STD_LOGIC; -- read clock
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                rst    : in STD_LOGIC; -- resets counters
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                srst   : in STD_LOGIC:='0'; -- resets counters (sync with clk_WR)
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                WR     : in STD_LOGIC; -- write control
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                RD     : in STD_LOGIC; -- read control
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                D      : in STD_LOGIC_VECTOR (data_width-1 downto 0);
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                Q      : out STD_LOGIC_VECTOR (data_width-1 downto 0);
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                empty  : out STD_LOGIC;
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                full   : out STD_LOGIC);
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end entity;
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architecture a of gh_fifo_async16_sr is
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        type ram_mem_type is array (2**add_width-1 downto 0)
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                of STD_LOGIC_VECTOR (data_width-1 downto 0);
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        signal ram_mem : ram_mem_type := (others => (others => '0'));
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        signal iempty      : STD_LOGIC;
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        signal ifull       : STD_LOGIC;
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        signal add_WR_CE   : std_logic;
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        signal add_WR      : std_logic_vector(add_width downto 0); -- add_width -1 bits are used to address MEM
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        signal add_WR_GC   : std_logic_vector(add_width downto 0); -- add_width bits are used to compare
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        signal n_add_WR    : std_logic_vector(add_width downto 0); --   for empty, full flags
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        signal add_WR_RS   : std_logic_vector(add_width downto 0); -- synced to read clk
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        signal add_RD_CE   : std_logic;
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        signal add_RD      : std_logic_vector(add_width downto 0);
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        signal add_RD_GC   : std_logic_vector(add_width downto 0);
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        signal add_RD_GCwc : std_logic_vector(add_width downto 0);
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        signal n_add_RD    : std_logic_vector(add_width downto 0);
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        signal add_RD_WS   : std_logic_vector(add_width downto 0); -- synced to write clk
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        signal srst_w      : STD_LOGIC;
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        signal isrst_w     : STD_LOGIC;
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        signal srst_r      : STD_LOGIC;
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        signal isrst_r     : STD_LOGIC;
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begin
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--------------------------------------------
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------- memory -----------------------------
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--------------------------------------------
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process (clk_WR)
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begin
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        if (rising_edge(clk_WR)) then
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                if ((WR = '1') and (ifull = '0')) then
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                        ram_mem(CONV_INTEGER(add_WR(add_width-1 downto 0))) <= D;
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                end if;
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        end if;
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end process;
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        Q <= ram_mem(CONV_INTEGER(add_RD(add_width-1 downto 0)));
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-----------------------------------------
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----- Write address counter -------------
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-----------------------------------------
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        add_WR_CE <= '0' when (ifull = '1') else
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                     '0' when (WR = '0') else
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                     '1';
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        n_add_WR <= add_WR + "01";
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process (clk_WR,rst)
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begin
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        if (rst = '1') then
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                add_WR <= (others => '0');
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                add_RD_WS(add_width downto add_width-1) <= "11";
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                add_RD_WS(add_width-2 downto 0) <= (others => '0');
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                add_WR_GC <= (others => '0');
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        elsif (rising_edge(clk_WR)) then
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                add_RD_WS <= add_RD_GCwc;
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                if (srst_w = '1') then
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                        add_WR <= (others => '0');
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                        add_WR_GC <= (others => '0');
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                elsif (add_WR_CE = '1') then
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                        add_WR <= n_add_WR;
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                        for i in 0 to add_width-1 loop
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                                add_WR_GC(i) <= n_add_WR(i) xor n_add_WR(i+1);
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                        end loop;
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                        add_WR_GC(add_width) <= n_add_WR(add_width);
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                else
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                        add_WR <= add_WR;
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                        add_WR_GC <= add_WR_GC;
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                end if;
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        end if;
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end process;
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        full <= ifull;
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        ifull <= '0' when (iempty = '1') else -- just in case add_RD_WS is reset to all zero's
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                 '0' when (add_RD_WS /= add_WR_GC) else ---- instend of "11 zero's"
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                 '1';
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-----------------------------------------
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----- Read address counter --------------
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-----------------------------------------
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        add_RD_CE <= '0' when (iempty = '1') else
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                     '0' when (RD = '0') else
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                     '1';
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        n_add_RD <= add_RD + "01";
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process (clk_RD,rst)
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begin
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        if (rst = '1') then
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                add_RD <= (others => '0');
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                add_WR_RS <= (others => '0');
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                add_RD_GC <= (others => '0');
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                add_RD_GCwc(add_width downto add_width-1) <= "11";
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                add_RD_GCwc(add_width-2 downto 0) <= (others => '0');
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        elsif (rising_edge(clk_RD)) then
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                add_WR_RS <= add_WR_GC;
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                if (srst_r = '1') then
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                        add_RD <= (others => '0');
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                        add_RD_GC <= (others => '0');
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                        add_RD_GCwc(add_width downto add_width-1) <= "11";
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                        add_RD_GCwc(add_width-2 downto 0) <= (others => '0');
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                elsif (add_RD_CE = '1') then
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                        add_RD <= n_add_RD;
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                        for j in 0 to add_width-1 loop
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                                add_RD_GC(j) <= n_add_RD(j) xor n_add_RD(j+1);
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                        end loop;
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                        add_RD_GC(add_width) <= n_add_RD(add_width);
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                        for k in 0 to add_width-2 loop
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                                add_RD_GCwc(k) <= n_add_RD(k) xor n_add_RD(k+1);
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                        end loop;
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                        add_RD_GCwc(add_width-1) <= n_add_RD(add_width-1) xor (not n_add_RD(add_width));
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                        add_RD_GCwc(add_width) <= (not n_add_RD(add_width));
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                else
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                        add_RD <= add_RD;
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                        add_RD_GC <= add_RD_GC;
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                        add_RD_GCwc <= add_RD_GCwc;
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                end if;
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        end if;
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end process;
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        empty <= iempty;
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        iempty <= '1' when (add_WR_RS = add_RD_GC) else
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                  '0';
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----------------------------------
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--- sync rest stuff --------------
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--- srst is sync with clk_WR -----
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--- srst_r is sync with clk_RD ---
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----------------------------------
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process (clk_WR,rst)
181 
begin
182 
        if (rst = '1') then
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                srst_w <= '0';
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                isrst_r <= '0';
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        elsif (rising_edge(clk_WR)) then
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                isrst_r <= srst_r;
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                if (srst = '1') then
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                        srst_w <= '1';
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                elsif (isrst_r = '1') then
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                        srst_w <= '0';
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                end if;
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        end if;
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end process;
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process (clk_RD,rst)
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begin
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        if (rst = '1') then
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                srst_r <= '0';
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                isrst_w <= '0';
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        elsif (rising_edge(clk_RD)) then
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                isrst_w <= srst_w;
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                if (isrst_w = '1') then
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                        srst_r <= '1';
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                else
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                        srst_r <= '0';
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                end if;
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        end if;
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end process;
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end architecture;

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