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[/] [uart_fpga_slow_control/] [trunk/] [code/] [gh_uart_16550.vhd] - Blame information for rev 19

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1 3 aborga 
-----------------------------------------------------------------------------
2 
--      Filename:       gh_uart_16550.vhd
3 
--
4 
--      Description:
5 
--              designed to be a 16550 compatible UART
6 
--
7 
--      Copyright (c) 2006, 2007, 2008 by H LeFevre
8 
--              A VHDL 16550 UART core
9 
--              an OpenCores.org Project
10 
--              free to use, but see documentation for conditions
11 
--
12 
--      Revision        History:
13 
--      Revision        Date            Author          Comment
14 
--      --------        ----------      ---------       -----------
15 
--      1.0             02/25/06        H LeFevre       Initial revision
16 
--      1.1             03/18/06        H LeFevre       mod to clear THREmpty interrupt
17 
--                                                          with IIR read
18 
--      1.2             04/08/06        H LeFevre       add time out interrupt
19 
--      1.3             04/19/06        H LeFevre       fix read fifo signal, so fifo
20 
--                                                         will not lose data when baud rate
21 
--                                                         generator is read
22 
--      2.0             12/13/06        H LeFevre       Fixed THRE interrupt, as recommended
23 
--                                                         by Walter Hogan 12/12/06
24 
--      2.1             12/23/06        H LeFevre       replace fifo's
25 
--      2.2             01/20/07        H LeFevre       replace read fifo
26 
--      2.3             02/22/07        B Chini         Modified TOI Function To Work as Specified in 16550D manual
27 
--      2.4             07/12/07        H LeFevre       fix 6, 7 bits transfers (LCR bits 1,0 were swapped
28 
--                                                         as pointed out by Matthias Klemm
29 
--      2.5             08/03/07        H LeFevre       Mod TOI to fix issues missed in 2.3 (enabled with receiveIRQ,
30 
--                                                         time reset with receive word- as Specified in 16550D manual)
31 
--      2.6             08/04/07        H LeFevre       load TOI when receive IRQ disabled
32 
--      2.7             10/12/07        H LeFevre       fix LSR Interrupt, as suggested by Matthias Klemm
33 
--                                                      +  mod to THRE Interrupt now, will be generated
34 
--                                                         when enabled while trans FIFO is empty
35 
--                                                         (opencore bug report)
36 
--      2.7             10/13/07        H LeFevre       mod LSR Interrupt so that it will retrigger with
37 
--                                                         back to back errors
38 
--      2.8             07/21/08        H LeFevre       mod equ for iBreak_ITR [add (and (not RF_EMPTY))]
39 
--                                                         as suggested by Nathan Z.
40 
--      2.9             08/18/11        A Borga         updated gh_fifo_async16_sr: fixed bug with pointers init
41 
--
42 
--
43 
-----------------------------------------------------------------------------
44 
library ieee ;
45 
use ieee.std_logic_1164.all ;
46 
 
47 
entity gh_uart_16550 is
48 
        port(
49 
                clk     : in std_logic;                         -- Main clock
50 
                BR_clk  : in std_logic;                         -- Baudrate generator clock TX and RX
51 
                rst     : in std_logic;                         -- Reset
52 
                rst_buffer : in std_logic;                      -- Reset for FIFO and TX and RX
53 
                CS      : in std_logic;                         -- Chip select -> 1 Cycle long CS strobe = 1 data send
54 
                WR      : in std_logic;                         -- WRITE when HIGH with CS high | READ when LOW with CS high
55 
                ADD     : in std_logic_vector(2 downto 0);      -- Address bus
56 
                D       : in std_logic_vector(7 downto 0);      -- Input DATA BUS
57 
 
58 19 aborga 
                sRX     : in std_logic;                         -- uart's INPUT
59 3 aborga 
                CTSn    : in std_logic := '1';
60 
                DSRn    : in std_logic := '1';
61 
                RIn     : in std_logic := '1';
62 
                DCDn    : in std_logic := '1';
63 
 
64 19 aborga 
                sTX     : out std_logic;                        -- uart's OUTPUT
65 3 aborga 
                DTRn    : out std_logic;  -- not used
66 
                RTSn    : out std_logic;  -- not used
67 
                OUT1n   : out std_logic;  -- not used
68 
                OUT2n   : out std_logic;  -- not used
69 
                TXRDYn  : out std_logic;                        -- Tx FIFO Data Ready
70 
                RXRDYn  : out std_logic;                        -- Rx FIFO Data Ready
71 
 
72 
                IRQ     : out std_logic;  -- not used
73 
                B_CLK   : out std_logic;                        -- 16x Baudrate clock output
74 
                RD      : out std_logic_vector(7 downto 0)      -- Output DATA BUS
75 
                );
76 
end entity;
77 
 
78 
architecture a of gh_uart_16550 is
79 
 
80 
COMPONENT gh_edge_det is
81 
        PORT(
82 
                clk : in STD_LOGIC;
83 
                rst : in STD_LOGIC;
84 
                D   : in STD_LOGIC;
85 
                re  : out STD_LOGIC; -- rising edge (need sync source at D)
86 
                fe  : out STD_LOGIC; -- falling edge (need sync source at D)
87 
                sre : out STD_LOGIC; -- sync'd rising edge
88 
                sfe : out STD_LOGIC  -- sync'd falling edge
89 
                );
90 
END COMPONENT;
91 
 
92 
COMPONENT gh_register_ce is
93 
        GENERIC (size: INTEGER := 8);
94 
        PORT(
95 
                clk : IN                STD_LOGIC;
96 
                rst : IN                STD_LOGIC;
97 
                CE  : IN                STD_LOGIC; -- clock enable
98 
                D   : IN                STD_LOGIC_VECTOR(size-1 DOWNTO 0);
99 
                Q   : OUT               STD_LOGIC_VECTOR(size-1 DOWNTO 0)
100 
                );
101 
END COMPONENT;
102 
 
103 
COMPONENT gh_DECODE_3to8 is
104 
        port(
105 
                A   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0); -- address
106 
                G1  : IN  STD_LOGIC; -- enable positive
107 
                G2n : IN  STD_LOGIC; -- enable negitive
108 
                G3n : IN  STD_LOGIC; -- enable negitive
109 
                Y   : out STD_LOGIC_VECTOR(7 downto 0)
110 
                );
111 
END COMPONENT;
112 
 
113 
COMPONENT gh_jkff is
114 
        PORT(
115 
                clk  : IN STD_logic;
116 
                rst  : IN STD_logic;
117 
                J,K  : IN STD_logic;
118 
                Q    : OUT STD_LOGIC
119 
                );
120 
END COMPONENT;
121 
 
122 
COMPONENT gh_uart_Tx_8bit is
123 
        port(
124 
                clk       : in std_logic; --  clock
125 
                rst       : in std_logic;
126 
                xBRC      : in std_logic; -- x clock enable
127 
                D_RYn     : in std_logic; -- data ready
128 
                D         : in std_logic_vector(7 downto 0);
129 
                num_bits  : in integer:= 8; -- number of bits in transfer
130 
                Break_CB  : in std_logic;
131 
                stopB     : in std_logic;
132 
                Parity_EN : in std_logic;
133 
                Parity_EV : in std_logic;
134 
                sTX       : out std_logic;
135 
                BUSYn     : out std_logic;
136 
                read      : out std_logic -- data read
137 
                );
138 
END COMPONENT;
139 
 
140 
COMPONENT gh_uart_Rx_8bit is
141 
        port(
142 
                clk       : in std_logic; -- clock
143 
                rst       : in std_logic;
144 
                BRCx16    : in std_logic; -- 16x clock enable
145 
                sRX       : in std_logic;
146 
                num_bits  : in integer;
147 
                Parity_EN : in std_logic;
148 
                Parity_EV : in std_logic;
149 
                Parity_ER : out std_logic;
150 
                Frame_ER  : out std_logic;
151 
                Break_ITR : out std_logic;
152 
                D_RDY     : out std_logic;
153 
                D         : out std_logic_vector(7 downto 0)
154 
                );
155 
END COMPONENT;
156 
 
157 
COMPONENT gh_fifo_async16_sr is
158 
        GENERIC (data_width: INTEGER :=8 ); -- size of data bus
159 
        port (
160 
                clk_WR : in STD_LOGIC; -- write clock
161 
                clk_RD : in STD_LOGIC; -- read clock
162 
                rst    : in STD_LOGIC; -- resets counters
163 
                srst   : in STD_LOGIC; -- resets counters
164 
                WR     : in STD_LOGIC; -- write control
165 
                RD     : in STD_LOGIC; -- read control
166 
                D      : in STD_LOGIC_VECTOR (data_width-1 downto 0);
167 
                Q      : out STD_LOGIC_VECTOR (data_width-1 downto 0);
168 
                empty  : out STD_LOGIC;
169 
                full   : out STD_LOGIC);
170 
END COMPONENT;
171 
 
172 
COMPONENT gh_baud_rate_gen is
173 
        port(
174 
                clk     : in std_logic;
175 
                rst     : in std_logic;
176 
                BR_clk  : in std_logic;
177 
                WR      : in std_logic;
178 
                BE      : in std_logic_vector (1 downto 0); -- byte enable
179 
                D       : in std_logic_vector (15 downto 0);
180 
                RD      : out std_logic_vector (15 downto 0);
181 
                rCE     : out std_logic;
182 
                rCLK    : out std_logic
183 
                );
184 
END COMPONENT;
185 
 
186 
COMPONENT gh_fifo_async16_rcsr_wf is
187 
        GENERIC (data_width: INTEGER :=8 ); -- size of data bus
188 
        port (
189 
                clk_WR  : in STD_LOGIC; -- write clock
190 
                clk_RD  : in STD_LOGIC; -- read clock
191 
                rst     : in STD_LOGIC; -- resets counters
192 
                rc_srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_RD!!!)
193 
                WR      : in STD_LOGIC; -- write control
194 
                RD      : in STD_LOGIC; -- read control
195 
                D       : in STD_LOGIC_VECTOR (data_width-1 downto 0);
196 
                Q       : out STD_LOGIC_VECTOR (data_width-1 downto 0);
197 
                empty   : out STD_LOGIC; -- sync with clk_RD!!!
198 
                q_full  : out STD_LOGIC; -- sync with clk_RD!!!
199 
                h_full  : out STD_LOGIC; -- sync with clk_RD!!!
200 
                a_full  : out STD_LOGIC; -- sync with clk_RD!!!
201 
                full    : out STD_LOGIC);
202 
END COMPONENT;
203 
 
204 
COMPONENT  gh_counter_down_ce_ld_tc IS
205 
        GENERIC (size: INTEGER :=8);
206 
        PORT(
207 
                CLK   : IN      STD_LOGIC;
208 
                rst   : IN      STD_LOGIC;
209 
                LOAD  : IN      STD_LOGIC;
210 
                CE    : IN      STD_LOGIC;
211 
                D     : IN  STD_LOGIC_VECTOR(size-1 DOWNTO 0);
212 
                Q     : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0);
213 
                TC    : OUT STD_LOGIC
214 
                );
215 
END COMPONENT;
216 
 
217 
COMPONENT  gh_edge_det_XCD is -- added 2 aug 2007
218 
        port(
219 
                iclk : in STD_LOGIC;  -- clock for input data signal
220 
                oclk : in STD_LOGIC;  -- clock for output data pulse
221 
                rst  : in STD_LOGIC;
222 
                D    : in STD_LOGIC;
223 
                re   : out STD_LOGIC; -- rising edge
224 
                fe   : out STD_LOGIC  -- falling edge
225 
                );
226 
END COMPONENT;
227 
 
228 
        signal IER    : std_logic_vector(3 downto 0); -- Interrupt Enable Register
229 
        signal IIR    : std_logic_vector(7 downto 0); -- Interrupt ID Register
230 
        signal iIIR   : std_logic_vector(3 downto 0); -- 12/23/06
231 
        signal FCR    : std_logic_vector(7 downto 0); -- FIFO Control register
232 
        signal LCR    : std_logic_vector(7 downto 0); -- Line Control Register
233 
        signal MCR    : std_logic_vector(4 downto 0); -- Modem Control Register
234 
        signal LSR    : std_logic_vector(7 downto 0); -- Line Status Register
235 
        signal MSR    : std_logic_vector(7 downto 0); -- Modem Status Register
236 
        signal SCR    : std_logic_vector(7 downto 0); -- Line Control Register
237 
        signal RDD    : std_logic_vector(15 downto 0); -- Divisor Latch
238 
        signal iMSR   : std_logic_vector(7 downto 4); -- Modem Status Register
239 
        signal RD_IIR : std_logic;
240 
 
241 
        signal iRD    : std_logic_vector(7 downto 0);
242 
        signal CSn    : std_logic;
243 
        signal WR_B   : std_logic_vector(7 downto 0);
244 
        signal WR_F   : std_logic;
245 
        signal WR_IER : std_logic;
246 
        signal WR_D   : std_logic;
247 
        signal WR_DML : std_logic_vector(1 downto 0);
248 
        signal D16    : std_logic_vector(15 downto 0);
249 
        signal BRC16x : std_logic; -- baud rate clock
250 
 
251 
        signal ITR0   : std_logic;
252 
        signal isITR1 : std_logic;
253 
        signal sITR1  : std_logic;
254 
        signal cITR1  : std_logic;
255 
        signal cITR1a : std_logic;
256 
        signal ITR1   : std_logic;
257 
        signal ITR2   : std_logic;
258 
        signal ITR3   : std_logic;
259 
 
260 
        signal DCTS     : std_logic;
261 
        signal CTSn_RE  : std_logic;
262 
        signal CTSn_FE  : std_logic;
263 
        signal iDCTS    : std_logic;
264 
        signal iLOOP    : std_logic;
265 
 
266 
        signal DDSR     : std_logic;
267 
        signal DSRn_RE  : std_logic;
268 
        signal DSRn_FE  : std_logic;
269 
        signal iDDSR    : std_logic;
270 
 
271 
        signal TERI    : std_logic;
272 
        signal RIn_RE  : std_logic;
273 
 
274 
        signal DDCD     : std_logic;
275 
        signal DCDn_RE  : std_logic;
276 
        signal DCDn_FE  : std_logic;
277 
        signal iDDCD    : std_logic;
278 
 
279 
        signal RD_MSR   : std_logic;
280 
        signal MSR_CLR  : std_logic;
281 
 
282 
        signal RD_LSR   : std_logic;
283 
        signal LSR_CLR  : std_logic;
284 
 
285 
        signal num_bits  : integer:=0;
286 
        signal stopB     : std_logic;
287 
        signal Parity_EN : std_logic;
288 
        signal Parity_OD : std_logic;
289 
        signal Parity_EV : std_logic;
290 
--      signal Parity_sticky : std_logic;
291 
        signal Break_CB : std_logic;
292 
 
293 
        signal TF_RD    : std_logic;
294 
        signal TF_CLR   : std_logic;
295 
        signal TF_CLRS  : std_logic;
296 
        signal TF_DO    : std_logic_vector(7 downto 0);
297 
        signal TF_empty : std_logic;
298 
        signal TF_full  : std_logic;
299 
 
300 
        signal RF_WR     : std_logic;
301 
        signal RF_RD     : std_logic;
302 
        signal RF_RD_brs : std_logic; -- added 3 aug 2007
303 
        signal RF_CLR    : std_logic;
304 
        signal RF_CLRS   : std_logic;
305 
        signal RF_DI     : std_logic_vector(10 downto 0); -- Read FIFO data input
306 
        signal RF_DO     : std_logic_vector(10 downto 0); -- Read FIFO data output
307 
        signal RF_empty  : std_logic;
308 
        signal RF_full   : std_logic;
309 
        signal RD_RDY    : std_logic;
310 
 
311 
        signal iParity_ER : std_logic; -- added 13 oct 2007
312 
        signal iFRAME_ER  : std_logic; -- added 13 oct 2007
313 
        signal iBreak_ITR : std_logic; -- added 13 oct 2007
314 
        signal Parity_ER  : std_logic;
315 
        signal FRAME_ER   : std_logic;
316 
        signal Break_ITR  : std_logic;
317 
        signal TSR_EMPTY  : std_logic;
318 
        signal OVR_ER     : std_logic;
319 
        signal isTX       : std_logic;
320 
        signal isRX       : std_logic;
321 
 
322 
        signal q_full   : std_logic;
323 
        signal h_full   : std_logic;
324 
        signal a_full   : std_logic;
325 
 
326 
        signal RF_ER   : std_logic;
327 
        signal TX_RDY  : std_logic;
328 
        signal TX_RDYS : std_logic;
329 
        signal TX_RDYC : std_logic;
330 
        signal RX_RDY  : std_logic;
331 
        signal RX_RDYS : std_logic;
332 
        signal RX_RDYC : std_logic;
333 
 
334 
        signal TOI      : std_logic; -- time out interrupt
335 
        signal TOI_enc  : std_logic; -- time out interrupt counter inable
336 
        signal iTOI_enc : std_logic;
337 
        signal TOI_set  : std_logic;
338 
        signal iTOI_set : std_logic; -- added 3 aug 2007
339 
        signal TOI_clr  : std_logic;
340 
        signal TOI_c_ld : std_logic;
341 
        signal TOI_c_d  : std_logic_vector(11 downto 0);
342 
 
343 
begin
344 
 
345 
----------------------------------------------
346 
---- resd   ----------------------------------
347 
----------------------------------------------
348 
 
349 
        RD <= RF_DO(7 downto 0) when ((ADD = o"0") and (LCR(7) = '0')) else
350 
              (x"0" & IER) when ((ADD = o"1") and (LCR(7) = '0')) else
351 
              IIR when (ADD = o"2") else
352 
              LCR when (ADD = o"3") else
353 
              ("000" & MCR) when (ADD = o"4") else
354 
              LSR when (ADD = o"5") else
355 
              MSR when (ADD = o"6") else
356 
              SCR when (ADD = o"7") else
357 
              RDD(7 downto 0) when (ADD = o"0") else
358 
              RDD(15 downto 8);
359 
 
360 
----------------------------------------------
361 
 
362 
U1 : gh_jkff
363 
        PORT MAP (
364 
                clk => clk,
365 
                rst => rst,
366 
                j => TX_RDYS,
367 
                k => TX_RDYC,
368 
                Q => TX_RDY);
369 
 
370 
        TXRDYn <= (not TX_RDY);
371 
 
372 
        TX_RDYS <= '1' when ((FCR(3) = '0') and (TF_empty = '1') and (TSR_EMPTY = '1')) else
373 
                   '1' when ((FCR(3) = '1') and (TF_empty = '1')) else
374 
                   '0';
375 
 
376 
        TX_RDYC <= '1' when ((FCR(3) = '0') and (TF_empty = '0')) else
377 
                   '1' when ((FCR(3) = '1') and (TF_full = '1')) else
378 
                   '0';
379 
 
380 
U2 : gh_jkff
381 
        PORT MAP (
382 
                clk => clk,
383 
                rst => rst,
384 
                j => RX_RDYS,
385 
                k => RX_RDYC,
386 
                Q => RX_RDY);
387 
 
388 
        RXRDYn <= (not RX_RDY);
389 
 
390 
        RX_RDYS <= '1' when ((FCR(3) = '0') and (RF_empty = '0')) else    -- mod 01/20/07
391 
                   '1' when ((FCR(3) = '1') and (FCR(7 downto 6) = "11") and (a_full = '1')) else
392 
                   '1' when ((FCR(3) = '1') and (FCR(7 downto 6) = "10") and (h_full = '1')) else
393 
                   '1' when ((FCR(3) = '1') and (FCR(7 downto 6) = "01") and (q_full = '1')) else
394 
                   '1' when ((FCR(3) = '1') and (FCR(7 downto 6) = "00") and (RF_empty = '0')) else
395 
                   '0';
396 
 
397 
 
398 
        RX_RDYC <= '1' when (RF_empty = '1') else
399 
                   '0';
400 
 
401 
 
402 
----------------------------------------------
403 
---- Modem Status Register Bits --------------
404 
----------------------------------------------
405 
 
406 
U3 : gh_edge_det
407 
        PORT MAP (
408 
                clk => clk,
409 
                rst => rst,
410 
                d => CTSn,
411 
                sre => CTSn_RE,
412 
                sfe => CTSn_FE);
413 
 
414 
        iDCTS <= CTSn_RE or CTSn_FE;
415 
 
416 
U4 : gh_jkff
417 
        PORT MAP (
418 
                clk => clk,
419 
                rst => rst,
420 
                j => iDCTS,
421 
                k => MSR_CLR,
422 
                Q => DCTS);
423 
 
424 
        MSR(0) <= DCTS;
425 
 
426 
U5 : gh_edge_det
427 
        PORT MAP (
428 
                clk => clk,
429 
                rst => rst,
430 
                d => DSRn,
431 
                sre => DSRn_RE,
432 
                sfe => DSRn_FE);
433 
 
434 
        iDDSR <= DSRn_RE or DSRn_FE;
435 
 
436 
U6 : gh_jkff
437 
        PORT MAP (
438 
                clk => clk,
439 
                rst => rst,
440 
                j => iDDSR,
441 
                k => MSR_CLR,
442 
                Q => DDSR);
443 
 
444 
        MSR(1) <= DDSR;
445 
 
446 
U7 : gh_edge_det
447 
        PORT MAP (
448 
                clk => clk,
449 
                rst => rst,
450 
                d => RIn,
451 
                sre => RIn_RE);
452 
 
453 
U8 : gh_jkff
454 
        PORT MAP (
455 
                clk => clk,
456 
                rst => rst,
457 
                j => RIn_RE,
458 
                k => MSR_CLR,
459 
                Q => TERI);
460 
 
461 
        MSR(2) <= TERI;
462 
 
463 
U9 : gh_edge_det
464 
        PORT MAP (
465 
                clk => clk,
466 
                rst => rst,
467 
                d => DCDn,
468 
                sre => DCDn_RE,
469 
                sfe => DCDn_FE);
470 
 
471 
        iDDCD <= DCDn_RE or DCDn_FE;
472 
 
473 
U10 : gh_jkff
474 
        PORT MAP (
475 
                clk => clk,
476 
                rst => rst,
477 
                j => iDDCD,
478 
                k => MSR_CLR,
479 
                Q => DDCD);
480 
 
481 
        MSR(3) <= DDCD;
482 
 
483 
        iMSR(4) <= (not CTSn) when (iLOOP = '0') else
484 
                    MCR(1);
485 
 
486 
        iMSR(5) <= (not DSRn) when (iLOOP = '0') else
487 
                    MCR(0);
488 
 
489 
        iMSR(6) <= (not RIn) when (iLOOP = '0') else
490 
                    MCR(2);
491 
 
492 
        iMSR(7) <= (not DCDn) when (iLOOP = '0') else
493 
                    MCR(3);
494 
 
495 
        RD_MSR <= '0' when ((CS = '0') or (WR = '1')) else
496 
                  '0' when (ADD /= o"6") else
497 
                  '1';
498 
 
499 
 
500 
        ITR0 <= '0' when (IER(3) = '0') else
501 
                '1' when (MSR(3 downto 0) > x"0") else
502 
                '0';
503 
 
504 
U11 : gh_edge_det
505 
        PORT MAP (
506 
                clk => clk,
507 
                rst => rst,
508 
                d => RD_MSR,
509 
                sfe => MSR_CLR);
510 
 
511 
u12 : gh_register_ce
512 
        generic map (4)
513 
        port map(
514 
                clk => clk,
515 
                rst => rst,
516 
                ce => '1',
517 
                D => iMSR,
518 
                Q => MSR(7 downto 4)
519 
                );
520 
 
521 
---------------------------------------------------
522 
-------- LSR --------------------------------------
523 
---------------------------------------------------
524 
 
525 
        LSR(0) <= (not RF_empty);
526 
 
527 
U13 : gh_jkff
528 
        PORT MAP (
529 
                clk => clk,
530 
                rst => rst,
531 
                j => OVR_ER,
532 
                k => LSR_CLR,
533 
                Q => LSR(1));
534 
 
535 
        OVR_ER <= '1' when ((RF_full = '1') and (RF_WR = '1')) else
536 
                  '0';
537 
 
538 
U14 : gh_jkff
539 
        PORT MAP (
540 
                clk => clk,
541 
                rst => rst,
542 
                j => PARITY_ER,
543 
                k => LSR_CLR,
544 
                Q => LSR(2));
545 
 
546 
U15 : gh_jkff
547 
        PORT MAP (
548 
                clk => clk,
549 
                rst => rst,
550 
                j => FRAME_ER,
551 
                k => LSR_CLR,
552 
                Q => LSR(3));
553 
 
554 
U16 : gh_jkff
555 
        PORT MAP (
556 
                clk => clk,
557 
                rst => rst,
558 
                j => Break_ITR,
559 
                k => LSR_CLR,
560 
                Q => LSR(4));
561 
 
562 
        LSR(5) <= TF_EMPTY;
563 
        LSR(6) <= TF_EMPTY and TSR_EMPTY;
564 
 
565 
U17 : gh_jkff
566 
        PORT MAP (
567 
                clk => clk,
568 
                rst => rst,
569 
                j => RF_ER,
570 
                k => LSR_CLR,
571 
                Q => LSR(7));
572 
 
573 
        RF_ER <= '1' when (RF_DI(10 downto 8) > "000") else
574 
                 '0';
575 
 
576 
        RD_LSR <= '0' when ((CS = '0') or (WR = '1')) else
577 
                  '0' when (ADD /= o"5") else
578 
                  '1';
579 
 
580 
U18 : gh_edge_det
581 
        PORT MAP (
582 
                clk => clk,
583 
                rst => rst,
584 
                d => RD_LSR,
585 
                sfe => LSR_CLR);
586 
 
587 
----------------------------------------------
588 
------  registers -------
589 
----------------------------------------------
590 
 
591 
        CSn <= (not CS);
592 
 
593 
 
594 
u19 : gh_DECODE_3to8
595 
        port map(
596 
                A => ADD,
597 
                G1 => WR,
598 
                G2n => CSn,
599 
                G3n => '0',
600 
                Y => WR_B
601 
                );
602 
 
603 
        WR_F <= WR_B(0) and (not LCR(7));
604 
        WR_IER <= WR_B(1) and (not LCR(7));
605 
        WR_D <= LCR(7) and (WR_B(0) or WR_B(1));
606 
        WR_DML <= (WR_B(1) and LCR(7)) & (WR_B(0) and LCR(7));
607 
 
608 
u20 : gh_register_ce
609 
        generic map (4)
610 
        port map(
611 
                clk => clk,
612 
                rst => rst,
613 
                ce => WR_IER,
614 
                D => D(3 downto 0),
615 
                Q => IER
616 
                );
617 
 
618 
u21 : gh_register_ce
619 
        generic map (8)
620 
        port map(
621 
                clk => clk,
622 
                rst => rst,
623 
                ce => WR_B(2),
624 
                D => D,
625 
                Q => FCR
626 
                );
627 
 
628 
U22 : gh_jkff
629 
        PORT MAP (
630 
                clk => clk,
631 
                rst => rst,
632 
                j => RF_CLRS,
633 
                k => RF_EMPTY,
634 
                Q => RF_CLR);
635 
 
636 
        RF_CLRS <= D(1) AND WR_B(2);
637 
 
638 
U23 : gh_jkff
639 
        PORT MAP (
640 
                clk => clk,
641 
                rst => rst,
642 
                j => TF_CLRS,
643 
                k => TF_EMPTY,
644 
                Q => TF_CLR);
645 
 
646 
        TF_CLRS <= D(2) AND WR_B(2);
647 
 
648 
u24 : gh_register_ce
649 
        generic map (8)
650 
        port map(
651 
                clk => clk,
652 
                rst => rst,
653 
                ce => WR_B(3),
654 
                D => D,
655 
                Q => LCR
656 
                );
657 
 
658 
        num_bits <= 5 when ((LCR(0) = '0') and (LCR(1) = '0')) else
659 
                    6 when ((LCR(0) = '1') and (LCR(1) = '0')) else        -- 07/12/07
660 
                    7 when ((LCR(0) = '0') and (LCR(1) = '1')) else        -- 07/12/07
661 
                    8;
662 
 
663 
        stopB <= LCR(2);
664 
 
665 
        Parity_EN <= LCR(3);
666 
        Parity_OD <= LCR(3) and (not LCR(4)) and (not LCR(5));
667 
        Parity_EV <= LCR(3) and LCR(4) and (not LCR(5));
668 
--      Parity_sticky <= LCR(3) and LCR(5);
669 
        Break_CB <= LCR(6);
670 
 
671 
u25 : gh_register_ce
672 
        generic map (5)
673 
        port map(
674 
                clk => clk,
675 
                rst => rst,
676 
                ce => WR_B(4),
677 
                D => D(4 downto 0),
678 
                Q => MCR
679 
                );
680 
 
681 
        DTRn <= (not MCR(0)) or iLOOP;
682 
        RTSn <= (not MCR(1)) or iLOOP;
683 
        OUT1n <= (not MCR(2)) or iLOOP;
684 
        OUT2n <= (not MCR(3)) or iLOOP;
685 
        iLOOP <= MCR(4);
686 
 
687 
u26 : gh_register_ce
688 
        generic map (8)
689 
        port map(
690 
                clk => clk,
691 
                rst => rst,
692 
                ce => WR_B(7),
693 
                D => D,
694 
                Q => SCR
695 
                );
696 
 
697 
----------------------------------------------------------
698 
 
699 
        D16 <= D & D;
700 
 
701 
u27 : gh_baud_rate_gen
702 
        port map(
703 
                clk => clk,
704 
                BR_clk => BR_clk,
705 
                rst  => rst,
706 
                WR => WR_D,
707 
                BE => WR_DML,
708 
                D => D16,
709 
                RD => RDD,
710 
                rCE => BRC16x,
711 
                rCLK => B_clk
712 
                );
713 
 
714 
--------------------------------------------------
715 
---- trans FIFO   12/23/06 -----------------------
716 
--------------------------------------------------
717 
 
718 
U28 : gh_fifo_async16_sr
719 
        Generic Map(data_width => 8)
720 
        PORT MAP (
721 
                clk_WR => clk,
722 
                clk_RD => BR_clk,
723 
                rst => rst_buffer,
724 
                srst => TF_CLR,
725 
                WR => WR_F,
726 
                RD => TF_RD,
727 
                D => D,
728 
                Q => TF_DO,
729 
                empty => TF_empty,
730 
                full => TF_full);
731 
 
732 
----------------------------------------------------------------
733 
----------- added 03/18/06 -------------------------------------
734 
-----------  mod 10/12/07 --------------------------------------
735 
 
736 
U28a : gh_edge_det
737 
        PORT MAP (
738 
                clk => clk,
739 
                rst => rst,
740 
                d => isITR1,
741 
                sre => sITR1);
742 
 
743 
        isITR1 <= TF_empty and IER(1);
744 
 
745 
---------- end mod 10/12/07 -----------------
746 
 
747 
        RD_IIR <= '0' when (ADD /= o"2") else
748 
                  '0' when (WR = '1') else
749 
                  '0' when (CS = '0') else
750 
                  '0' when (IIR(3 downto 1) /= "001") else -- walter hogan 12/12/2006
751 
                  '1';
752 
 
753 
U28b : gh_edge_det
754 
        PORT MAP (
755 
                clk => clk,
756 
                rst => rst,
757 
                d => RD_IIR,
758 
                sfe => cITR1a);
759 
 
760 
        cITR1 <= cITR1a or (not TF_empty);
761 
 
762 
U28c : gh_jkff
763 
        PORT MAP (
764 
                clk => clk,
765 
                rst => rst,
766 
                j => sITR1,
767 
                k => cITR1,
768 
                Q => ITR1);
769 
 
770 
----------- added 03/18/06 ------------------------------------------
771 
---------------------------------------------------------------------
772 
 
773 
U29 : gh_UART_Tx_8bit
774 
        PORT MAP (
775 
                clk => BR_clk,
776 
                rst => rst_buffer,
777 
                xBRC => BRC16x,
778 
                D_RYn => TF_empty,
779 
                D => TF_DO,
780 
                num_bits => num_bits,
781 
                Break_CB => Break_CB,
782 
                StopB => stopB,
783 
                Parity_EN => Parity_EN,
784 
                Parity_EV => Parity_EV,
785 
                sTX => isTX,
786 
                BUSYn => TSR_EMPTY,
787 
                read => TF_RD);
788 
 
789 
        sTX <= isTX;
790 
 
791 
--------------------------------------------------
792 
---- Receive FIFO ----------------------------------
793 
--------------------------------------------------
794 
 
795 
U30 : gh_edge_det
796 
        PORT MAP (
797 
                clk => BR_clk,
798 
                rst => rst,
799 
                d => RD_RDY,
800 
                re => RF_WR);
801 
 
802 
        RF_RD <= '0' when (LCR(7) = '1') else -- added 04/19/06
803 
                 '1' when ((ADD = "000") and (CS = '1') and (WR = '0')) else
804 
                 '0';
805 
 
806 
U31 : gh_fifo_async16_rcsr_wf -- 01/20/07
807 
        Generic Map(data_width => 11)
808 
        PORT MAP (
809 
                clk_WR => BR_clk,
810 
                clk_RD => clk,
811 
                rst => rst_buffer,
812 
                rc_srst => RF_CLR,
813 
                WR => RF_WR,
814 
                RD => RF_RD,
815 
                D => RF_DI,
816 
                Q => RF_DO,
817 
                empty => RF_empty,
818 
                q_full => q_full,
819 
                h_full => h_full,
820 
                a_full => a_full,
821 
                full => RF_full);
822 
 
823 
------------ 10/12/07 --------------------------------------
824 
----- as suggested  Matthias Klemm -------------------------
825 
----- mod 10/13/07 -----------------------------------------
826 
 
827 
        iParity_ER <= RF_DO(8) and (not RF_RD);
828 
 
829 
U32a : gh_edge_det
830 
        PORT MAP (
831 
                clk => clk,
832 
                rst => rst,
833 
                d => iParity_ER,
834 
                sre => Parity_ER);
835 
 
836 
        iFRAME_ER <= RF_DO(9) and (not RF_RD);
837 
 
838 
U32b : gh_edge_det
839 
        PORT MAP (
840 
                clk => clk,
841 
                rst => rst,
842 
                d => iFRAME_ER,
843 
                sre => FRAME_ER);
844 
 
845 
        iBreak_ITR <= RF_DO(10) and (not RF_RD) and (not RF_EMPTY);     -- 07/21/08
846 
 
847 
U32c : gh_edge_det
848 
        PORT MAP (
849 
                clk => clk,
850 
                rst => rst,
851 
                d => iBreak_ITR,
852 
                sre => Break_ITR);
853 
 
854 
        ITR3 <= '0' when (IER(2) = '0') else
855 
                '1' when (LSR(1) = '1') else
856 
                '1' when (LSR(4 downto 2) > "000") else
857 
                '0';
858 
 
859 
-----------------------------------------------------------------------
860 
 
861 
 
862 
        isRX <= sRX when (iLOOP = '0') else
863 
                isTX;
864 
 
865 
 
866 
        ITR2 <= '0' when (IER(0) = '0') else  -- mod 01/20/07
867 
                '1' when ((FCR(7 downto 6) = "11") and (a_full = '1')) else
868 
                '1' when ((FCR(7 downto 6) = "10") and (h_full = '1')) else
869 
                '1' when ((FCR(7 downto 6) = "01") and (q_full = '1')) else
870 
                '1' when ((FCR(7 downto 6) = "00") and(RF_empty = '0')) else
871 
                '0';
872 
 
873 
U33 : gh_UART_Rx_8bit
874 
        PORT MAP (
875 
                clk => BR_clk,
876 
                rst => rst_buffer,
877 
                BRCx16 => BRC16x,
878 
                sRX => isRX,
879 
                num_bits => num_bits,
880 
                Parity_EN => Parity_EN,
881 
                Parity_EV => Parity_EV,
882 
                Parity_ER => RF_DI(8),
883 
                FRAME_ER => RF_DI(9),
884 
                Break_ITR => RF_DI(10),
885 
                D_RDY => RD_RDY,
886 
                D => RF_DI(7 downto 0)
887 
                );
888 
 
889 
----------------------------------------------------------------
890 
---------- added 04/08/06 time out interrupt -------------------
891 
---------- once there a received data word is recieved, --------
892 
---------- the counter will be running until -------------------
893 
---------- FIFO is empty, counter reset on FIFO read or write --
894 
------- mod 3 aug 2007
895 
 
896 
        TOI_clr <= RF_empty or RF_RD or (not IER(0));
897 
 
898 
U34 : gh_jkff
899 
        PORT MAP (
900 
                clk => clk,
901 
                rst => rst,
902 
                j => TOI_set,
903 
                k => TOI_clr,
904 
                Q => TOI);
905 
 
906 
U35 : gh_jkff
907 
        PORT MAP (
908 
                clk => clk,
909 
                rst => rst,
910 
                j => LSR(0), -- enable time out counter with received data
911 
                k => RF_empty, -- once FIFO is empty, stop counter
912 
                Q => iTOI_enc);
913 
 
914 
U35a : gh_edge_det_XCD
915 
        PORT MAP (
916 
                iclk => clk,
917 
                oclk => BR_clk,
918 
                rst => rst,
919 
                d => RF_RD,
920 
                re => RF_RD_brs,
921 
                fe => open);
922 
 
923 
process(BR_clk,rst)
924 
begin
925 
        if (rst = '1') then
926 
                TOI_enc <= '0';
927 
        elsif (rising_edge(BR_clk)) then
928 
                TOI_enc <= iTOI_enc;
929 
        end if;
930 
end process;
931 
 
932 
        TOI_c_ld <= '1' when (IER(0) = '0') else -- added 4 aug 2007
933 
                    '1' when (TOI_enc = '0') else
934 
                    '1' when (RF_RD_brs = '1') else
935 
                    '1' when (RF_WR = '1') else
936 
                    '0';
937 
 
938 
U36 : gh_counter_down_ce_ld_tc
939 
        generic map(10)
940 
        port map(
941 
                clk => BR_clk,
942 
                rst => rst,
943 
                LOAD => TOI_c_ld,
944 
                CE => BRC16x,
945 
                D => TOI_c_d(9 downto 0),
946 
--              Q => ,
947 
                TC => iTOI_set
948 
                );
949 
 
950 
U36a : gh_edge_det_XCD
951 
        PORT MAP (
952 
                iclk => BR_clk,
953 
                oclk => clk,
954 
                rst => rst,
955 
                d => iTOI_set,
956 
                re => TOI_set,
957 
                fe => open);
958 
 
959 
 
960 
        TOI_c_d <= x"1C0" when (num_bits = 5) else
961 
                   x"200" when (num_bits = 6) else
962 
                   x"240" when (num_bits = 7) else
963 
                   x"280";-- when (num_bits = 8)
964 
 
965 
--------------------------------------------------------------
966 
--------------------------------------------------------------
967 
 
968 
        IRQ <= '1' when ((ITR3 or ITR2 or TOI or ITR1 or ITR0) = '1') else
969 
               '0';
970 
 
971 
        iIIR(0) <= '0' when ((ITR3 or ITR2 or TOI or ITR1 or ITR0) = '1') else
972 
                   '1';
973 
 
974 
        iIIR(3 downto 1) <= "011" when (ITR3 = '1') else
975 
                            "010" when (ITR2 = '1') else
976 
                            "110" when (TOI  = '1') else        -- added 04/08/06
977 
                            "001" when (ITR1 = '1') else
978 
                            "000";
979 
 
980 
        IIR(7 downto 4) <= x"C"; -- FIFO's always enabled
981 
 
982 
u37 : gh_register_ce -- 12/23/06
983 
        generic map (4)
984 
        port map(
985 
                clk => clk,
986 
                rst => rst,
987 
                ce => CSn,
988 
                D => iIIR,
989 
                Q => IIR(3 downto 0)
990 
                );
991 
 
992 
--------------------------------------------------------------
993 
 
994 
end a;

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