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[/] [uart_fpga_slow_control/] [trunk/] [code/] [gh_uart_Rx_8bit.vhd] - Blame information for rev 20

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-----------------------------------------------------------------------------
--      Filename:       gh_uart_Rx_8bit.vhd
--
--      Description:
--              an 8 bit UART Rx Module
--
--      Copyright (c) 2006 by H LeFevre 
--              A VHDL 16550 UART core
--              an OpenCores.org Project
--              free to use, but see documentation for conditions 
--
--      Revision        History:
--      Revision        Date            Author          Comment
--      --------        ----------      ---------       -----------
--      1.0             02/18/06        H LeFevre       Initial revision
--      1.1             02/25/06        H LeFevre       mod to SM, goes to idle faster
--                                                         if no break error  
--      2.0             06/18/07        P.Azkarate  Define "range" in R_WCOUNT and R_brdCOUNT signals
-----------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
 
entity gh_uart_Rx_8bit is
        port(
                clk       : in std_logic; -- clock
                rst       : in std_logic;
                BRCx16    : in std_logic; -- 16x clock enable
                sRX       : in std_logic;
                num_bits  : in integer;
                Parity_EN : in std_logic;
                Parity_EV : in std_logic;
                Parity_ER : out std_logic;
                Frame_ER  : out std_logic;
                Break_ITR : out std_logic;
                D_RDY     : out std_logic;
                D         : out std_logic_vector(7 downto 0)
                );
end entity;
 
architecture a of gh_uart_Rx_8bit is
 
COMPONENT gh_shift_reg_se_sl is
        GENERIC (size: INTEGER := 16);
        PORT(
                clk      : IN STD_logic;
                rst      : IN STD_logic;
                srst     : IN STD_logic:='0';
                SE       : IN STD_logic; -- shift enable
                D        : IN STD_LOGIC;
                Q        : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
                );
END COMPONENT;
 
COMPONENT gh_parity_gen_Serial is
        PORT(
                clk      : IN STD_LOGIC;
                rst      : IN STD_LOGIC;
                srst     : in STD_LOGIC;
                SD       : in STD_LOGIC; -- sample data pulse
                D        : in STD_LOGIC; -- data
                Q        : out STD_LOGIC
                );
END COMPONENT;
 
COMPONENT gh_counter_integer_down IS
        generic(max_count : integer := 8);
        PORT(
                clk      : IN STD_LOGIC;
                rst      : IN STD_LOGIC;
                LOAD     : in STD_LOGIC; -- load D
                CE       : IN STD_LOGIC; -- count enable
                D        : in integer RANGE 0 TO max_count;
                Q        : out integer RANGE 0 TO max_count
                );
END COMPONENT;
 
COMPONENT gh_jkff is
        PORT(
                clk  : IN STD_logic;
                rst  : IN STD_logic;
                J,K  : IN STD_logic;
                Q    : OUT STD_LOGIC
                );
END COMPONENT;
 
        type R_StateType is (idle,R_start_bit,shift_data,R_parity,
                             R_stop_bit,break_err);
        signal R_state, R_nstate : R_StateType;
 
        signal parity      : std_logic;
        signal parity_Grst : std_logic;
        signal RWC_LD      : std_logic;
        signal R_WCOUNT : integer range 0 to 15;
        signal s_DATA_LD : std_logic;
        signal chk_par : std_logic;
        signal chk_frm : std_logic;
        signal clr_brk : std_logic;
        signal clr_D : std_logic;
        signal s_chk_par : std_logic;
        signal s_chk_frm : std_logic;
        signal R_shift_reg : std_logic_vector(7 downto 0);
        signal iRX : std_logic;
        signal BRC : std_logic;
        signal dCLK_LD : std_logic;
        signal R_brdCOUNT : integer range 0 to 15;
        signal iParity_ER : std_logic;
        signal iFrame_ER : std_logic;
        signal iBreak_ITR : std_logic;
        signal iD_RDY : std_logic;
 
begin
 
----------------------------------------------
---- outputs----------------------------------
----------------------------------------------
process(CLK,rst)
begin
        if (rst = '1') then
                Parity_ER <= '0';
                Frame_ER <= '0';
                Break_ITR <= '0';
                D_RDY <= '0';
        elsif (rising_edge(CLK)) then
                if (BRCx16 = '1') then
                        D_RDY <= iD_RDY;
                        if (iD_RDY = '1') then
                                Parity_ER <= iParity_ER;
                                Frame_ER <= iFrame_ER;
                                Break_ITR <= iBreak_ITR;
                        end if;
                end if;
        end if;
end process;
 
        D <= R_shift_reg when (num_bits = 8) else
            ('0' & R_shift_reg(7 downto 1)) when (num_bits = 7) else
            ("00" & R_shift_reg(7 downto 2)) when (num_bits = 6) else
            ("000" & R_shift_reg(7 downto 3)); -- when (bits_word = 5) else
 
 
----------------------------------------------
 
        dCLK_LD <= '1' when (R_state = idle) else
                   '0';
 
        BRC <= '0' when (BRCx16 = '0') else
               '1' when (R_brdCOUNT = 0) else
               '0';
 
u1 : gh_counter_integer_down -- baud rate divider
        generic map (15)
        port map(
                clk => clk,
                rst  => rst,
                LOAD => dCLK_LD,
                CE => BRCx16,
                D => 14,
                Q => R_brdCOUNT);
 
----------------------------------------------------------
 
U2 : gh_shift_reg_se_sl
        Generic Map(8)
        PORT MAP (
                clk => clk,
                rst => rst,
                srst => clr_D,
                SE => s_DATA_LD,
                D => sRX,
                Q => R_shift_reg);
 
-----------------------------------------------------------
 
        chk_par <= s_chk_par and (((parity xor iRX) and Parity_EV)
                         or (((not parity) xor iRX) and (not Parity_EV)));
 
U2c : gh_jkff
        PORT MAP (
                clk => clk,
                rst => rst,
                j => chk_par,
                k => dCLK_LD,
                Q => iParity_ER);
 
        chk_frm <= s_chk_frm and (not iRX);
 
U2d : gh_jkff
        PORT MAP (
                clk => clk,
                rst => rst,
                j => chk_frm,
                k => dCLK_LD,
                Q => iFrame_ER);
 
U2e : gh_jkff
        PORT MAP (
                clk => clk,
                rst => rst,
                j => clr_d,
                k => clr_brk,
                Q => iBreak_ITR);
 
--------------------------------------------------------------
--------------------------------------------------------------
 
 
process(R_state,BRCx16,BRC,iRX,R_WCOUNT,Parity_EN,R_brdCOUNT,iBreak_ITR)
begin
        case R_state is
                when idle => -- idle  
                        iD_RDY <= '0'; s_DATA_LD <= '0'; RWC_LD <= '1';
                        s_chk_par <= '0'; s_chk_frm <= '0'; clr_brk <= '0';
                        clr_D <= '0';
                        if (iRX = '0') then
                                R_nstate <= R_start_bit;
                        else
                                R_nstate <= idle;
                        end if;
                when R_start_bit => -- 
                        iD_RDY <= '0'; s_DATA_LD <= '0'; RWC_LD <= '1';
                        s_chk_par <= '0'; s_chk_frm <= '0'; clr_brk <= '0';
                        if (BRC = '1') then
                                clr_D <= '1';
                                R_nstate <= shift_data;
                        elsif ((R_brdCOUNT = 8) and (iRX = '1')) then -- false start bit detection
                                clr_D <= '0';
                                R_nstate <= idle;
                        else
                                clr_D <= '0';
                                R_nstate <= R_start_bit;
                        end if;
                when shift_data => -- send data bit     
                        iD_RDY <= '0'; RWC_LD <= '0';
                        s_chk_par <= '0'; s_chk_frm <= '0';
                        clr_D <= '0';
                        if (BRCx16 = '0') then
                                s_DATA_LD <= '0'; clr_brk <= '0';
                                R_nstate <= shift_data;
                        elsif (R_brdCOUNT = 8) then
                                s_DATA_LD <= '1'; clr_brk <= iRX;
                                R_nstate <= shift_data;
                        elsif ((R_WCOUNT = 1) and (R_brdCOUNT = 0) and (Parity_EN = '1')) then
                                s_DATA_LD <= '0'; clr_brk <= '0';
                                R_nstate <= R_parity;
                        elsif ((R_WCOUNT = 1) and (R_brdCOUNT = 0)) then
                                s_DATA_LD <= '0'; clr_brk <= '0';
                                R_nstate <= R_stop_bit;
                        else
                                s_DATA_LD <= '0'; clr_brk <= '0';
                                R_nstate <= shift_data;
                        end if;
                when R_parity => -- check parity bit
                        iD_RDY <= '0'; s_DATA_LD <= '0';
                        RWC_LD <= '0'; s_chk_frm <= '0';
                        clr_D <= '0';
                        if (BRCx16 = '0') then
                                s_chk_par <= '0';  clr_brk <= '0';
                                R_nstate <= R_parity;
                        elsif (R_brdCOUNT = 8) then
                                s_chk_par <= '1'; clr_brk <= iRX;
                                R_nstate <= R_parity;
                        elsif (BRC = '1') then
                                s_chk_par <= '0'; clr_brk <= '0';
                                R_nstate <= R_stop_bit;
                        else
                                s_chk_par <= '0'; clr_brk <= '0';
                                R_nstate <= R_parity;
                        end if;
                when R_stop_bit => -- check stop bit
                        s_DATA_LD <= '0'; RWC_LD <= '0';
                        s_chk_par <= '0'; clr_brk <= iRX;
                        clr_D <= '0';
                        if ((BRC = '1') and (iBreak_ITR = '1')) then
                                iD_RDY <= '1'; s_chk_frm <= '0';
                                R_nstate <= break_err;
                        elsif (BRC = '1') then
                                iD_RDY <= '1'; s_chk_frm <= '0';
                                R_nstate <=     idle;
                        elsif (R_brdCOUNT = 8) then
                                iD_RDY <= '0'; s_chk_frm <= '1';
                                R_nstate <= R_stop_bit;
                        elsif ((R_brdCOUNT = 7) and (iBreak_ITR = '0')) then -- added 02/20/06
                                iD_RDY <= '1'; s_chk_frm <= '0';
                                R_nstate <=     idle;
                        else
                                iD_RDY <= '0'; s_chk_frm <= '0';
                                R_nstate <= R_stop_bit;
                        end if;
                when break_err =>
                        iD_RDY <= '0'; s_DATA_LD <= '0'; RWC_LD <= '0';
                        s_chk_par <= '0'; s_chk_frm <= '0'; clr_brk <= '0';
                        clr_D <= '0';
                        if (iRX = '1') then
                                R_nstate <= idle;
                        else
                                R_nstate <= break_err;
                        end if;
                when others =>
                        iD_RDY <= '0'; s_DATA_LD <= '0'; RWC_LD <= '0';
                        s_chk_par <= '0'; s_chk_frm <= '0'; clr_brk <= '0';
                        clr_D <= '0';
                        R_nstate <= idle;
        end case;
end process;
 
--
-- registers for SM
process(CLK,rst)
begin
        if (rst = '1') then
                iRX <= '1';
                R_state <= idle;
        elsif (rising_edge(CLK)) then
                if (BRCx16 = '1') then
                        iRX <= sRX;
                        R_state <= R_nstate;
                else
                        iRX <= iRX;
                        R_state <= R_state;
                end if;
        end if;
end process;
 
u3 : gh_counter_integer_down -- word counter
        generic map (8)
        port map(
                clk => clk,
                rst  => rst,
                LOAD => RWC_LD,
                CE => BRC,
                D => num_bits,
                Q => R_WCOUNT
                );
 
--------------------------------------------------------
--------------------------------------------------------
 
        parity_Grst <= '1' when (R_state = R_start_bit) else
                       '0';
 
U4 : gh_parity_gen_Serial
        PORT MAP (
                clk => clk,
                rst => rst,
                srst => parity_Grst,
                SD => BRC,
                D => R_shift_reg(7),
                Q => parity);
 
 
end a;
 

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[/] [uart_fpga_slow_control/] [trunk/] [code/] [gh_uart_Rx_8bit.vhd] - Blame information for rev 20

Line No.	Rev	Author	Line
1	3	aborga	`-----------------------------------------------------------------------------`
2			`-- Filename: gh_uart_Rx_8bit.vhd`
3			`--`
4			`-- Description:`
5			`-- an 8 bit UART Rx Module`
6			`--`
7			`-- Copyright (c) 2006 by H LeFevre`
8			`-- A VHDL 16550 UART core`
9			`-- an OpenCores.org Project`
10			`-- free to use, but see documentation for conditions`
11			`--`
12			`-- Revision History:`
13			`-- Revision Date Author Comment`
14			`-- -------- ---------- --------- -----------`
15			`-- 1.0 02/18/06 H LeFevre Initial revision`
16			`-- 1.1 02/25/06 H LeFevre mod to SM, goes to idle faster`
17			`-- if no break error`
18			`-- 2.0 06/18/07 P.Azkarate Define "range" in R_WCOUNT and R_brdCOUNT signals`
19			`-----------------------------------------------------------------------------`
20			`library ieee ;`
21			`use ieee.std_logic_1164.all ;`
22
23			`entity gh_uart_Rx_8bit is`
24			`port(`
25			`clk : in std_logic; -- clock`
26			`rst : in std_logic;`
27			`BRCx16 : in std_logic; -- 16x clock enable`
28			`sRX : in std_logic;`
29			`num_bits : in integer;`
30			`Parity_EN : in std_logic;`
31			`Parity_EV : in std_logic;`
32			`Parity_ER : out std_logic;`
33			`Frame_ER : out std_logic;`
34			`Break_ITR : out std_logic;`
35			`D_RDY : out std_logic;`
36			`D : out std_logic_vector(7 downto 0)`
37			`);`
38			`end entity;`
39
40			`architecture a of gh_uart_Rx_8bit is`
41
42			`COMPONENT gh_shift_reg_se_sl is`
43			`GENERIC (size: INTEGER := 16);`
44			`PORT(`
45			`clk : IN STD_logic;`
46			`rst : IN STD_logic;`
47			`srst : IN STD_logic:='0';`
48			`SE : IN STD_logic; -- shift enable`
49			`D : IN STD_LOGIC;`
50			`Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)`
51			`);`
52			`END COMPONENT;`
53
54			`COMPONENT gh_parity_gen_Serial is`
55			`PORT(`
56			`clk : IN STD_LOGIC;`
57			`rst : IN STD_LOGIC;`
58			`srst : in STD_LOGIC;`
59			`SD : in STD_LOGIC; -- sample data pulse`
60			`D : in STD_LOGIC; -- data`
61			`Q : out STD_LOGIC`
62			`);`
63			`END COMPONENT;`
64
65			`COMPONENT gh_counter_integer_down IS`
66			`generic(max_count : integer := 8);`
67			`PORT(`
68			`clk : IN STD_LOGIC;`
69			`rst : IN STD_LOGIC;`
70			`LOAD : in STD_LOGIC; -- load D`
71			`CE : IN STD_LOGIC; -- count enable`
72			`D : in integer RANGE 0 TO max_count;`
73			`Q : out integer RANGE 0 TO max_count`
74			`);`
75			`END COMPONENT;`
76
77			`COMPONENT gh_jkff is`
78			`PORT(`
79			`clk : IN STD_logic;`
80			`rst : IN STD_logic;`
81			`J,K : IN STD_logic;`
82			`Q : OUT STD_LOGIC`
83			`);`
84			`END COMPONENT;`
85
86			`type R_StateType is (idle,R_start_bit,shift_data,R_parity,`
87			`R_stop_bit,break_err);`
88			`signal R_state, R_nstate : R_StateType;`
89
90			`signal parity : std_logic;`
91			`signal parity_Grst : std_logic;`
92			`signal RWC_LD : std_logic;`
93			`signal R_WCOUNT : integer range 0 to 15;`
94			`signal s_DATA_LD : std_logic;`
95			`signal chk_par : std_logic;`
96			`signal chk_frm : std_logic;`
97			`signal clr_brk : std_logic;`
98			`signal clr_D : std_logic;`
99			`signal s_chk_par : std_logic;`
100			`signal s_chk_frm : std_logic;`
101			`signal R_shift_reg : std_logic_vector(7 downto 0);`
102			`signal iRX : std_logic;`
103			`signal BRC : std_logic;`
104			`signal dCLK_LD : std_logic;`
105			`signal R_brdCOUNT : integer range 0 to 15;`
106			`signal iParity_ER : std_logic;`
107			`signal iFrame_ER : std_logic;`
108			`signal iBreak_ITR : std_logic;`
109			`signal iD_RDY : std_logic;`
110
111			`begin`
112
113			`----------------------------------------------`
114			`---- outputs----------------------------------`
115			`----------------------------------------------`
116			`process(CLK,rst)`
117			`begin`
118			`if (rst = '1') then`
119			`Parity_ER <= '0';`
120			`Frame_ER <= '0';`
121			`Break_ITR <= '0';`
122			`D_RDY <= '0';`
123			`elsif (rising_edge(CLK)) then`
124			`if (BRCx16 = '1') then`
125			`D_RDY <= iD_RDY;`
126			`if (iD_RDY = '1') then`
127			`Parity_ER <= iParity_ER;`
128			`Frame_ER <= iFrame_ER;`
129			`Break_ITR <= iBreak_ITR;`
130			`end if;`
131			`end if;`
132			`end if;`
133			`end process;`
134
135			`D <= R_shift_reg when (num_bits = 8) else`
136			`('0' & R_shift_reg(7 downto 1)) when (num_bits = 7) else`
137			`("00" & R_shift_reg(7 downto 2)) when (num_bits = 6) else`
138			`("000" & R_shift_reg(7 downto 3)); -- when (bits_word = 5) else`
139
140
141			`----------------------------------------------`
142
143			`dCLK_LD <= '1' when (R_state = idle) else`
144			`'0';`
145
146			`BRC <= '0' when (BRCx16 = '0') else`
147			`'1' when (R_brdCOUNT = 0) else`
148			`'0';`
149
150			`u1 : gh_counter_integer_down -- baud rate divider`
151			`generic map (15)`
152			`port map(`
153			`clk => clk,`
154			`rst => rst,`
155			`LOAD => dCLK_LD,`
156			`CE => BRCx16,`
157			`D => 14,`
158			`Q => R_brdCOUNT);`
159
160			`----------------------------------------------------------`
161
162			`U2 : gh_shift_reg_se_sl`
163			`Generic Map(8)`
164			`PORT MAP (`
165			`clk => clk,`
166			`rst => rst,`
167			`srst => clr_D,`
168			`SE => s_DATA_LD,`
169			`D => sRX,`
170			`Q => R_shift_reg);`
171
172			`-----------------------------------------------------------`
173
174			`chk_par <= s_chk_par and (((parity xor iRX) and Parity_EV)`
175			`or (((not parity) xor iRX) and (not Parity_EV)));`
176
177			`U2c : gh_jkff`
178			`PORT MAP (`
179			`clk => clk,`
180			`rst => rst,`
181			`j => chk_par,`
182			`k => dCLK_LD,`
183			`Q => iParity_ER);`
184
185			`chk_frm <= s_chk_frm and (not iRX);`
186
187			`U2d : gh_jkff`
188			`PORT MAP (`
189			`clk => clk,`
190			`rst => rst,`
191			`j => chk_frm,`
192			`k => dCLK_LD,`
193			`Q => iFrame_ER);`
194
195			`U2e : gh_jkff`
196			`PORT MAP (`
197			`clk => clk,`
198			`rst => rst,`
199			`j => clr_d,`
200			`k => clr_brk,`
201			`Q => iBreak_ITR);`
202
203			`--------------------------------------------------------------`
204			`--------------------------------------------------------------`
205
206
207			`process(R_state,BRCx16,BRC,iRX,R_WCOUNT,Parity_EN,R_brdCOUNT,iBreak_ITR)`
208			`begin`
209			`case R_state is`
210			`when idle => -- idle`
211			`iD_RDY <= '0'; s_DATA_LD <= '0'; RWC_LD <= '1';`
212			`s_chk_par <= '0'; s_chk_frm <= '0'; clr_brk <= '0';`
213			`clr_D <= '0';`
214			`if (iRX = '0') then`
215			`R_nstate <= R_start_bit;`
216			`else`
217			`R_nstate <= idle;`
218			`end if;`
219			`when R_start_bit => --`
220			`iD_RDY <= '0'; s_DATA_LD <= '0'; RWC_LD <= '1';`
221			`s_chk_par <= '0'; s_chk_frm <= '0'; clr_brk <= '0';`
222			`if (BRC = '1') then`
223			`clr_D <= '1';`
224			`R_nstate <= shift_data;`
225			`elsif ((R_brdCOUNT = 8) and (iRX = '1')) then -- false start bit detection`
226			`clr_D <= '0';`
227			`R_nstate <= idle;`
228			`else`
229			`clr_D <= '0';`
230			`R_nstate <= R_start_bit;`
231			`end if;`
232			`when shift_data => -- send data bit`
233			`iD_RDY <= '0'; RWC_LD <= '0';`
234			`s_chk_par <= '0'; s_chk_frm <= '0';`
235			`clr_D <= '0';`
236			`if (BRCx16 = '0') then`
237			`s_DATA_LD <= '0'; clr_brk <= '0';`
238			`R_nstate <= shift_data;`
239			`elsif (R_brdCOUNT = 8) then`
240			`s_DATA_LD <= '1'; clr_brk <= iRX;`
241			`R_nstate <= shift_data;`
242			`elsif ((R_WCOUNT = 1) and (R_brdCOUNT = 0) and (Parity_EN = '1')) then`
243			`s_DATA_LD <= '0'; clr_brk <= '0';`
244			`R_nstate <= R_parity;`
245			`elsif ((R_WCOUNT = 1) and (R_brdCOUNT = 0)) then`
246			`s_DATA_LD <= '0'; clr_brk <= '0';`
247			`R_nstate <= R_stop_bit;`
248			`else`
249			`s_DATA_LD <= '0'; clr_brk <= '0';`
250			`R_nstate <= shift_data;`
251			`end if;`
252			`when R_parity => -- check parity bit`
253			`iD_RDY <= '0'; s_DATA_LD <= '0';`
254			`RWC_LD <= '0'; s_chk_frm <= '0';`
255			`clr_D <= '0';`
256			`if (BRCx16 = '0') then`
257			`s_chk_par <= '0'; clr_brk <= '0';`
258			`R_nstate <= R_parity;`
259			`elsif (R_brdCOUNT = 8) then`
260			`s_chk_par <= '1'; clr_brk <= iRX;`
261			`R_nstate <= R_parity;`
262			`elsif (BRC = '1') then`
263			`s_chk_par <= '0'; clr_brk <= '0';`
264			`R_nstate <= R_stop_bit;`
265			`else`
266			`s_chk_par <= '0'; clr_brk <= '0';`
267			`R_nstate <= R_parity;`
268			`end if;`
269			`when R_stop_bit => -- check stop bit`
270			`s_DATA_LD <= '0'; RWC_LD <= '0';`
271			`s_chk_par <= '0'; clr_brk <= iRX;`
272			`clr_D <= '0';`
273			`if ((BRC = '1') and (iBreak_ITR = '1')) then`
274			`iD_RDY <= '1'; s_chk_frm <= '0';`
275			`R_nstate <= break_err;`
276			`elsif (BRC = '1') then`
277			`iD_RDY <= '1'; s_chk_frm <= '0';`
278			`R_nstate <= idle;`
279			`elsif (R_brdCOUNT = 8) then`
280			`iD_RDY <= '0'; s_chk_frm <= '1';`
281			`R_nstate <= R_stop_bit;`
282			`elsif ((R_brdCOUNT = 7) and (iBreak_ITR = '0')) then -- added 02/20/06`
283			`iD_RDY <= '1'; s_chk_frm <= '0';`
284			`R_nstate <= idle;`
285			`else`
286			`iD_RDY <= '0'; s_chk_frm <= '0';`
287			`R_nstate <= R_stop_bit;`
288			`end if;`
289			`when break_err =>`
290			`iD_RDY <= '0'; s_DATA_LD <= '0'; RWC_LD <= '0';`
291			`s_chk_par <= '0'; s_chk_frm <= '0'; clr_brk <= '0';`
292			`clr_D <= '0';`
293			`if (iRX = '1') then`
294			`R_nstate <= idle;`
295			`else`
296			`R_nstate <= break_err;`
297			`end if;`
298			`when others =>`
299			`iD_RDY <= '0'; s_DATA_LD <= '0'; RWC_LD <= '0';`
300			`s_chk_par <= '0'; s_chk_frm <= '0'; clr_brk <= '0';`
301			`clr_D <= '0';`
302			`R_nstate <= idle;`
303			`end case;`
304			`end process;`
305
306			`--`
307			`-- registers for SM`
308			`process(CLK,rst)`
309			`begin`
310			`if (rst = '1') then`
311			`iRX <= '1';`
312			`R_state <= idle;`
313			`elsif (rising_edge(CLK)) then`
314			`if (BRCx16 = '1') then`
315			`iRX <= sRX;`
316			`R_state <= R_nstate;`
317			`else`
318			`iRX <= iRX;`
319			`R_state <= R_state;`
320			`end if;`
321			`end if;`
322			`end process;`
323
324			`u3 : gh_counter_integer_down -- word counter`
325			`generic map (8)`
326			`port map(`
327			`clk => clk,`
328			`rst => rst,`
329			`LOAD => RWC_LD,`
330			`CE => BRC,`
331			`D => num_bits,`
332			`Q => R_WCOUNT`
333			`);`
334
335			`--------------------------------------------------------`
336			`--------------------------------------------------------`
337
338			`parity_Grst <= '1' when (R_state = R_start_bit) else`
339			`'0';`
340
341			`U4 : gh_parity_gen_Serial`
342			`PORT MAP (`
343			`clk => clk,`
344			`rst => rst,`
345			`srst => parity_Grst,`
346			`SD => BRC,`
347			`D => R_shift_reg(7),`
348			`Q => parity);`
349
350
351			`end a;`
352