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[/] [uart_fpga_slow_control/] [trunk/] [code/] [gh_uart_Tx_8bit.vhd] - Blame information for rev 3

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-----------------------------------------------------------------------------
--      Filename:       gh_uart_Tx_8bit.vhd
--
--      Description:
--              an 8 bit UART Tx Module
--
--      Copyright (c) 2006, 2007 by H LeFevre
--              A VHDL 16550 UART core
--              an OpenCores.org Project
--              free to use, but see documentation for conditions 
--
--      Revision        History:
--      Revision        Date            Author          Comment
--      --------        ----------      ---------       -----------
--      1.0             02/18/06        H LeFevre       Initial revision
--      1.1             02/25/06        H LeFevre       add BUSYn output
--      2.0             06/18/07        P.Azkarate  Define "range" in T_WCOUNT and x_dCOUNT signals
--      2.1             07/12/07        H LeFevre       fix a problem with 5 bit data and 1.5 stop bits
--                                                         as pointed out by Matthias Klemm
--      2.2             08/17/07        H LeFevre       add stopB to sensitivity list line 164
--                                                         as suggested by Guillaume Zin 
-----------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
 
entity gh_uart_Tx_8bit is
        port(
                clk       : in std_logic; --  clock
                rst       : in std_logic;
                xBRC      : in std_logic; -- x clock enable
                D_RYn     : in std_logic; -- data ready 
                D         : in std_logic_vector(7 downto 0);
                num_bits  : in integer:= 8; -- number of bits in transfer
                Break_CB  : in std_logic;
                stopB     : in std_logic;
                Parity_EN : in std_logic;
                Parity_EV : in std_logic;
                sTX       : out std_logic;
                BUSYn     : out std_logic;
                read      : out std_logic -- data read
                );
end entity;
 
architecture a of gh_uart_Tx_8bit is
 
COMPONENT gh_shift_reg_PL_sl is
        GENERIC (size: INTEGER := 16);
        PORT(
                clk      : IN STD_logic;
                rst      : IN STD_logic;
                LOAD     : IN STD_LOGIC;  -- load data
                SE       : IN STD_LOGIC;  -- shift enable
                D        : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
                Q        : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
                );
END COMPONENT;
 
COMPONENT gh_parity_gen_Serial is
        PORT(
                clk      : IN STD_LOGIC;
                rst      : IN STD_LOGIC;
                srst     : in STD_LOGIC;
                SD       : in STD_LOGIC; -- sample data pulse
                D        : in STD_LOGIC; -- data
                Q        : out STD_LOGIC
                );
END COMPONENT;
 
COMPONENT gh_counter_integer_down IS
        generic(max_count : integer := 8);
        PORT(
                clk      : IN STD_LOGIC;
                rst      : IN STD_LOGIC;
                LOAD     : in STD_LOGIC; -- load D
                CE       : IN STD_LOGIC; -- count enable
                D        : in integer RANGE 0 TO max_count;
                Q        : out integer RANGE 0 TO max_count
                );
END COMPONENT;
 
        type T_StateType is (idle,s_start_bit,shift_data,s_parity,
                             s_stop_bit,s_stop_bit2);
        signal T_state, T_nstate : T_StateType;
 
        signal parity      : std_logic;
        signal parity_Grst : std_logic;
        signal TWC_LD      : std_logic;
        signal TWC_CE      : std_logic;
        signal T_WCOUNT : integer range 0 to 15;
        signal D_LD_v : integer range 1 to 15;
        signal D_LD : std_logic;
        signal Trans_sr_SE : std_logic;
        signal Trans_shift_reg : std_logic_vector(7 downto 0);
        signal iTX : std_logic;
        signal BRC : std_logic;
        signal dCLK_LD : std_logic;
        signal x_dCOUNT : integer range 0 to 15;
 
begin
 
----------------------------------------------
---- outputs----------------------------------
----------------------------------------------
 
        BUSYn <= '1' when (T_state = idle) else
                 '0';
 
        read <= D_LD; -- read a data word
 
----------------------------------------------
 
        dCLK_LD <= '1' when ((num_bits = 5) and (stopB = '1')
                       and (T_state = s_stop_bit2) and (x_dCOUNT = 7)) else
                   '0' when (D_RYn = '0') else
                   '0' when (T_state /= idle) else
                   '1';
 
        D_LD_v <= 15 when (T_state = s_stop_bit2) else
                   1;
 
        BRC <= '0' when (xBRC = '0') else
               '1' when (x_dCOUNT = 0) else
               '0';
 
 
u1 : gh_counter_integer_down -- baud rate divider
        generic map (15)
        port map(
                clk => clk,
                rst  => rst,
                LOAD => dCLK_LD,
                CE => xBRC,
                D => D_LD_v,
                Q => x_dCOUNT);
 
U2 : gh_shift_reg_PL_sl
        Generic Map(8)
        PORT MAP (
                clk => clk,
                rst => rst,
                LOAD => D_LD,
                SE => Trans_sr_SE,
                D => D,
                Q => Trans_shift_reg);
 
--------------------------------------------------------------
--------------------------------------------------------------
 
process (clk,rst)
begin
        if (rst = '1') then
                sTX <= '1';
        elsif (rising_edge(clk)) then
                sTX <= iTX and (not Break_CB);
        end if;
end process ;
 
        iTX <= '0' when (T_state = s_start_bit) else -- send start bit
                Trans_shift_reg(0) when (T_state = shift_data) else -- send data
                parity when ((Parity_EV = '1') and (T_state = s_parity)) else
                (not parity) when (T_state = s_parity) else
                '1'; -- idle, stop bit
 
process(T_state,D_RYn,BRC,T_WCOUNT,Parity_EN,num_bits,x_dCOUNT,stopB)
begin
        case T_state is
                when idle => -- idle  
                        TWC_CE <= '0';
                        if ((D_RYn = '0') and (BRC = '1')) then
                                D_LD <= '1'; Trans_sr_SE <= '0';
                                TWC_LD <= '0';
                                T_nstate <= s_start_bit;
                        else
                                D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= idle;
                        end if;
                when s_start_bit => -- fifo is read, send start bit
                        TWC_CE <= '0';
                        if (BRC = '1') then
                                D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '1';
                                T_nstate <= shift_data;
                        else
                                D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= s_start_bit;
                        end if;
                when shift_data => -- send data bit
                        if (BRC = '0') then
                                D_LD <= '0'; Trans_sr_SE <= '0';
                                TWC_LD <= '0'; TWC_CE <= '0';
                                T_nstate <= shift_data;
                        elsif ((T_WCOUNT = 1) and (Parity_EN = '1')) then
                                D_LD <= '0'; Trans_sr_SE <= '0';
                                TWC_LD <= '0'; TWC_CE <= '1';
                                T_nstate <= s_parity;
                        elsif (T_WCOUNT = 1) then
                                D_LD <= '0'; Trans_sr_SE <= '0';
                                TWC_LD <= '0'; TWC_CE <= '1';
                                T_nstate <= s_stop_bit;
                        else
                                D_LD <= '0'; Trans_sr_SE <= '1';
                                TWC_LD <= '0'; TWC_CE <= '1';
                                T_nstate <= shift_data;
                        end if;
                when s_parity => -- send parity bit
                        TWC_CE <= '0';
                        if (BRC = '1') then
                                D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= s_stop_bit;
                        else
                                D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= s_parity;
                        end if;
                when s_stop_bit => -- send stop bit
                        TWC_CE <= '0';
                        if (BRC = '0') then
                                D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= s_stop_bit;
                        elsif (stopB = '1') then
                                D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= s_stop_bit2;
                        elsif (D_RYn = '0') then
                                D_LD <= '1'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= s_start_bit;
                        else
                                D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= idle;
                        end if;
                when s_stop_bit2 => -- send stop bit 
                        TWC_CE <= '0';
                        if ((D_RYn = '0') and (BRC = '1')) then
                                D_LD <= '1'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= s_start_bit;
                        elsif (BRC = '1') then
                                D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= idle;
                        elsif ((num_bits = 5) and (x_dCOUNT = 7) and (D_RYn = '0')) then
                                D_LD <= '1'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= s_start_bit;
                        elsif ((num_bits = 5) and (x_dCOUNT = 7)) then
                                D_LD <= '1'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= idle;
                        else
                                D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';
                                T_nstate <= s_stop_bit2;
                        end if;
                when others =>
                        D_LD <= '0'; Trans_sr_SE <= '0';
                        TWC_LD <= '0'; TWC_CE <= '0';
                        T_nstate <= idle;
        end case;
end process;
 
--
-- registers for SM
process(CLK,rst)
begin
        if (rst = '1') then
                T_state <= idle;
        elsif (rising_edge(CLK)) then
                T_state <= T_nstate;
        end if;
end process;
 
u3 : gh_counter_integer_down -- word counter
        generic map (8)
        port map(
                clk => clk,
                rst  => rst,
                LOAD => TWC_LD,
                CE => TWC_CE,
                D => num_bits,
                Q => T_WCOUNT
                );
 
--------------------------------------------------------
--------------------------------------------------------
 
        parity_Grst <= '1' when (T_state = s_start_bit) else
                       '0';
 
U4 : gh_parity_gen_Serial
        PORT MAP (
                clk => clk,
                rst => rst,
                srst => parity_Grst,
                SD => BRC,
                D => Trans_shift_reg(0),
                Q => parity);
 
 
end a;
 

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[/] [uart_fpga_slow_control/] [trunk/] [code/] [gh_uart_Tx_8bit.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	aborga	`-----------------------------------------------------------------------------`
2			`-- Filename: gh_uart_Tx_8bit.vhd`
3			`--`
4			`-- Description:`
5			`-- an 8 bit UART Tx Module`
6			`--`
7			`-- Copyright (c) 2006, 2007 by H LeFevre`
8			`-- A VHDL 16550 UART core`
9			`-- an OpenCores.org Project`
10			`-- free to use, but see documentation for conditions`
11			`--`
12			`-- Revision History:`
13			`-- Revision Date Author Comment`
14			`-- -------- ---------- --------- -----------`
15			`-- 1.0 02/18/06 H LeFevre Initial revision`
16			`-- 1.1 02/25/06 H LeFevre add BUSYn output`
17			`-- 2.0 06/18/07 P.Azkarate Define "range" in T_WCOUNT and x_dCOUNT signals`
18			`-- 2.1 07/12/07 H LeFevre fix a problem with 5 bit data and 1.5 stop bits`
19			`-- as pointed out by Matthias Klemm`
20			`-- 2.2 08/17/07 H LeFevre add stopB to sensitivity list line 164`
21			`-- as suggested by Guillaume Zin`
22			`-----------------------------------------------------------------------------`
23			`library ieee ;`
24			`use ieee.std_logic_1164.all ;`
25
26			`entity gh_uart_Tx_8bit is`
27			`port(`
28			`clk : in std_logic; -- clock`
29			`rst : in std_logic;`
30			`xBRC : in std_logic; -- x clock enable`
31			`D_RYn : in std_logic; -- data ready`
32			`D : in std_logic_vector(7 downto 0);`
33			`num_bits : in integer:= 8; -- number of bits in transfer`
34			`Break_CB : in std_logic;`
35			`stopB : in std_logic;`
36			`Parity_EN : in std_logic;`
37			`Parity_EV : in std_logic;`
38			`sTX : out std_logic;`
39			`BUSYn : out std_logic;`
40			`read : out std_logic -- data read`
41			`);`
42			`end entity;`
43
44			`architecture a of gh_uart_Tx_8bit is`
45
46			`COMPONENT gh_shift_reg_PL_sl is`
47			`GENERIC (size: INTEGER := 16);`
48			`PORT(`
49			`clk : IN STD_logic;`
50			`rst : IN STD_logic;`
51			`LOAD : IN STD_LOGIC; -- load data`
52			`SE : IN STD_LOGIC; -- shift enable`
53			`D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);`
54			`Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)`
55			`);`
56			`END COMPONENT;`
57
58			`COMPONENT gh_parity_gen_Serial is`
59			`PORT(`
60			`clk : IN STD_LOGIC;`
61			`rst : IN STD_LOGIC;`
62			`srst : in STD_LOGIC;`
63			`SD : in STD_LOGIC; -- sample data pulse`
64			`D : in STD_LOGIC; -- data`
65			`Q : out STD_LOGIC`
66			`);`
67			`END COMPONENT;`
68
69			`COMPONENT gh_counter_integer_down IS`
70			`generic(max_count : integer := 8);`
71			`PORT(`
72			`clk : IN STD_LOGIC;`
73			`rst : IN STD_LOGIC;`
74			`LOAD : in STD_LOGIC; -- load D`
75			`CE : IN STD_LOGIC; -- count enable`
76			`D : in integer RANGE 0 TO max_count;`
77			`Q : out integer RANGE 0 TO max_count`
78			`);`
79			`END COMPONENT;`
80
81			`type T_StateType is (idle,s_start_bit,shift_data,s_parity,`
82			`s_stop_bit,s_stop_bit2);`
83			`signal T_state, T_nstate : T_StateType;`
84
85			`signal parity : std_logic;`
86			`signal parity_Grst : std_logic;`
87			`signal TWC_LD : std_logic;`
88			`signal TWC_CE : std_logic;`
89			`signal T_WCOUNT : integer range 0 to 15;`
90			`signal D_LD_v : integer range 1 to 15;`
91			`signal D_LD : std_logic;`
92			`signal Trans_sr_SE : std_logic;`
93			`signal Trans_shift_reg : std_logic_vector(7 downto 0);`
94			`signal iTX : std_logic;`
95			`signal BRC : std_logic;`
96			`signal dCLK_LD : std_logic;`
97			`signal x_dCOUNT : integer range 0 to 15;`
98
99			`begin`
100
101			`----------------------------------------------`
102			`---- outputs----------------------------------`
103			`----------------------------------------------`
104
105			`BUSYn <= '1' when (T_state = idle) else`
106			`'0';`
107
108			`read <= D_LD; -- read a data word`
109
110			`----------------------------------------------`
111
112			`dCLK_LD <= '1' when ((num_bits = 5) and (stopB = '1')`
113			`and (T_state = s_stop_bit2) and (x_dCOUNT = 7)) else`
114			`'0' when (D_RYn = '0') else`
115			`'0' when (T_state /= idle) else`
116			`'1';`
117
118			`D_LD_v <= 15 when (T_state = s_stop_bit2) else`
119			`1;`
120
121			`BRC <= '0' when (xBRC = '0') else`
122			`'1' when (x_dCOUNT = 0) else`
123			`'0';`
124
125
126			`u1 : gh_counter_integer_down -- baud rate divider`
127			`generic map (15)`
128			`port map(`
129			`clk => clk,`
130			`rst => rst,`
131			`LOAD => dCLK_LD,`
132			`CE => xBRC,`
133			`D => D_LD_v,`
134			`Q => x_dCOUNT);`
135
136			`U2 : gh_shift_reg_PL_sl`
137			`Generic Map(8)`
138			`PORT MAP (`
139			`clk => clk,`
140			`rst => rst,`
141			`LOAD => D_LD,`
142			`SE => Trans_sr_SE,`
143			`D => D,`
144			`Q => Trans_shift_reg);`
145
146			`--------------------------------------------------------------`
147			`--------------------------------------------------------------`
148
149			`process (clk,rst)`
150			`begin`
151			`if (rst = '1') then`
152			`sTX <= '1';`
153			`elsif (rising_edge(clk)) then`
154			`sTX <= iTX and (not Break_CB);`
155			`end if;`
156			`end process ;`
157
158			`iTX <= '0' when (T_state = s_start_bit) else -- send start bit`
159			`Trans_shift_reg(0) when (T_state = shift_data) else -- send data`
160			`parity when ((Parity_EV = '1') and (T_state = s_parity)) else`
161			`(not parity) when (T_state = s_parity) else`
162			`'1'; -- idle, stop bit`
163
164			`process(T_state,D_RYn,BRC,T_WCOUNT,Parity_EN,num_bits,x_dCOUNT,stopB)`
165			`begin`
166			`case T_state is`
167			`when idle => -- idle`
168			`TWC_CE <= '0';`
169			`if ((D_RYn = '0') and (BRC = '1')) then`
170			`D_LD <= '1'; Trans_sr_SE <= '0';`
171			`TWC_LD <= '0';`
172			`T_nstate <= s_start_bit;`
173			`else`
174			`D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
175			`T_nstate <= idle;`
176			`end if;`
177			`when s_start_bit => -- fifo is read, send start bit`
178			`TWC_CE <= '0';`
179			`if (BRC = '1') then`
180			`D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '1';`
181			`T_nstate <= shift_data;`
182			`else`
183			`D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
184			`T_nstate <= s_start_bit;`
185			`end if;`
186			`when shift_data => -- send data bit`
187			`if (BRC = '0') then`
188			`D_LD <= '0'; Trans_sr_SE <= '0';`
189			`TWC_LD <= '0'; TWC_CE <= '0';`
190			`T_nstate <= shift_data;`
191			`elsif ((T_WCOUNT = 1) and (Parity_EN = '1')) then`
192			`D_LD <= '0'; Trans_sr_SE <= '0';`
193			`TWC_LD <= '0'; TWC_CE <= '1';`
194			`T_nstate <= s_parity;`
195			`elsif (T_WCOUNT = 1) then`
196			`D_LD <= '0'; Trans_sr_SE <= '0';`
197			`TWC_LD <= '0'; TWC_CE <= '1';`
198			`T_nstate <= s_stop_bit;`
199			`else`
200			`D_LD <= '0'; Trans_sr_SE <= '1';`
201			`TWC_LD <= '0'; TWC_CE <= '1';`
202			`T_nstate <= shift_data;`
203			`end if;`
204			`when s_parity => -- send parity bit`
205			`TWC_CE <= '0';`
206			`if (BRC = '1') then`
207			`D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
208			`T_nstate <= s_stop_bit;`
209			`else`
210			`D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
211			`T_nstate <= s_parity;`
212			`end if;`
213			`when s_stop_bit => -- send stop bit`
214			`TWC_CE <= '0';`
215			`if (BRC = '0') then`
216			`D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
217			`T_nstate <= s_stop_bit;`
218			`elsif (stopB = '1') then`
219			`D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
220			`T_nstate <= s_stop_bit2;`
221			`elsif (D_RYn = '0') then`
222			`D_LD <= '1'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
223			`T_nstate <= s_start_bit;`
224			`else`
225			`D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
226			`T_nstate <= idle;`
227			`end if;`
228			`when s_stop_bit2 => -- send stop bit`
229			`TWC_CE <= '0';`
230			`if ((D_RYn = '0') and (BRC = '1')) then`
231			`D_LD <= '1'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
232			`T_nstate <= s_start_bit;`
233			`elsif (BRC = '1') then`
234			`D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
235			`T_nstate <= idle;`
236			`elsif ((num_bits = 5) and (x_dCOUNT = 7) and (D_RYn = '0')) then`
237			`D_LD <= '1'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
238			`T_nstate <= s_start_bit;`
239			`elsif ((num_bits = 5) and (x_dCOUNT = 7)) then`
240			`D_LD <= '1'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
241			`T_nstate <= idle;`
242			`else`
243			`D_LD <= '0'; Trans_sr_SE <= '0'; TWC_LD <= '0';`
244			`T_nstate <= s_stop_bit2;`
245			`end if;`
246			`when others =>`
247			`D_LD <= '0'; Trans_sr_SE <= '0';`
248			`TWC_LD <= '0'; TWC_CE <= '0';`
249			`T_nstate <= idle;`
250			`end case;`
251			`end process;`
252
253			`--`
254			`-- registers for SM`
255			`process(CLK,rst)`
256			`begin`
257			`if (rst = '1') then`
258			`T_state <= idle;`
259			`elsif (rising_edge(CLK)) then`
260			`T_state <= T_nstate;`
261			`end if;`
262			`end process;`
263
264			`u3 : gh_counter_integer_down -- word counter`
265			`generic map (8)`
266			`port map(`
267			`clk => clk,`
268			`rst => rst,`
269			`LOAD => TWC_LD,`
270			`CE => TWC_CE,`
271			`D => num_bits,`
272			`Q => T_WCOUNT`
273			`);`
274
275			`--------------------------------------------------------`
276			`--------------------------------------------------------`
277
278			`parity_Grst <= '1' when (T_state = s_start_bit) else`
279			`'0';`
280
281			`U4 : gh_parity_gen_Serial`
282			`PORT MAP (`
283			`clk => clk,`
284			`rst => rst,`
285			`srst => parity_Grst,`
286			`SD => BRC,`
287			`D => Trans_shift_reg(0),`
288			`Q => parity);`
289
290
291			`end a;`
292