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[/] [uart_fpga_slow_control/] [trunk/] [code/] [library/] [gh_baud_rate_gen.vhd] - Blame information for rev 3

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-----------------------------------------------------------------------------
--      Filename:       gh_baud_rate_gen.vhd
--
--      Description:
--              a 16 bit baud rate generator
--
--      Copyright (c) 2005 by George Huber 
--              an OpenCores.org Project
--              free to use, but see documentation for conditions 
--
--      Revision        History:
--      Revision        Date            Author          Comment
--      --------        ----------      ---------       -----------
--      1.0             01/28/06        H LeFevre       Initial revision
--      2.0             02/04/06        H LeFevre       reload counter with register load
--      2.1             04/10/06        H LeFevre       Fix error in rCLK
--
-----------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
 
entity gh_baud_rate_gen is
        port(
                clk     : in std_logic;
                BR_clk  : in std_logic;
                rst     : in std_logic;
                WR      : in std_logic;
                BE      : in std_logic_vector (1 downto 0); -- byte enable
                D       : in std_logic_vector (15 downto 0);
                RD      : out std_logic_vector (15 downto 0);
                rCE     : out std_logic;
                rCLK    : out std_logic
                );
end entity;
 
architecture a of gh_baud_rate_gen is
 
COMPONENT gh_register_ce is
        GENERIC (size: INTEGER := 8);
        PORT(
                clk : IN                STD_LOGIC;
                rst : IN                STD_LOGIC;
                CE  : IN                STD_LOGIC; -- clock enable
                D   : IN                STD_LOGIC_VECTOR(size-1 DOWNTO 0);
                Q   : OUT               STD_LOGIC_VECTOR(size-1 DOWNTO 0)
                );
END COMPONENT;
 
COMPONENT gh_counter_down_ce_ld is
        GENERIC (size: INTEGER :=8);
        PORT(
                CLK   : IN      STD_LOGIC;
                rst   : IN      STD_LOGIC;
                LOAD  : IN      STD_LOGIC;
                CE    : IN      STD_LOGIC;
                D     : IN  STD_LOGIC_VECTOR(size-1 DOWNTO 0);
                Q     : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
        );
END COMPONENT;
 
        signal UB_LD   : std_logic;
        signal LB_LD   : std_logic;
        signal rate    : std_logic_vector(15 downto 0);
        signal C_LD    : std_logic;
        signal C_CE    : std_logic;
        signal irLD    : std_logic;     -- added 02/04/06
        signal rLD     : std_logic; -- added 02/04/06
        signal count   : std_logic_vector(15 downto 0);
 
begin
 
        rCE <= '1' when (count = x"01") else
               '0';
 
process(BR_clk,rst)
begin
        if (rst = '1') then
                rCLK <= '0';
                rLD <= '0';
        elsif (rising_edge(BR_CLK)) then
                rLD <= irLD;
                if (count > ('0' & (rate(15 downto 1)))) then -- fixed 04/10/06
                        rCLK <= '1';
                else
                        rCLK <= '0';
                end if;
        end if;
end process;
 
        RD <= rate;
 
----------------------------------------------
----------------------------------------------  
 
        UB_LD <= '0' when (WR = '0') else
                 '0' when (BE(1) = '0') else
                 '1';
 
u1 : gh_register_ce
        generic map (8)
        port map(
                clk => clk,
                rst => rst,
                ce => UB_LD,
                D => d(15 downto 8),
                Q => rate(15 downto 8)
                );
 
        LB_LD <= '0' when (WR = '0') else
                 '0' when (BE(0) = '0') else
                 '1';
 
u2 : gh_register_ce
        generic map (8)
        port map(
                clk => clk,
                rst => rst,
                ce => LB_LD,
                D => d(7 downto 0),
                Q => rate(7 downto 0)
                );
 
------------------------------------------------------------
------------ baud rate counter -----------------------------
------------------------------------------------------------
 
process(clk,rst)
begin
        if (rst = '1') then
                irLD <= '0';
        elsif (rising_edge(CLK)) then
                if ((UB_LD or LB_LD) = '1') then
                        irLD <= '1';
                elsif (rLD = '1') then
                        irLD <= '0';
                end if;
        end if;
end process;
 
        C_LD <= '1' when (count = x"01") else
                '1' when (rLD = '1') else
                '0';
 
        C_CE <= '1' when (rate > x"01") else
                '0';
 
U3 : gh_counter_down_ce_ld
        Generic Map (size => 16)
        PORT MAP (
                clk => BR_clk,
                rst => rst,
                LOAD => C_LD,
                CE => C_CE,
                D => rate,
                Q => count);
 
end a;
 

Line No.	Rev	Author	Line
1	3	aborga	`-----------------------------------------------------------------------------`
2			`-- Filename: gh_baud_rate_gen.vhd`
3			`--`
4			`-- Description:`
5			`-- a 16 bit baud rate generator`
6			`--`
7			`-- Copyright (c) 2005 by George Huber`
8			`-- an OpenCores.org Project`
9			`-- free to use, but see documentation for conditions`
10			`--`
11			`-- Revision History:`
12			`-- Revision Date Author Comment`
13			`-- -------- ---------- --------- -----------`
14			`-- 1.0 01/28/06 H LeFevre Initial revision`
15			`-- 2.0 02/04/06 H LeFevre reload counter with register load`
16			`-- 2.1 04/10/06 H LeFevre Fix error in rCLK`
17			`--`
18			`-----------------------------------------------------------------------------`
19			`library ieee ;`
20			`use ieee.std_logic_1164.all ;`
21			`use ieee.std_logic_arith.all ;`
22			`use ieee.std_logic_unsigned.all ;`
23
24			`entity gh_baud_rate_gen is`
25			`port(`
26			`clk : in std_logic;`
27			`BR_clk : in std_logic;`
28			`rst : in std_logic;`
29			`WR : in std_logic;`
30			`BE : in std_logic_vector (1 downto 0); -- byte enable`
31			`D : in std_logic_vector (15 downto 0);`
32			`RD : out std_logic_vector (15 downto 0);`
33			`rCE : out std_logic;`
34			`rCLK : out std_logic`
35			`);`
36			`end entity;`
37
38			`architecture a of gh_baud_rate_gen is`
39
40			`COMPONENT gh_register_ce is`
41			`GENERIC (size: INTEGER := 8);`
42			`PORT(`
43			`clk : IN STD_LOGIC;`
44			`rst : IN STD_LOGIC;`
45			`CE : IN STD_LOGIC; -- clock enable`
46			`D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);`
47			`Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)`
48			`);`
49			`END COMPONENT;`
50
51			`COMPONENT gh_counter_down_ce_ld is`
52			`GENERIC (size: INTEGER :=8);`
53			`PORT(`
54			`CLK : IN STD_LOGIC;`
55			`rst : IN STD_LOGIC;`
56			`LOAD : IN STD_LOGIC;`
57			`CE : IN STD_LOGIC;`
58			`D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);`
59			`Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)`
60			`);`
61			`END COMPONENT;`
62
63			`signal UB_LD : std_logic;`
64			`signal LB_LD : std_logic;`
65			`signal rate : std_logic_vector(15 downto 0);`
66			`signal C_LD : std_logic;`
67			`signal C_CE : std_logic;`
68			`signal irLD : std_logic; -- added 02/04/06`
69			`signal rLD : std_logic; -- added 02/04/06`
70			`signal count : std_logic_vector(15 downto 0);`
71
72			`begin`
73
74			`rCE <= '1' when (count = x"01") else`
75			`'0';`
76
77			`process(BR_clk,rst)`
78			`begin`
79			`if (rst = '1') then`
80			`rCLK <= '0';`
81			`rLD <= '0';`
82			`elsif (rising_edge(BR_CLK)) then`
83			`rLD <= irLD;`
84			`if (count > ('0' & (rate(15 downto 1)))) then -- fixed 04/10/06`
85			`rCLK <= '1';`
86			`else`
87			`rCLK <= '0';`
88			`end if;`
89			`end if;`
90			`end process;`
91
92			`RD <= rate;`
93
94			`----------------------------------------------`
95			`----------------------------------------------`
96
97			`UB_LD <= '0' when (WR = '0') else`
98			`'0' when (BE(1) = '0') else`
99			`'1';`
100
101			`u1 : gh_register_ce`
102			`generic map (8)`
103			`port map(`
104			`clk => clk,`
105			`rst => rst,`
106			`ce => UB_LD,`
107			`D => d(15 downto 8),`
108			`Q => rate(15 downto 8)`
109			`);`
110
111			`LB_LD <= '0' when (WR = '0') else`
112			`'0' when (BE(0) = '0') else`
113			`'1';`
114
115			`u2 : gh_register_ce`
116			`generic map (8)`
117			`port map(`
118			`clk => clk,`
119			`rst => rst,`
120			`ce => LB_LD,`
121			`D => d(7 downto 0),`
122			`Q => rate(7 downto 0)`
123			`);`
124
125			`------------------------------------------------------------`
126			`------------ baud rate counter -----------------------------`
127			`------------------------------------------------------------`
128
129			`process(clk,rst)`
130			`begin`
131			`if (rst = '1') then`
132			`irLD <= '0';`
133			`elsif (rising_edge(CLK)) then`
134			`if ((UB_LD or LB_LD) = '1') then`
135			`irLD <= '1';`
136			`elsif (rLD = '1') then`
137			`irLD <= '0';`
138			`end if;`
139			`end if;`
140			`end process;`
141
142			`C_LD <= '1' when (count = x"01") else`
143			`'1' when (rLD = '1') else`
144			`'0';`
145
146			`C_CE <= '1' when (rate > x"01") else`
147			`'0';`
148
149			`U3 : gh_counter_down_ce_ld`
150			`Generic Map (size => 16)`
151			`PORT MAP (`
152			`clk => BR_clk,`
153			`rst => rst,`
154			`LOAD => C_LD,`
155			`CE => C_CE,`
156			`D => rate,`
157			`Q => count);`
158
159			`end a;`
160

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[/] [uart_fpga_slow_control/] [trunk/] [code/] [library/] [gh_baud_rate_gen.vhd] - Blame information for rev 3