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[/] [uart_fpga_slow_control/] [trunk/] [documents/] [HardwareDescription.txt] - Blame information for rev 31

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1 31 aborga
Remember to add a voltage translator buffer:
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!! none of the FPGAs on the market are 12V tolerant !!
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~ use a MAX3224 chip for example
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Timing
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In case an external clock is needed to drive the UART:
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~ use a 29.4912 MHz Oscillator like ASV-29.4912MHZ-EJ-T

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