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[/] [uart_fpga_slow_control/] [trunk/] [documents/] [OpenCores_description.txt] - Blame information for rev 29

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Control the activity and status of your FPGA by targeting a memory mapped space inside it.
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Based on:
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-- elements from the GH libraries ( http://opencores.org/project,gh_vhdl_library )
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-- HLeFevre UART project ( http://opencores.org/project,a_vhd_16550_uart )
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Simple three steps access procedure:
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-- Write words of 2 bytes address and 4 bytes data.
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-- Ask for an update targeting the update register (default 0x8000 0x00000000)
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-- Read words of 2 bytes address and 4 bytes data.
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The code comes plug and play:
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* the whole uart initialization process is automatic
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* 4 pins interface to the outsideworld: serial tx, serial rx, uart clock, hard reset
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* up to 2^16 32 bit wide registers for user logic control and monitor
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Declare the registers you want to read and write in the top level entity. the rest will be handled automatically by FSMs.
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Almost no documentation is required.
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no knowledge of the internals of the core required.
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The top entity is self-explanatory.
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Remotely control the logic from a PC:
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~ Under Windows use RealTerm to simply send and receive HEX commands ( http://realterm.sourceforge.net/ ).
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~ Simple Python script to drive the uart via command line in linux (see software details tab above).
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~ TCP/IP to UART bridging is just around the corner using inexpensive external devices.
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crossplatform compatible (tested on Xilinx Virtex-5 and Altera Stratix-4 devices). Tested up to 1 Mbps with a 29.4912 MHz oscillator.
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## Feeback:
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