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[/] [uart_observer/] [trunk/] [verilog/] [uart_observer.v] - Blame information for rev 2

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1 2 audriusa
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: none 
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// Engineer: Audrius Meskauskas
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// 
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// Create Date: 03/10/2018 09:31:52 PM
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// Design Name:  UART observer
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// Module Name: uart_observer
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// 
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//////////////////////////////////////////////////////////////////////////////////
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module uart_observer (
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// clock, tested with 90 MHZ clock
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  input clk,
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  // The array of observables.
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  input wire [BITS-1:0] observables,
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  // UART  
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  input CTS, // "clear to send"
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  output TXD, // Serial data output
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  output RTS  // Request to send, this UART does not send all the time.
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);
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 // The number of bits to show in the output
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 parameter  BITS = 128;
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// Clock frequency Hz
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 parameter CLOCK_FREQ = 90_000_000;
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 // Serial port speed baud
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 parameter BAUDS = 921600; // 9600;
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 parameter DIV_MAX = CLOCK_FREQ/BAUDS;
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 parameter DIV_BITS = 32; // bits in frequency divider
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 parameter N = 10;
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 parameter H = N-1; // Highest bit
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 // RAM buffer to transfer from 
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 parameter RAM_LENGTH = 3 + 3 + 11*BITS;
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 reg [7:0] mem [RAM_LENGTH - 1:0];
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 // RAM index of value currently being sent
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 reg [7:0] ram_addr = 0;
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 // Divider to 1 baud                          
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 reg [DIV_BITS:0] divider = 0;
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 // Internal phase counter to track what we are doing
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 reg [4:0] phase = 0;
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 // The output data connector
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 wire s_out;
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 // The output "sending" connector
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 reg sending = 0;
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 // Main sending register
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 reg [H:0] r_reg;
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 wire [H:0] r_next;
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 wire [H:0] r_sendit;
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 // The byte being written
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 reg [7:0] out; // = 8'b0011_0001;
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 // New data from the buffer (start bit on the right)
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 assign r_sendit = { 1'b1, out, 1'b0 };
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 // Shifted value
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 assign r_next = { 1'b0, r_reg [H:1] };
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 // Out output (lowest bit)
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 assign s_out = r_reg[0];
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 reg [BITS-1:0] observables_reg;
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 reg [BITS-1:0] observables_prev = 32'hFFFFF;
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 parameter [7:0] ESC = 8'b0001_1011;
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 integer b;
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 integer p;
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 integer bytes_in_row;
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 // Initialize RAM with content to send
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 initial
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   begin
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     // See http://www.termsys.demon.co.uk/vtansi.htm
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     // Top left corner (ESC [ H)
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     mem[0] <= ESC; // ESC
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     mem[1] <= "["; // [
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     mem[2] <= "H"; // H
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     /*
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     for (b = 3; b <= 3 + BITS*11; b = b + 11)
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       render_byte(b);
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     */
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     bytes_in_row = 0;
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     p = 3;
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     for (b = 0; b < BITS/8; b = b + 1)
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       begin
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         if (bytes_in_row == 3)
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           begin
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             render_byte(p, 8'h0d, 8'h0a);
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             bytes_in_row = 0;
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           end
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         else
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           begin
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             render_byte(p, " ", " ");
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             bytes_in_row = bytes_in_row + 1;
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           end;
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         p = p + 11;
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       end
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     // Erase till end of screen (ESC [ J)
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     mem[p] <= ESC; // ESC
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     mem[p + 1] <= "["; // [
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     mem[p + 2] <= "J"; // J    
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   end
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// Prepare initial data to render the byte (11 bytes - tetrad spacer and doubled byte spacer)
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// The last two bytes (parameters) are inter-byte spacer that may be row separator.
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task render_byte;
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   input integer p;
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   input reg [7:0] b1;
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   input reg [7:0] b2;
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   begin
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     // (first tetrad 0 .. 3)
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     mem[p + 4] <= " "; // Space separator
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     // (second tetrad 5 .. 8)       
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     // (Two spaces)    
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     mem[p + 9] <= b1; // space
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     mem[p + 10] <= b2; // space
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   end
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endtask
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 // Convert a bit to ASCII representation of it.  
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 function [7:0] ascii;
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    input x;
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    begin
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      if (x==0)
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        ascii = "."; // dot
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      else
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        ascii = "1";
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    end
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 endfunction
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 // Loop over all 32 bits, populating memory cells with translated values.  
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 task update_ram;
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   integer k;
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   integer b;
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   integer ib; // bit
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   integer p; // memory pointer
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   begin
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     ib = 0;
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     p = 3; // Leave place for the header
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     for (b = 0; b < BITS / 8; b = b + 1)
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       begin
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         for (k = 0; k < 4; k = k + 1)
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           begin
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             mem[p] = ascii(observables_reg[ib]);
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             ib = ib + 1;
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             p = p + 1;
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           end
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         p = p + 1; // spacer between tetrads
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         for (k = 4; k < 8; k = k + 1)
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           begin
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             mem[p] = ascii(observables_reg[ib]);
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             ib = ib + 1;
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             p = p + 1;
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           end
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         p = p + 2; // spacer between bytes  
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       end
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   end
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 endtask
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 // Populate the register 'out' with next data to write  
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 task next_data;
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   begin
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     out = mem[ram_addr];
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     ram_addr = ram_addr + 1;
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     if (ram_addr == RAM_LENGTH)
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       ram_addr = 0;
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   end
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 endtask
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 // Increement the "phase" variable that loops over 0-1-2-3-4-5-6-7-8-9-0
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 task increment_phase;
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   begin
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     if (phase == 9)
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       begin
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         phase <= 0;
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         observables_prev <= observables_reg;
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       end
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     else
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       phase <= phase + 1;
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   end
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 endtask
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 always @(posedge clk)
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 begin :cl
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   // Need 781.25 (90000000 Hz to 115200 Hz)
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   if (divider > DIV_MAX)
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     begin
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       if (phase == 0 && ram_addr == 0)
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         begin
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           observables_reg = observables;
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           if (observables_prev == observables_reg)
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             begin
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               r_reg <= 10'b1_1111_1111_1;
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               divider <= 0;
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               sending <= 0;
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               disable cl;
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             end
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           else
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             update_ram();
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         end
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       sending = 1;
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       if (CTS == 0)
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         begin
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           // Not clear to send, keep inactive line high
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           r_reg <= 10'b1_1111_1111_1;
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           phase <= 0;
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           divider <= 0;
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           disable cl;
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         end;
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       if (phase == 0)
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         begin
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            next_data();
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            r_reg = r_sendit;
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         end
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       else
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         begin
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           r_reg <= r_next;
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         end;
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       increment_phase();
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       divider = 0;
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     end
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     divider = divider + 1;
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 end
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 assign TXD = s_out;
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 assign RTS = sending;
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endmodule
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