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[/] [uart_observer/] [trunk/] [verilog/] [uart_observer_demonstrator.v] - Blame information for rev 5

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1 3 audriusa
/**
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* Demonstrates the functionality of the UART observer. Reads 64 bits from the terminal keyboard.
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*/
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module uart_observer_demonstrator (
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  input USB_UART_TX_FPGA_RX_LS,
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  input USB_UART_CTS_I_B_LS,
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  input CLK_I,
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  input GPIO_SW_E,
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  input GPIO_SW_W,
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  input GPIO_SW_S,
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  input GPIO_SW_N,
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  input GPIO_SW_C,
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  input GPIO_DIP_SW0,
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  input GPIO_DIP_SW1,
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  input GPIO_DIP_SW2,
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  input GPIO_DIP_SW3,
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  output GPIO_LED_0,
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  output GPIO_LED_1,
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  output GPIO_LED_2,
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  output GPIO_LED_3,
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  output GPIO_LED_4,
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  output GPIO_LED_5,
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  output GPIO_LED_6,
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  output GPIO_LED_7,
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  output USB_UART_RX_FPGA_TX_LS,
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  output USB_UART_RTS_O_B_LS
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);
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 // 32 bits we observe.
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 wire [31:0] observables;
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 uart_receiver #(.CLOCK_FREQ (90_000_000), .BAUDS(921600), .BITS(32) )
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 UR(
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  // Clock
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  .CLK_I(CLK_I),
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  // Values to observer
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  .DAT_O(observables),
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  // UART
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  .RXD(USB_UART_TX_FPGA_RX_LS), // data  
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  .CTR(USB_UART_CTS_I_B_LS)     // clear to receive
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 );
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 uart_observer #(.CLOCK_FREQ (90_000_000), .BAUDS(921600), .BITS(32) )
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 U0(
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  // Clock
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  .CLK_I(CLK_I),
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  // Values to observer
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  .DAT_I(observables),
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  // UART
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  .TXD(USB_UART_RX_FPGA_TX_LS), // data  
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  .RTS(USB_UART_RTS_O_B_LS),    // request to send
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  .CTS(USB_UART_CTS_I_B_LS)     // clear to send
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 );
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 assign GPIO_LED_0 = observables[0];
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 assign GPIO_LED_1 = observables[1];
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 assign GPIO_LED_2 = observables[2];
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 assign GPIO_LED_3 = observables[3];
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 assign GPIO_LED_4 = observables[4];
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endmodule

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