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gavinux |
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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package uart_components is
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component uart
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generic (DATA_BITS : integer);
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Port (
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rst : in std_logic;
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clk : in std_logic;
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dlw : in std_logic_vector(15 downto 0);
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--
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-- DLW = round(clk_Hz / (Desired_BaudRate x 16)) - 2
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-- For baudrate 115200Hz :
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-- 62.5MHz : DLW = 0x001F
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-- 50.0MHz : DLW = 0x0019
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--
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tx_wr : in std_logic; -- pulse signal
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tx_fifo_reset : in std_logic; -- pulse signal
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tx_din : in std_logic_vector(DATA_BITS-1 downto 0);
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tx_fifo_full : out std_logic; -- level signal
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tx_fifo_almost_full : out std_logic; -- level signal
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tx_fifo_empty : out std_logic; -- level signal
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tx_fifo_almost_empty : out std_logic; -- level signal
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tx_xmt_empty : out std_logic; -- level signal, transmit shift register empty
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--
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rx_rd : in std_logic; -- pulse signal
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rx_fifo_reset : in std_logic; -- pulse signal
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rx_dout : out std_logic_vector(DATA_BITS-1 downto 0);
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rx_fifo_full : out std_logic; -- level signal
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rx_fifo_almost_full : out std_logic; -- level signal
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rx_fifo_empty : out std_logic; -- level signal
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rx_fifo_almost_empty : out std_logic; -- level signal
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rx_timeout : out std_logic; -- pulse signal
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--
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tx_sout : out std_logic;
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rx_sin : in std_logic
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);
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end component;
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component baudrate
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port(
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clk : in std_logic;
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rst : in std_logic;
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dlw : in std_logic_vector(15 downto 0);
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tick : out std_logic -- baudrate * 16 tick
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);
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end component;
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component xmt
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generic (DATA_BITS : integer);
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port (
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clk : in std_logic; -- Clock
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rst : in std_logic; -- Reset
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tick : in std_logic; -- baudrate * 16 tick
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wr : in std_logic; -- write din to transmitter
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din : in std_logic_vector(DATA_BITS-1 downto 0); -- Input data
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sout : out std_logic; -- Transmitter serial output
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done : out std_logic -- Transmitter operation finished
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);
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end component;
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component rcv
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generic (DATA_BITS : integer);
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port (
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clk : in std_logic; -- Clock
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rst : in std_logic; -- Reset
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tick : in std_logic; -- baudrate * 16 tick
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sin : in std_logic; -- Receiver serial input
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dout : out std_logic_vector(DATA_BITS-1 downto 0); -- Output data
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done : out std_logic -- Receiver operation finished
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);
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end component;
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component tmo
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Port (
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clk : in std_logic;
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clr : in std_logic;
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tick : in std_logic;
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timeout : out std_logic
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);
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end component;
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COMPONENT fifo_generator_v8_1_8x16
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PORT (
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clk : IN STD_LOGIC;
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srst : IN STD_LOGIC;
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din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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wr_en : IN STD_LOGIC;
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rd_en : IN STD_LOGIC;
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dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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full : OUT STD_LOGIC;
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almost_full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC;
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almost_empty : OUT STD_LOGIC
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);
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END COMPONENT;
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end uart_components;
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package body uart_components is
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end uart_components;
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