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gavinux |
------------------------------------------------------------------------------
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-- uart_plb.vhd - entity/architecture pair
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------------------------------------------------------------------------------
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-- IMPORTANT:
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-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
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--
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-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
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--
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-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
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-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
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-- OF THE USER_LOGIC ENTITY.
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------------------------------------------------------------------------------
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--
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-- ***************************************************************************
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-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
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-- ** **
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-- ** Xilinx, Inc. **
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-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
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-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
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-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
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-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
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-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
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-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
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-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
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-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
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-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
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-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
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-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
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-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
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-- ** FOR A PARTICULAR PURPOSE. **
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-- ** **
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-- ***************************************************************************
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--
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------------------------------------------------------------------------------
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-- Filename: uart_plb.vhd
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-- Version: 1.00.a
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-- Description: Top level design, instantiates library components and user logic.
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-- Date: Fri Jun 03 17:26:27 2011 (by Create and Import Peripheral Wizard)
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-- VHDL Standard: VHDL'93
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------------------------------------------------------------------------------
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-- Naming Conventions:
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-- active low signals: "*_n"
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-- clock signals: "clk", "clk_div#", "clk_#x"
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-- reset signals: "rst", "rst_n"
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-- generics: "C_*"
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-- user defined types: "*_TYPE"
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-- state machine next state: "*_ns"
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-- state machine current state: "*_cs"
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-- combinatorial signals: "*_com"
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-- pipelined or register delay signals: "*_d#"
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-- counter signals: "*cnt*"
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-- clock enable signals: "*_ce"
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-- internal version of output port: "*_i"
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-- device pins: "*_pin"
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-- ports: "- Names begin with Uppercase"
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-- processes: "*_PROCESS"
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-- component instantiations: "<ENTITY_>I_<#|FUNC>"
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library proc_common_v3_00_a;
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use proc_common_v3_00_a.proc_common_pkg.all;
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use proc_common_v3_00_a.ipif_pkg.all;
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library interrupt_control_v2_01_a;
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use interrupt_control_v2_01_a.interrupt_control;
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library plbv46_slave_single_v1_01_a;
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use plbv46_slave_single_v1_01_a.plbv46_slave_single;
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library uart_plb_v1_00_a;
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use uart_plb_v1_00_a.user_logic;
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------------------------------------------------------------------------------
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-- Entity section
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------------------------------------------------------------------------------
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-- Definition of Generics:
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-- C_BASEADDR -- PLBv46 slave: base address
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-- C_HIGHADDR -- PLBv46 slave: high address
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-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
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-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
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-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
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-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
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-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
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-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
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-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
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-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
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-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
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-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
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-- C_FAMILY -- Xilinx FPGA family
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--
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-- Definition of Ports:
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-- SPLB_Clk -- PLB main bus clock
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-- SPLB_Rst -- PLB main bus reset
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-- PLB_ABus -- PLB address bus
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-- PLB_UABus -- PLB upper address bus
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-- PLB_PAValid -- PLB primary address valid indicator
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-- PLB_SAValid -- PLB secondary address valid indicator
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-- PLB_rdPrim -- PLB secondary to primary read request indicator
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-- PLB_wrPrim -- PLB secondary to primary write request indicator
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-- PLB_masterID -- PLB current master identifier
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-- PLB_abort -- PLB abort request indicator
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-- PLB_busLock -- PLB bus lock
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-- PLB_RNW -- PLB read/not write
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-- PLB_BE -- PLB byte enables
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-- PLB_MSize -- PLB master data bus size
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-- PLB_size -- PLB transfer size
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-- PLB_type -- PLB transfer type
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-- PLB_lockErr -- PLB lock error indicator
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-- PLB_wrDBus -- PLB write data bus
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-- PLB_wrBurst -- PLB burst write transfer indicator
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-- PLB_rdBurst -- PLB burst read transfer indicator
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-- PLB_wrPendReq -- PLB write pending bus request indicator
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-- PLB_rdPendReq -- PLB read pending bus request indicator
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-- PLB_wrPendPri -- PLB write pending request priority
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-- PLB_rdPendPri -- PLB read pending request priority
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-- PLB_reqPri -- PLB current request priority
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-- PLB_TAttribute -- PLB transfer attribute
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-- Sl_addrAck -- Slave address acknowledge
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-- Sl_SSize -- Slave data bus size
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-- Sl_wait -- Slave wait indicator
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-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
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-- Sl_wrDAck -- Slave write data acknowledge
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-- Sl_wrComp -- Slave write transfer complete indicator
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-- Sl_wrBTerm -- Slave terminate write burst transfer
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-- Sl_rdDBus -- Slave read data bus
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-- Sl_rdWdAddr -- Slave read word address
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-- Sl_rdDAck -- Slave read data acknowledge
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-- Sl_rdComp -- Slave read transfer complete indicator
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-- Sl_rdBTerm -- Slave terminate read burst transfer
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-- Sl_MBusy -- Slave busy indicator
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-- Sl_MWrErr -- Slave write error indicator
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-- Sl_MRdErr -- Slave read error indicator
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-- Sl_MIRQ -- Slave interrupt indicator
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-- IP2INTC_Irpt -- Interrupt output to processor
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------------------------------------------------------------------------------
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entity uart_plb is
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generic
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(
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-- ADD USER GENERICS BELOW THIS LINE ---------------
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--USER generics added here
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-- ADD USER GENERICS ABOVE THIS LINE ---------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- Bus protocol parameters, do not add to or delete
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C_BASEADDR : std_logic_vector := X"FFFFFFFF";
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C_HIGHADDR : std_logic_vector := X"00000000";
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C_SPLB_AWIDTH : integer := 32;
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C_SPLB_DWIDTH : integer := 128;
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C_SPLB_NUM_MASTERS : integer := 8;
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C_SPLB_MID_WIDTH : integer := 3;
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C_SPLB_NATIVE_DWIDTH : integer := 32;
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C_SPLB_P2P : integer := 0;
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C_SPLB_SUPPORT_BURSTS : integer := 0;
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C_SPLB_SMALLEST_MASTER : integer := 32;
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C_SPLB_CLK_PERIOD_PS : integer := 10000;
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C_INCLUDE_DPHASE_TIMER : integer := 0;
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C_FAMILY : string := "virtex6"
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-- DO NOT EDIT ABOVE THIS LINE ---------------------
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);
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port
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(
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-- ADD USER PORTS BELOW THIS LINE ------------------
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--USER ports added here
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tx_sout : out std_logic;
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rx_sin : in std_logic;
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-- ADD USER PORTS ABOVE THIS LINE ------------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- Bus protocol ports, do not add to or delete
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SPLB_Clk : in std_logic;
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SPLB_Rst : in std_logic;
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PLB_ABus : in std_logic_vector(0 to 31);
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PLB_UABus : in std_logic_vector(0 to 31);
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PLB_PAValid : in std_logic;
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PLB_SAValid : in std_logic;
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PLB_rdPrim : in std_logic;
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PLB_wrPrim : in std_logic;
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PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
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PLB_abort : in std_logic;
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PLB_busLock : in std_logic;
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PLB_RNW : in std_logic;
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PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
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PLB_MSize : in std_logic_vector(0 to 1);
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PLB_size : in std_logic_vector(0 to 3);
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PLB_type : in std_logic_vector(0 to 2);
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PLB_lockErr : in std_logic;
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PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
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PLB_wrBurst : in std_logic;
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PLB_rdBurst : in std_logic;
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PLB_wrPendReq : in std_logic;
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PLB_rdPendReq : in std_logic;
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PLB_wrPendPri : in std_logic_vector(0 to 1);
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PLB_rdPendPri : in std_logic_vector(0 to 1);
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PLB_reqPri : in std_logic_vector(0 to 1);
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PLB_TAttribute : in std_logic_vector(0 to 15);
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Sl_addrAck : out std_logic;
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Sl_SSize : out std_logic_vector(0 to 1);
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Sl_wait : out std_logic;
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Sl_rearbitrate : out std_logic;
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Sl_wrDAck : out std_logic;
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Sl_wrComp : out std_logic;
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Sl_wrBTerm : out std_logic;
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Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
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Sl_rdWdAddr : out std_logic_vector(0 to 3);
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Sl_rdDAck : out std_logic;
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Sl_rdComp : out std_logic;
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Sl_rdBTerm : out std_logic;
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Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
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Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
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Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
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Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
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IP2INTC_Irpt : out std_logic
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-- DO NOT EDIT ABOVE THIS LINE ---------------------
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);
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attribute SIGIS : string;
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attribute SIGIS of SPLB_Clk : signal is "CLK";
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attribute SIGIS of SPLB_Rst : signal is "RST";
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attribute SIGIS of IP2INTC_Irpt : signal is "INTR_LEVEL_HIGH";
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end entity uart_plb;
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------------------------------------------------------------------------------
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-- Architecture section
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------------------------------------------------------------------------------
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architecture IMP of uart_plb is
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------------------------------------------
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-- Array of base/high address pairs for each address range
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------------------------------------------
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constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
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constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
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constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
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constant INTR_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
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constant INTR_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
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244 |
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constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
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245 |
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(
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246 |
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ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
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247 |
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ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
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248 |
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ZERO_ADDR_PAD & INTR_BASEADDR, -- interrupt control space base address
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249 |
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ZERO_ADDR_PAD & INTR_HIGHADDR -- interrupt control space high address
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250 |
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);
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------------------------------------------
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253 |
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-- Array of desired number of chip enables for each address range
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254 |
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------------------------------------------
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255 |
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constant USER_SLV_NUM_REG : integer := 8;
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256 |
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constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
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257 |
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constant INTR_NUM_CE : integer := 16;
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258 |
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259 |
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constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
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260 |
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(
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262 |
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1 => INTR_NUM_CE -- number of ce for interrupt control space
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263 |
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);
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264 |
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265 |
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------------------------------------------
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266 |
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-- Ratio of bus clock to core clock (for use in dual clock systems)
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267 |
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-- 1 = ratio is 1:1
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268 |
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-- 2 = ratio is 2:1
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269 |
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------------------------------------------
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270 |
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constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
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271 |
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272 |
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------------------------------------------
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273 |
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-- Width of the slave data bus (32 only)
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------------------------------------------
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275 |
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constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
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276 |
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constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
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278 |
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279 |
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------------------------------------------
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280 |
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-- Number of device level interrupts
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281 |
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------------------------------------------
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282 |
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constant INTR_NUM_IPIF_IRPT_SRC : integer := 4;
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283 |
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284 |
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------------------------------------------
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285 |
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-- Capture mode for each IP interrupt (generated by user logic)
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-- 1 = pass through (non-inverting)
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-- 2 = pass through (inverting)
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-- 3 = registered level (non-inverting)
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-- 4 = registered level (inverting)
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-- 5 = positive edge detect
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-- 6 = negative edge detect
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292 |
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------------------------------------------
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constant USER_NUM_INTR : integer := 1;
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constant USER_INTR_CAPTURE_MODE : integer := 1;
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296 |
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constant INTR_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
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(
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);
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300 |
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301 |
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------------------------------------------
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302 |
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-- Device priority encoder feature inclusion/omission
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303 |
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-- true = include priority encoder
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304 |
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-- false = omit priority encoder
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305 |
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------------------------------------------
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306 |
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constant INTR_INCLUDE_DEV_PENCODER : boolean := false;
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307 |
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308 |
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------------------------------------------
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309 |
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-- Device ISC feature inclusion/omission
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310 |
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-- true = include device ISC
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311 |
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-- false = omit device ISC
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312 |
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------------------------------------------
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313 |
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constant INTR_INCLUDE_DEV_ISC : boolean := false;
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314 |
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315 |
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------------------------------------------
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316 |
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-- Index for CS/CE
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317 |
|
|
------------------------------------------
|
318 |
|
|
constant USER_SLV_CS_INDEX : integer := 0;
|
319 |
|
|
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
|
320 |
|
|
constant INTR_CS_INDEX : integer := 1;
|
321 |
|
|
constant INTR_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX);
|
322 |
|
|
|
323 |
|
|
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
|
324 |
|
|
|
325 |
|
|
------------------------------------------
|
326 |
|
|
-- IP Interconnect (IPIC) signal declarations
|
327 |
|
|
------------------------------------------
|
328 |
|
|
signal ipif_Bus2IP_Clk : std_logic;
|
329 |
|
|
signal ipif_Bus2IP_Reset : std_logic;
|
330 |
|
|
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
|
331 |
|
|
signal ipif_IP2Bus_WrAck : std_logic;
|
332 |
|
|
signal ipif_IP2Bus_RdAck : std_logic;
|
333 |
|
|
signal ipif_IP2Bus_Error : std_logic;
|
334 |
|
|
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
|
335 |
|
|
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
|
336 |
|
|
signal ipif_Bus2IP_RNW : std_logic;
|
337 |
|
|
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
|
338 |
|
|
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
|
339 |
|
|
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
|
340 |
|
|
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
|
341 |
|
|
signal intr_IPIF_Reg_Interrupts : std_logic_vector(0 to 1);
|
342 |
|
|
signal intr_IPIF_Lvl_Interrupts : std_logic_vector(0 to INTR_NUM_IPIF_IRPT_SRC-1);
|
343 |
|
|
signal intr_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
|
344 |
|
|
signal intr_IP2Bus_WrAck : std_logic;
|
345 |
|
|
signal intr_IP2Bus_RdAck : std_logic;
|
346 |
|
|
signal intr_IP2Bus_Error : std_logic;
|
347 |
|
|
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
|
348 |
|
|
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
|
349 |
|
|
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
|
350 |
|
|
signal user_IP2Bus_RdAck : std_logic;
|
351 |
|
|
signal user_IP2Bus_WrAck : std_logic;
|
352 |
|
|
signal user_IP2Bus_Error : std_logic;
|
353 |
|
|
signal user_IP2Bus_IntrEvent : std_logic_vector(0 to USER_NUM_INTR-1);
|
354 |
|
|
|
355 |
|
|
begin
|
356 |
|
|
|
357 |
|
|
------------------------------------------
|
358 |
|
|
-- instantiate plbv46_slave_single
|
359 |
|
|
------------------------------------------
|
360 |
|
|
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
|
361 |
|
|
generic map
|
362 |
|
|
(
|
363 |
|
|
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
|
364 |
|
|
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
|
365 |
|
|
C_SPLB_P2P => C_SPLB_P2P,
|
366 |
|
|
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
|
367 |
|
|
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
|
368 |
|
|
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
|
369 |
|
|
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
|
370 |
|
|
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
|
371 |
|
|
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
|
372 |
|
|
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
|
373 |
|
|
C_FAMILY => C_FAMILY
|
374 |
|
|
)
|
375 |
|
|
port map
|
376 |
|
|
(
|
377 |
|
|
SPLB_Clk => SPLB_Clk,
|
378 |
|
|
SPLB_Rst => SPLB_Rst,
|
379 |
|
|
PLB_ABus => PLB_ABus,
|
380 |
|
|
PLB_UABus => PLB_UABus,
|
381 |
|
|
PLB_PAValid => PLB_PAValid,
|
382 |
|
|
PLB_SAValid => PLB_SAValid,
|
383 |
|
|
PLB_rdPrim => PLB_rdPrim,
|
384 |
|
|
PLB_wrPrim => PLB_wrPrim,
|
385 |
|
|
PLB_masterID => PLB_masterID,
|
386 |
|
|
PLB_abort => PLB_abort,
|
387 |
|
|
PLB_busLock => PLB_busLock,
|
388 |
|
|
PLB_RNW => PLB_RNW,
|
389 |
|
|
PLB_BE => PLB_BE,
|
390 |
|
|
PLB_MSize => PLB_MSize,
|
391 |
|
|
PLB_size => PLB_size,
|
392 |
|
|
PLB_type => PLB_type,
|
393 |
|
|
PLB_lockErr => PLB_lockErr,
|
394 |
|
|
PLB_wrDBus => PLB_wrDBus,
|
395 |
|
|
PLB_wrBurst => PLB_wrBurst,
|
396 |
|
|
PLB_rdBurst => PLB_rdBurst,
|
397 |
|
|
PLB_wrPendReq => PLB_wrPendReq,
|
398 |
|
|
PLB_rdPendReq => PLB_rdPendReq,
|
399 |
|
|
PLB_wrPendPri => PLB_wrPendPri,
|
400 |
|
|
PLB_rdPendPri => PLB_rdPendPri,
|
401 |
|
|
PLB_reqPri => PLB_reqPri,
|
402 |
|
|
PLB_TAttribute => PLB_TAttribute,
|
403 |
|
|
Sl_addrAck => Sl_addrAck,
|
404 |
|
|
Sl_SSize => Sl_SSize,
|
405 |
|
|
Sl_wait => Sl_wait,
|
406 |
|
|
Sl_rearbitrate => Sl_rearbitrate,
|
407 |
|
|
Sl_wrDAck => Sl_wrDAck,
|
408 |
|
|
Sl_wrComp => Sl_wrComp,
|
409 |
|
|
Sl_wrBTerm => Sl_wrBTerm,
|
410 |
|
|
Sl_rdDBus => Sl_rdDBus,
|
411 |
|
|
Sl_rdWdAddr => Sl_rdWdAddr,
|
412 |
|
|
Sl_rdDAck => Sl_rdDAck,
|
413 |
|
|
Sl_rdComp => Sl_rdComp,
|
414 |
|
|
Sl_rdBTerm => Sl_rdBTerm,
|
415 |
|
|
Sl_MBusy => Sl_MBusy,
|
416 |
|
|
Sl_MWrErr => Sl_MWrErr,
|
417 |
|
|
Sl_MRdErr => Sl_MRdErr,
|
418 |
|
|
Sl_MIRQ => Sl_MIRQ,
|
419 |
|
|
Bus2IP_Clk => ipif_Bus2IP_Clk,
|
420 |
|
|
Bus2IP_Reset => ipif_Bus2IP_Reset,
|
421 |
|
|
IP2Bus_Data => ipif_IP2Bus_Data,
|
422 |
|
|
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
|
423 |
|
|
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
|
424 |
|
|
IP2Bus_Error => ipif_IP2Bus_Error,
|
425 |
|
|
Bus2IP_Addr => ipif_Bus2IP_Addr,
|
426 |
|
|
Bus2IP_Data => ipif_Bus2IP_Data,
|
427 |
|
|
Bus2IP_RNW => ipif_Bus2IP_RNW,
|
428 |
|
|
Bus2IP_BE => ipif_Bus2IP_BE,
|
429 |
|
|
Bus2IP_CS => ipif_Bus2IP_CS,
|
430 |
|
|
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
|
431 |
|
|
Bus2IP_WrCE => ipif_Bus2IP_WrCE
|
432 |
|
|
);
|
433 |
|
|
|
434 |
|
|
------------------------------------------
|
435 |
|
|
-- instantiate interrupt_control
|
436 |
|
|
------------------------------------------
|
437 |
|
|
INTERRUPT_CONTROL_I : entity interrupt_control_v2_01_a.interrupt_control
|
438 |
|
|
generic map
|
439 |
|
|
(
|
440 |
|
|
C_NUM_CE => INTR_NUM_CE,
|
441 |
|
|
C_NUM_IPIF_IRPT_SRC => INTR_NUM_IPIF_IRPT_SRC,
|
442 |
|
|
C_IP_INTR_MODE_ARRAY => INTR_IP_INTR_MODE_ARRAY,
|
443 |
|
|
C_INCLUDE_DEV_PENCODER => INTR_INCLUDE_DEV_PENCODER,
|
444 |
|
|
C_INCLUDE_DEV_ISC => INTR_INCLUDE_DEV_ISC,
|
445 |
|
|
C_IPIF_DWIDTH => IPIF_SLV_DWIDTH
|
446 |
|
|
)
|
447 |
|
|
port map
|
448 |
|
|
(
|
449 |
|
|
Bus2IP_Clk => ipif_Bus2IP_Clk,
|
450 |
|
|
Bus2IP_Reset => ipif_Bus2IP_Reset,
|
451 |
|
|
Bus2IP_Data => ipif_Bus2IP_Data,
|
452 |
|
|
Bus2IP_BE => ipif_Bus2IP_BE,
|
453 |
|
|
Interrupt_RdCE => ipif_Bus2IP_RdCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
|
454 |
|
|
Interrupt_WrCE => ipif_Bus2IP_WrCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
|
455 |
|
|
IPIF_Reg_Interrupts => intr_IPIF_Reg_Interrupts,
|
456 |
|
|
IPIF_Lvl_Interrupts => intr_IPIF_Lvl_Interrupts,
|
457 |
|
|
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent,
|
458 |
|
|
Intr2Bus_DevIntr => IP2INTC_Irpt,
|
459 |
|
|
Intr2Bus_DBus => intr_IP2Bus_Data,
|
460 |
|
|
Intr2Bus_WrAck => intr_IP2Bus_WrAck,
|
461 |
|
|
Intr2Bus_RdAck => intr_IP2Bus_RdAck,
|
462 |
|
|
Intr2Bus_Error => intr_IP2Bus_Error,
|
463 |
|
|
Intr2Bus_Retry => open,
|
464 |
|
|
Intr2Bus_ToutSup => open
|
465 |
|
|
);
|
466 |
|
|
|
467 |
|
|
-- feed registered and level-pass-through interrupts into Device ISC if exists, otherwise ignored
|
468 |
|
|
intr_IPIF_Reg_Interrupts(0) <= '0';
|
469 |
|
|
intr_IPIF_Reg_Interrupts(1) <= '0';
|
470 |
|
|
intr_IPIF_Lvl_Interrupts(0) <= '0';
|
471 |
|
|
intr_IPIF_Lvl_Interrupts(1) <= '0';
|
472 |
|
|
intr_IPIF_Lvl_Interrupts(2) <= '0';
|
473 |
|
|
intr_IPIF_Lvl_Interrupts(3) <= '0';
|
474 |
|
|
|
475 |
|
|
------------------------------------------
|
476 |
|
|
-- instantiate User Logic
|
477 |
|
|
------------------------------------------
|
478 |
|
|
USER_LOGIC_I : entity uart_plb_v1_00_a.user_logic
|
479 |
|
|
generic map
|
480 |
|
|
(
|
481 |
|
|
-- MAP USER GENERICS BELOW THIS LINE ---------------
|
482 |
|
|
--USER generics mapped here
|
483 |
|
|
-- MAP USER GENERICS ABOVE THIS LINE ---------------
|
484 |
|
|
C_SLV_DWIDTH => USER_SLV_DWIDTH,
|
485 |
|
|
C_NUM_REG => USER_NUM_REG,
|
486 |
|
|
C_NUM_INTR => USER_NUM_INTR
|
487 |
|
|
)
|
488 |
|
|
port map
|
489 |
|
|
(
|
490 |
|
|
-- MAP USER PORTS BELOW THIS LINE ------------------
|
491 |
|
|
--USER ports mapped here
|
492 |
|
|
tx_sout => tx_sout,
|
493 |
|
|
rx_sin => rx_sin,
|
494 |
|
|
-- MAP USER PORTS ABOVE THIS LINE ------------------
|
495 |
|
|
Bus2IP_Clk => ipif_Bus2IP_Clk,
|
496 |
|
|
Bus2IP_Reset => ipif_Bus2IP_Reset,
|
497 |
|
|
Bus2IP_Data => ipif_Bus2IP_Data,
|
498 |
|
|
Bus2IP_BE => ipif_Bus2IP_BE,
|
499 |
|
|
Bus2IP_RdCE => user_Bus2IP_RdCE,
|
500 |
|
|
Bus2IP_WrCE => user_Bus2IP_WrCE,
|
501 |
|
|
IP2Bus_Data => user_IP2Bus_Data,
|
502 |
|
|
IP2Bus_RdAck => user_IP2Bus_RdAck,
|
503 |
|
|
IP2Bus_WrAck => user_IP2Bus_WrAck,
|
504 |
|
|
IP2Bus_Error => user_IP2Bus_Error,
|
505 |
|
|
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent
|
506 |
|
|
);
|
507 |
|
|
|
508 |
|
|
------------------------------------------
|
509 |
|
|
-- connect internal signals
|
510 |
|
|
------------------------------------------
|
511 |
|
|
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, intr_IP2Bus_Data ) is
|
512 |
|
|
begin
|
513 |
|
|
|
514 |
|
|
case ipif_Bus2IP_CS is
|
515 |
|
|
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
|
516 |
|
|
when "01" => ipif_IP2Bus_Data <= intr_IP2Bus_Data;
|
517 |
|
|
when others => ipif_IP2Bus_Data <= (others => '0');
|
518 |
|
|
end case;
|
519 |
|
|
|
520 |
|
|
end process IP2BUS_DATA_MUX_PROC;
|
521 |
|
|
|
522 |
|
|
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or intr_IP2Bus_WrAck;
|
523 |
|
|
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck;
|
524 |
|
|
ipif_IP2Bus_Error <= user_IP2Bus_Error or intr_IP2Bus_Error;
|
525 |
|
|
|
526 |
|
|
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
|
527 |
|
|
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
|
528 |
|
|
|
529 |
|
|
end IMP;
|