URL https://opencores.org/ocsvn/uart_serial/uart_serial/trunk

Subversion Repositories uart_serial

[/] [uart_serial/] [trunk/] [modelsim/] [compile.tcl] - Blame information for rev 4

Details | Compare with Previous | View Log


# if simulation was running then quit
quit -sim
 
set origin [pwd]
 
if {![file isdirectory work]} {
    exec vlib work
}
 
#cd $origin
 
# map lpm library, for ModelSim to find lpm objects
exec vmap lpm {$MODEL_TECH/../altera/vhdl/220model}
 
# map the work library
exec vmap work work
 
 
# compile all files
 
vcom -work work -2002 -explicit -check_synthesis ../sources/uart_serial.vhd
vcom -work work -2002 -explicit -check_synthesis ../testbench/tb_uart.vhd

Line No.	Rev	Author	Line
1	2	martin.xrm	`# if simulation was running then quit`
2			`quit -sim`
3
4			`set origin [pwd]`
5
6			`if {![file isdirectory work]} {`
7			`exec vlib work`
8			`}`
9
10			`#cd $origin`
11
12			`# map lpm library, for ModelSim to find lpm objects`
13			`exec vmap lpm {$MODEL_TECH/../altera/vhdl/220model}`
14
15			`# map the work library`
16			`exec vmap work work`
17
18
19			`# compile all files`
20
21			`vcom -work work -2002 -explicit -check_synthesis ../sources/uart_serial.vhd`
22			`vcom -work work -2002 -explicit -check_synthesis ../testbench/tb_uart.vhd`

Browse

Tools

Subversion Repositories uart_serial

[/] [uart_serial/] [trunk/] [modelsim/] [compile.tcl] - Blame information for rev 4