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UDP/IP Core for FPGAs (in VHDL)
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======================================================================================================
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Update date: February 9th, 2010
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Build date: December 15th, 2009
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Description
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-----------
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This is a VHDL implementation of a UDP/IP core that can be connected to the input and output ports of the
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Virtex-5 Ethernet MAC Local Link Wrapper and enable communication betweena a PC and a FPGA.
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It has been area-optimized, it is suitable for direct PC-FPGA communication and can operate at Gigabit speed.
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Example placement on a Virtex 5:
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-- -----------------------------------------------------------------------
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-- | EXAMPLE DESIGN WRAPPER |
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-- | --------------------------------------------------------|
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-- | |LOCAL LINK WRAPPER |
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-- | | -----------------------------------------|
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-- | UDP/IP core | |BLOCK LEVEL WRAPPER |
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-- | ----------- | | --------------------- |
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-- | |-------- | | ---------- | | ETHERNET MAC | |
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-- | || IPv4 | | | | | | | WRAPPER | --------- |
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-- |->| pack |-> |->| |--|--->| Tx Tx |--| |--->|
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-- | || trans| | | | | | | client PHY | | | |
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-- | |-------- | | | LOCAL | | | I/F I/F | | | |
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-- | | | | | LINK | | | | | PHY | |
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-- | | | | | FIFO | | | | | I/F | |
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-- | | | | | | | | | | | |
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-- | |-------- | | | | | | Rx Rx | | | |
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-- | || IPv4 | | | | | | | client PHY | | | |
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-- | || pack |<- |<-| |<-|----| I/F I/F |<-| |<---|
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-- | ||receiv| | | | | | | | --------- |
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-- | |-------- | | ---------- | --------------------- |
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-- | ----------- | -----------------------------------------|
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-- | --------------------------------------------------------|
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-- -----------------------------------------------------------------------
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Package Structure
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-----------------
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This package contains the following files and folder:
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-README : This file
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-UDP_IP_CORE : This folder contains VHDL, XCO and NGC files both for Virtex 5 as well as Spartan 3 FPGAs.
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-LUT COE file : This folder contains a COE file for the LUT that contains the IP packet header field.
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-JAVA app : This folder contains the JAVA application used on the PC side for transmitting and receiving packets.
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-PAPER : This folder contains a paper that describes in detail the design and implementation of the core.
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Usage of the UDP/IP core
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------------------------
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Before integrating the core into your design you have to reinitialize the LUT of the transmitter.
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This LUT contains the header section of the IP packet.One must change the X fields that appear in the following table.
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The field that should be changed are:
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Destination MAC Address : (LUT)
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Source MAC Address : (LUT)
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Source IP Address : (LUT)
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Destination IP Address : (LUT)
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Source Port : (LUT)
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Destination Port : (LUT)
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Header Checksum : VHDL file
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The Addresses are read from the LUT, thats why a reinitialization is required.
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The Header Checksum base value is not read from the LUT. It can be found in the VHDL file.
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The Header Checksum base value depends on the IP Addresses and it is the Header Checksum value of a packet with no user data.
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If you choose to use the JAVA application provided in this packet only the Destination MAC Address needs to change.
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------------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------------
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-- IPv4 PACKET STRUCTURE : -- --
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-- size | Description | Transmission Order | Position --
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------------------------------------------------------------------------------------------------------------------------------------------
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-- 6 bytes | Destin MAC Address (PC) | 0 1 2 3 4 5 | LUT --
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-- | X-X-X-X-X-X | | --
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-- | | | --
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-- 6 bytes | Source MAC Address (FPGA) | 6 7 8 9 10 11 | LUT --
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-- | 11111111-11111111-11111111-11111111-... | | --
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-- 2 bytes | Ethernet Type | 12 13 | LUT --
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-- | (fixed to 00001000-00000000 :=> | | --
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-- | Internet Protocol, Version 4 (IPv4)) | | --
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-- -- Start of IPv4 Packet - - - - - - - - - - - - - -- --
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-- 1 byte | 4 MSBs = Version , 4 LSBs = Header Length| 14 | LUT --
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-- | 0100 0101 | | --
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-- 1 byte | Differentiated Services | 15 | LUT --
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-- | 00000000 | | --
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-- 2 bytes | Total Length | 16 17 | REG --
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-- | 00000000-00100100 (base: 20 + 8 + datalength)| | --
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-- 2 bytes | Identification | 18 19 | LUT --
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-- | 00000000-00000000 | | --
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-- 2 bytes | 3 MSBs = Flags , 13 LSBs = Fragment Offset| 20 21 | LUT --
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-- | 010 - 0000000000000 | | --
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-- 1 byte | Time to Live | 22 | LUT --
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-- | 01000000 | | --
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-- 1 byte | Protocol | 23 | LUT --
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-- | 00010001 | | --
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-- 2 bytes | Header Checksum | 24 25 | REG --
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-- | X X (base value) | | --
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-- 4 bytes | Source IP Address | 26 27 28 29 | LUT --
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-- | X-X-X-X - FPGA | | --
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-- 4 bytes | Destin IP Address | 30 31 32 33 | LUT --
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-- | X-X-X-X - PC | | --
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-- -- Start of UDP Packet - - - - - - - - - - - - - - -- --
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-- 2 bytes | Source Port | 34 35 | LUT --
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-- | X-X | | --
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-- 2 bytes | Destination Port | 36 37 | LUT --
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-- | X-X | | --
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-- 2 bytes | Length | 38 39 | REG --
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-- | 00000000 - 00010000 (8 + # data bytes)| | --
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-- 2 bytes | Checksum | 40 41 | LUT --
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-- | 00000000 - 00000000 | | --
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-- X bytes | Data | 42 .. X | from input --
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-- | | | -- --
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------------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------------
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Interface of the UDP/IP core
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----------------------------
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The interface of the unit is defined as follows:
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entity UDP_IP_Core is
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Port ( rst : in STD_LOGIC; -- active-high
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clk_125MHz : in STD_LOGIC;
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-- Transmit signals
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transmit_start_enable : in STD_LOGIC;
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transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
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usr_data_trans_phase_on : out STD_LOGIC;
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transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
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start_of_frame_O : out STD_LOGIC;
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end_of_frame_O : out STD_LOGIC;
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source_ready : out STD_LOGIC;
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transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
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--Receive Signals
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rx_sof : in STD_LOGIC;
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rx_eof : in STD_LOGIC;
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input_bus : in STD_LOGIC_VECTOR(7 downto 0);
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valid_out_usr_data : out STD_LOGIC;
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usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)
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);
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end UDP_IP_Core;
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The UDP/IP core and the LOCAL LINK WRAPPER must have the same rst and clk signals.
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Signal transmit_start_enable : active high , It must be high for one clock cycle only.
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Signal transmit_data_length : number of user data to be transmitted (number of bytes)
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Signal usr_data_trans_phase_on: is high one clock cycle before the transmittion of user data and remains high while transmitting user data.
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Signal transmit_data_input_bus : input data to be transmitted. Starts transmitting one clock cycle after the usr_data_trans_phase_on is set.
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Signals start_of_frame_O,end_of_frame_O,source_ready,transmit_data_output_bus should be connected to the local link wrapper's input ports.
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Signals rx_sof, rx_eof : active low, inputs from the local link wrapper
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Signal input_bus : input from the local link wrapper
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Signal valid_out_usr_data : output to user, when set it indicates that the usr_data_output_bus contains the user data section of the incoming packet
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Signal usr_data_output_bus : user data output bus output to the user
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Implementation Details
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----------------------
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The VHDL unit have been designed using the Xilinx 10.1 Design Suite.
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ISE 10.1 was used to create the unit.
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Verification Details
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--------------------
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Modelsim 6.3f was used for extensive post place and route simulations.
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The development board HTG-V5-PCIE by HiTech Global populated with a V5SX95T-1 FPGA was used to verify the correct behavior of the core.
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The Spartan3 configuration has not been hardware-verified!
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Citation
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--------
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By using this component in any architecture design and associated publication, you agree to cite it as:
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"Efficient PC-FPGA Communication over Gigabit Ethernet", by Nikolaos Alachiotis, Simon A. Berger and Alexandros Stamatakis,
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The Exelixis Lab, Exelixis-RRDR-2010-4, TU Munich, February 2010.
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Authors and Contact Details
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---------------------------
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Nikos Alachiotis alachiot@in.tum.de , n.alachiotis@gmail.com
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Simon A. Berger bergers@in.tum.de
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Alexandros Stamatakis stamatak@in.tum.de
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Technichal University of Munich
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Department of Computer Science / I 12
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The Exelixis Lab
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Boltzmannstr. 3
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D-85748 Garching b. Muenchen
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Copyright
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---------
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This component is free. In case you use it for any purpose, particularly
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when publishing work relying on this component you must cite it as:
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IPv4 PACKET TRANSMITTER by Nikolas Alachiotis and Alexandros Stamatakis, The Exelixis Lab, TU Munich, distributed by the authors via
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http://wwwkramer.in.tum.de/exelixis/
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You can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This component is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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Release Notes
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------------
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Update date: February 9th, 2010
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Build date : December 15th, 2009
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