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-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
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-- --
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-- Engineer: Nikolaos Ch. Alachiotis --
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-- --
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-- Contact: alachiot@cs.tum.edu --
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-- n.alachiotis@gmail.com --
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-- --
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-- Create Date: 15:29:59 02/07/2010 --
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-- Module Name: UDP_IP_Core --
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-- Target Devices: Virtex 5 FPGAs --
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-- Tool versions: ISE 10.1 --
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-- Description: This component can be used to transmit and receive UDP/IP --
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-- Ethernet Packets (IPv4). --
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-- Additional Comments: The core has been area-optimized and is suitable for direct --
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-- PC-FPGA communication at Gigabit speed. --
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-- --
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-----------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity UDP_IP_Core is
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Port ( rst : in STD_LOGIC; -- active-high
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clk_125MHz : in STD_LOGIC;
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-- Transmit signals
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transmit_start_enable : in STD_LOGIC;
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transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
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usr_data_trans_phase_on : out STD_LOGIC;
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transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
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start_of_frame_O : out STD_LOGIC;
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end_of_frame_O : out STD_LOGIC;
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source_ready : out STD_LOGIC;
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transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
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--Receive Signals
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rx_sof : in STD_LOGIC;
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rx_eof : in STD_LOGIC;
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input_bus : in STD_LOGIC_VECTOR(7 downto 0);
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valid_out_usr_data : out STD_LOGIC;
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usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)
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);
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end UDP_IP_Core;
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architecture Behavioral of UDP_IP_Core is
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component IPV4_PACKET_TRANSMITTER is
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Port ( rst : in STD_LOGIC;
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clk_125MHz : in STD_LOGIC;
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transmit_start_enable : in STD_LOGIC;
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transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
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usr_data_trans_phase_on : out STD_LOGIC;
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transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
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start_of_frame_O : out STD_LOGIC;
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end_of_frame_O : out STD_LOGIC;
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source_ready : out STD_LOGIC;
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transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)
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);
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end component;
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component IPv4_PACKET_RECEIVER is
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Port ( rst : in STD_LOGIC;
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clk_125Mhz : in STD_LOGIC;
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rx_sof : in STD_LOGIC;
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rx_eof : in STD_LOGIC;
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input_bus : in STD_LOGIC_VECTOR(7 downto 0);
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valid_out_usr_data : out STD_LOGIC;
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usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0));
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end component;
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begin
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IPV4_PACKET_TRANSMITTER_port_map: IPV4_PACKET_TRANSMITTER
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Port Map
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( rst => rst,
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clk_125MHz => clk_125MHz,
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transmit_start_enable => transmit_start_enable,
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transmit_data_length => transmit_data_length,
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usr_data_trans_phase_on => usr_data_trans_phase_on,
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transmit_data_input_bus => transmit_data_input_bus,
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start_of_frame_O => start_of_frame_O,
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end_of_frame_O => end_of_frame_O,
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source_ready => source_ready,
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transmit_data_output_bus => transmit_data_output_bus
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);
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IPv4_PACKET_RECEIVER_port_map: IPv4_PACKET_RECEIVER
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Port Map
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( rst => rst,
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clk_125Mhz => clk_125Mhz,
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rx_sof => rx_sof,
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rx_eof => rx_eof,
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input_bus => input_bus,
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valid_out_usr_data => valid_out_usr_data,
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usr_data_output_bus => usr_data_output_bus
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);
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end Behavioral;
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