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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:01:00 06/11/2011
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-- Design Name:
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-- Module Name: UDP_integration_example - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.ipv4_types.all;
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use work.arp_types.all;
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entity UDP_integration_example is
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port (
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-- System signals
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------------------
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reset : in std_logic; -- asynchronous reset
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clk_in_p : in std_logic; -- 200MHz clock input from board
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clk_in_n : in std_logic;
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-- System controls
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------------------
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PBTX : in std_logic;
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UDP_RX : out std_logic;
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UDP_Start : out std_logic;
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PBTX_LED : out std_logic;
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TX_Started : out std_logic;
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TX_Completed : out std_logic;
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reset_leds : in std_logic;
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display : out std_logic_vector(7 downto 0);
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-- GMII Interface
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-----------------
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phy_resetn : out std_logic;
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gmii_txd : out std_logic_vector(7 downto 0);
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gmii_tx_en : out std_logic;
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gmii_tx_er : out std_logic;
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gmii_tx_clk : out std_logic;
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gmii_rxd : in std_logic_vector(7 downto 0);
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gmii_rx_dv : in std_logic;
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gmii_rx_er : in std_logic;
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gmii_rx_clk : in std_logic;
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gmii_col : in std_logic;
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gmii_crs : in std_logic;
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mii_tx_clk : in std_logic
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);
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end UDP_integration_example;
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architecture Behavioral of UDP_integration_example is
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------------------------------------------------------------------------------
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-- Component Declaration for the complete IP layer
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------------------------------------------------------------------------------
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component UDP_Complete
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Port (
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-- UDP TX signals
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udp_tx_start : in std_logic; -- indicates req to tx UDP
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udp_txi : in udp_tx_type; -- UDP tx cxns
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udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
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udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
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-- UDP RX signals
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udp_rx_start : out std_logic; -- indicates receipt of udp header
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udp_rxo : out udp_rx_type;
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-- IP RX signals
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ip_rx_hdr : out ipv4_rx_header_type;
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-- system signals
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clk_in_p : in std_logic; -- 200MHz clock input from board
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clk_in_n : in std_logic;
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clk_out : out std_logic;
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reset : in STD_LOGIC;
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our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
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our_mac_address : in std_logic_vector (47 downto 0);
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-- status signals
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arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
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ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
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-- GMII Interface
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phy_resetn : out std_logic;
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gmii_txd : out std_logic_vector(7 downto 0);
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gmii_tx_en : out std_logic;
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gmii_tx_er : out std_logic;
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gmii_tx_clk : out std_logic;
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gmii_rxd : in std_logic_vector(7 downto 0);
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gmii_rx_dv : in std_logic;
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gmii_rx_er : in std_logic;
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gmii_rx_clk : in std_logic;
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gmii_col : in std_logic;
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gmii_crs : in std_logic;
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mii_tx_clk : in std_logic
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);
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end component;
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type state_type is (IDLE, DATA_OUT);
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type count_mode_type is (RST, INCR, HOLD);
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type set_clr_type is (SET, CLR, HOLD);
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-- system signals
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signal clk_int : std_logic;
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signal our_mac : STD_LOGIC_VECTOR (47 downto 0);
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signal our_ip : STD_LOGIC_VECTOR (31 downto 0);
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signal udp_tx_int : udp_tx_type;
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signal udp_tx_result_int : std_logic_vector (1 downto 0);
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signal udp_tx_data_out_ready_int : std_logic;
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signal udp_rx_int : udp_rx_type;
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signal udp_tx_start_int : std_logic;
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signal udp_rx_start_int : std_logic;
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signal arp_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0);
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signal ip_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0);
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signal ip_rx_hdr_int : ipv4_rx_header_type;
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-- state signals
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signal state : state_type;
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signal count : unsigned (7 downto 0);
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signal tx_hdr : udp_tx_header_type;
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signal tx_start_reg : std_logic;
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signal tx_started_reg : std_logic;
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signal tx_fin_reg : std_logic;
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signal udp_rx_start_reg : std_logic;
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-- control signals
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signal next_state : state_type;
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signal set_state : std_logic;
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signal set_count : count_mode_type;
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signal set_hdr : std_logic;
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signal set_tx_start : set_clr_type;
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signal set_last : std_logic;
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signal set_tx_started : set_clr_type;
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signal set_tx_fin : set_clr_type;
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signal set_udp_rx_start_reg : set_clr_type;
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begin
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process (
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our_ip, our_mac, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, udp_rx_start_reg,
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udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
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reset, tx_started_reg, tx_fin_reg, tx_start_reg
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)
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begin
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-- set up our local addresses
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our_ip <= x"c0a80509"; -- 192.168.5.9
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our_mac <= x"002320212223";
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-- determine RX good and error LEDs
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if udp_rx_int.hdr.is_valid = '1' then
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UDP_RX <= '1';
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else
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UDP_RX <= '0';
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end if;
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UDP_Start <= udp_rx_start_reg;
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TX_Started <= tx_start_reg; --tx_started_reg;
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TX_Completed <= tx_fin_reg;
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-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
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display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
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display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
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end process;
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-- AUTO TX process - on receipt of any UDP pkt, send a response
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-- TX response process - COMB
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tx_proc_combinatorial: process(
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-- inputs
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udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid, PBTX, reset_leds,
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-- state
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state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, udp_rx_start_reg,
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-- controls
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next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
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set_tx_started, set_tx_fin, set_udp_rx_start_reg
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)
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begin
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-- set output_followers
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udp_tx_int.hdr <= tx_hdr;
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udp_tx_int.data.data_out_last <= set_last;
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udp_tx_start_int <= tx_start_reg;
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-- set control signal defaults
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next_state <= IDLE;
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set_state <= '0';
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set_count <= HOLD;
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set_hdr <= '0';
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set_tx_start <= HOLD;
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set_last <= '0';
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set_tx_started <= HOLD;
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set_tx_fin <= HOLD;
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set_udp_rx_start_reg <= HOLD;
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-- FSM
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case state is
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when IDLE =>
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udp_tx_int.data.data_out <= (others => '0');
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udp_tx_int.data.data_out_valid <= '0';
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if udp_rx_start_int = '1' or PBTX = '1' then
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set_udp_rx_start_reg <= SET;
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set_tx_started <= SET;
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set_hdr <= '1';
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set_tx_start <= SET;
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set_tx_fin <= CLR;
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set_count <= RST;
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next_state <= DATA_OUT;
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set_state <= '1';
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elsif reset_leds = '1' then
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set_udp_rx_start_reg <= CLR;
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set_tx_started <= CLR;
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set_tx_fin <= CLR;
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end if;
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when DATA_OUT =>
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udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
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udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
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if udp_tx_data_out_ready_int = '1' then
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set_tx_start <= CLR;
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if unsigned(count) = x"03" then
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set_last <= '1';
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set_tx_fin <= SET;
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set_tx_started <= CLR;
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next_state <= IDLE;
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set_state <= '1';
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else
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set_count <= INCR;
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end if;
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end if;
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end case;
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end process;
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-- TX response process - SEQ
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tx_proc_sequential: process(clk_int)
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begin
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if rising_edge(clk_int) then
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if reset = '1' then
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-- reset state variables
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state <= IDLE;
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count <= x"00";
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tx_start_reg <= '0';
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tx_hdr.dst_ip_addr <= (others => '0');
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tx_hdr.dst_port <= (others => '0');
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tx_hdr.src_port <= (others => '0');
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tx_hdr.data_length <= (others => '0');
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tx_hdr.checksum <= (others => '0');
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tx_started_reg <= '0';
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tx_fin_reg <= '0';
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PBTX_LED <= '0';
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else
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PBTX_LED <= PBTX;
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-- Next rx_state processing
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if set_state = '1' then
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state <= next_state;
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else
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state <= state;
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end if;
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-- count processing
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case set_count is
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when RST => count <= x"00";
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when INCR => count <= count + 1;
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when HOLD => count <= count;
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end case;
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-- set tx hdr
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if set_hdr = '1' then
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tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
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tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
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tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
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tx_hdr.data_length <= x"0004";
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tx_hdr.checksum <= x"0000";
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else
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tx_hdr <= tx_hdr;
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end if;
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-- set tx start signal
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case set_tx_start is
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when SET => tx_start_reg <= '1';
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when CLR => tx_start_reg <= '0';
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when HOLD => tx_start_reg <= tx_start_reg;
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end case;
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-- set tx started signal
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case set_tx_started is
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when SET => tx_started_reg <= '1';
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when CLR => tx_started_reg <= '0';
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when HOLD => tx_started_reg <= tx_started_reg;
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end case;
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-- set tx finished signal
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case set_tx_fin is
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when SET => tx_fin_reg <= '1';
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when CLR => tx_fin_reg <= '0';
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when HOLD => tx_fin_reg <= tx_fin_reg;
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end case;
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-- set UDP START signal
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case set_udp_rx_start_reg is
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when SET => udp_rx_start_reg <= '1';
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when CLR => udp_rx_start_reg <= '0';
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when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
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end case;
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end if;
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end if;
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end process;
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------------------------------------------------------------------------------
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-- Instantiate the UDP layer
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------------------------------------------------------------------------------
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UDP_block : UDP_Complete PORT MAP
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(
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-- UDP interface
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udp_tx_start => udp_tx_start_int,
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udp_txi => udp_tx_int,
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udp_tx_result => udp_tx_result_int,
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udp_tx_data_out_ready=> udp_tx_data_out_ready_int,
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udp_rx_start => udp_rx_start_int,
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udp_rxo => udp_rx_int,
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-- IP RX signals
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ip_rx_hdr => ip_rx_hdr_int,
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-- System interface
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clk_in_p => clk_in_p,
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clk_in_n => clk_in_n,
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clk_out => clk_int,
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reset => reset,
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344 |
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|
our_ip_address => our_ip,
|
345 |
|
|
our_mac_address => our_mac,
|
346 |
|
|
-- status signals
|
347 |
|
|
arp_pkt_count => arp_pkt_count_int,
|
348 |
|
|
ip_pkt_count => ip_pkt_count_int,
|
349 |
|
|
-- GMII Interface
|
350 |
|
|
-----------------
|
351 |
|
|
phy_resetn => phy_resetn,
|
352 |
|
|
gmii_txd => gmii_txd,
|
353 |
|
|
gmii_tx_en => gmii_tx_en,
|
354 |
|
|
gmii_tx_er => gmii_tx_er,
|
355 |
|
|
gmii_tx_clk => gmii_tx_clk,
|
356 |
|
|
gmii_rxd => gmii_rxd,
|
357 |
|
|
gmii_rx_dv => gmii_rx_dv,
|
358 |
|
|
gmii_rx_er => gmii_rx_er,
|
359 |
|
|
gmii_rx_clk => gmii_rx_clk,
|
360 |
|
|
gmii_col => gmii_col,
|
361 |
|
|
gmii_crs => gmii_crs,
|
362 |
|
|
mii_tx_clk => mii_tx_clk
|
363 |
|
|
);
|
364 |
|
|
|
365 |
|
|
|
366 |
|
|
end Behavioral;
|
367 |
|
|
|