URL https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk

Subversion Repositories udp_ip_stack

[/] [udp_ip_stack/] [trunk/] [bench/] [vhdl/] [IPv4_RX_tb.vhd] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   17:32:02 06/03/2011
-- Design Name:   
-- Module Name:   C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_RX_tb.vhd
-- Project Name:  ip1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: IPv4_RX
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
 
 
ENTITY IPv4_RX_tb IS
END IPv4_RX_tb;
 
ARCHITECTURE behavior OF IPv4_RX_tb IS
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT IPv4_RX
    PORT(
                        -- IP Layer signals
                        ip_rx                                           : out ipv4_rx_type;
                        ip_rx_start                             : out std_logic;                                                                        -- indicates receipt of ip frame.
                        -- system signals
                        clk                                             : in  STD_LOGIC;                                                                        -- same clock used to clock mac data and ip data
                        reset                                   : in  STD_LOGIC;
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
                        -- MAC layer RX signals
                        mac_data_in                     : in  STD_LOGIC_VECTOR (7 downto 0);             -- ethernet frame (from dst mac addr through to last byte of frame)
                        mac_data_in_valid       : in  STD_LOGIC;                                                                        -- indicates data_in valid on clock
                        mac_data_in_last                : in  STD_LOGIC                                                                 -- indicates last data in frame
       );
    END COMPONENT;
 
 
   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
   signal mac_data_in : std_logic_vector(7 downto 0) := (others => '0');
   signal mac_data_in_valid : std_logic := '0';
   signal mac_data_in_last : std_logic := '0';
 
        --Outputs
   signal ip_rx_start : std_logic;
   signal ip_rx : ipv4_rx_type;
 
   -- Clock period definitions
   constant clk_period : time := 8 ns;
 
BEGIN
 
        -- Instantiate the Unit Under Test (UUT)
   uut: IPv4_RX PORT MAP (
          ip_rx                                 => ip_rx,
          ip_rx_start           => ip_rx_start,
          clk                                   => clk,
          reset                                 => reset,
          our_ip_address        => our_ip_address,
          mac_data_in           => mac_data_in,
          mac_data_in_valid => mac_data_in_valid,
          mac_data_in_last => mac_data_in_last
        );
 
   -- Clock process definitions
   clk_process :process
   begin
                clk <= '0';
                wait for clk_period/2;
                clk <= '1';
                wait for clk_period/2;
   end process;
 
 
   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;
 
                our_ip_address <= x"c0a80509";          -- 192.168.5.9
                mac_data_in_valid <= '0';
      mac_data_in_last <= '0';
 
                reset <= '1';
      wait for clk_period*10;
                reset <= '0';
      wait for clk_period*5;
 
                -- check reset conditions
                assert ip_rx_start = '0'                                                         report "ip_rx_start not initialised correctly on reset";
                assert ip_rx.hdr.is_valid = '0'                                  report "ip_rx.hdr.is_valid not initialised correctly on reset";
                assert ip_rx.hdr.protocol = x"00"                               report "ip_rx.hdr.protocol not initialised correctly on reset";
                assert ip_rx.hdr.data_length = x"0000"                  report "ip_rx.hdr.data_length not initialised correctly on reset";
                assert ip_rx.hdr.src_ip_addr = x"00000000"      report "ip_rx.hdr.src_ip_addr not initialised correctly on reset";
                assert ip_rx.hdr.num_frame_errors = x"00"               report "ip_rx.hdr.num_frame_errors not initialised correctly on reset";
                assert ip_rx.data.data_in = x"00"                               report "ip_rx.data.data_in not initialised correctly on reset";
                assert ip_rx.data.data_in_valid = '0'                    report "ip_rx.data.data_in_valid not initialised correctly on reset";
                assert ip_rx.data.data_in_last = '0'                     report "ip_rx.data.data_in_last not initialised correctly on reset";
 
      -- insert stimulus here 
 
                ------------
                -- TEST 1 -- basic functional rx test with received ip pkt
                ------------
 
                report "T1: Send an eth frame with IP pkt dst ip_address c0a80509, dst mac 002320212223";
 
                mac_data_in_valid <= '1';
                -- dst MAC (bc)
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"23"; wait for clk_period;
                mac_data_in <= x"20"; wait for clk_period;
                mac_data_in <= x"21"; wait for clk_period;
                mac_data_in <= x"22"; wait for clk_period;
                mac_data_in <= x"23"; wait for clk_period;
                -- src MAC
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"23"; wait for clk_period;
                mac_data_in <= x"18"; wait for clk_period;
                mac_data_in <= x"29"; wait for clk_period;
                mac_data_in <= x"26"; wait for clk_period;
                mac_data_in <= x"7c"; wait for clk_period;
                -- type
                mac_data_in <= x"08"; wait for clk_period;              -- IP pkt
                mac_data_in <= x"00"; wait for clk_period;
                -- ver & HL / service type
                mac_data_in <= x"45"; wait for clk_period;
                mac_data_in <= x"00"; wait for clk_period;
                -- total len
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"18"; wait for clk_period;
                -- ID
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"00"; wait for clk_period;
                -- flags & frag
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"00"; wait for clk_period;
                -- TTL
                mac_data_in <= x"00"; wait for clk_period;
                -- Protocol
                mac_data_in <= x"11"; wait for clk_period;
                -- Header CKS
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"00"; wait for clk_period;
                -- SRC IP
                mac_data_in <= x"c0"; wait for clk_period;
                mac_data_in <= x"a8"; wait for clk_period;
                mac_data_in <= x"05"; wait for clk_period;
                mac_data_in <= x"01"; wait for clk_period;
                -- DST IP
                mac_data_in <= x"c0"; wait for clk_period;
                mac_data_in <= x"a8"; wait for clk_period;
                mac_data_in <= x"05"; wait for clk_period;
                mac_data_in <= x"09"; wait for clk_period;
 
                -- user data
                mac_data_in <= x"24"; wait for clk_period;
 
                assert ip_rx.hdr.is_valid = '1'                                 report "T1: ip_rx.hdr.is_valid not set";
                assert ip_rx.hdr.protocol = x"11"                               report "T1: ip_rx.hdr.protocol not set correctly";
                assert ip_rx.hdr.data_length = x"0004"                  report "T1: ip_rx.hdr.data_length not set correctly";
                assert ip_rx.hdr.src_ip_addr = x"c0a80501"      report "T1: ip_rx.hdr.src_ip_addr not set correctly";
                assert ip_rx.hdr.num_frame_errors = x"00"               report "T1: ip_rx.hdr.num_frame_errors not set correctly";
                assert ip_rx.hdr.last_error_code = x"0"          report "T1: ip_rx.hdr.last_error_code not set correctly";
                assert ip_rx_start = '1'                                                        report "T1: ip_rx_start not set";
                assert ip_rx.data.data_in_valid = '1'                   report "T1: ip_rx.data.data_in_valid not set";
 
                mac_data_in <= x"25"; wait for clk_period;
                mac_data_in <= x"26"; wait for clk_period;
                mac_data_in <= x"27"; mac_data_in_last <= '1';wait for clk_period;
 
                assert ip_rx.data.data_in_last = '1'                    report "T1: ip_rx.data.data_in_last not set";
 
                mac_data_in <= x"00";
                mac_data_in_last <= '0';
                mac_data_in_valid <= '0';
                wait for clk_period;
 
                assert ip_rx.data.data_in_valid = '0'                    report "T1: ip_rx.data.data_in_valid not cleared";
                assert ip_rx.data.data_in_last = '0'                     report "T1: ip_rx.data.data_in_last not cleared";
                assert ip_rx.hdr.num_frame_errors = x"00"               report "T1: ip_rx.hdr.num_frame_errors non zero at end of test";
                assert ip_rx.hdr.last_error_code = x"0"          report "T1: ip_rx.hdr.last_error_code indicates error at end of test";
                assert ip_rx_start = '0'                                                 report "T1: ip_rx_start not cleared";
 
                ------------
                -- TEST 2 -- basic functional rx test with received ip pkt that is not for us
                ------------
 
                report "T2: Send an eth frame with IP pkt dst ip_address c0a80507, dst mac 002320212223";
 
                mac_data_in_valid <= '1';
                -- dst MAC (bc)
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"23"; wait for clk_period;
                mac_data_in <= x"20"; wait for clk_period;
                mac_data_in <= x"21"; wait for clk_period;
                mac_data_in <= x"22"; wait for clk_period;
                mac_data_in <= x"23"; wait for clk_period;
 
                assert ip_rx.hdr.is_valid = '0'                                  report "T2: ip_rx.hdr.is_valid remains set";
 
                -- src MAC
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"23"; wait for clk_period;
                mac_data_in <= x"18"; wait for clk_period;
                mac_data_in <= x"29"; wait for clk_period;
                mac_data_in <= x"26"; wait for clk_period;
                mac_data_in <= x"7c"; wait for clk_period;
                -- type
                mac_data_in <= x"08"; wait for clk_period;              -- IP pkt
                mac_data_in <= x"00"; wait for clk_period;
                -- ver & HL / service type
                mac_data_in <= x"45"; wait for clk_period;
                mac_data_in <= x"00"; wait for clk_period;
                -- total len
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"18"; wait for clk_period;
                -- ID
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"00"; wait for clk_period;
                -- flags & frag
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"00"; wait for clk_period;
                -- TTL
                mac_data_in <= x"00"; wait for clk_period;
                -- Protocol
                mac_data_in <= x"11"; wait for clk_period;
                -- Header CKS
                mac_data_in <= x"00"; wait for clk_period;
                mac_data_in <= x"00"; wait for clk_period;
                -- SRC IP
                mac_data_in <= x"c0"; wait for clk_period;
                mac_data_in <= x"a8"; wait for clk_period;
                mac_data_in <= x"05"; wait for clk_period;
                mac_data_in <= x"02"; wait for clk_period;
                -- DST IP
                mac_data_in <= x"c0"; wait for clk_period;
                mac_data_in <= x"a8"; wait for clk_period;
                mac_data_in <= x"05"; wait for clk_period;
                mac_data_in <= x"07"; wait for clk_period;
 
                -- user data
                mac_data_in <= x"24"; wait for clk_period;
 
                assert ip_rx.hdr.is_valid = '1'                                 report "T2: ip_rx.hdr.is_valid not set";
                assert ip_rx.hdr.protocol = x"11"                               report "T2: ip_rx.hdr.protocol not set correctly";
                assert ip_rx.hdr.data_length = x"0004"                  report "T2: ip_rx.hdr.data_length not set correctly";
                assert ip_rx.hdr.src_ip_addr = x"c0a80502"      report "T2: ip_rx.hdr.src_ip_addr not set correctly";
                assert ip_rx.hdr.num_frame_errors = x"00"               report "T2: ip_rx.hdr.num_frame_errors not set correctly";
                assert ip_rx.hdr.last_error_code = x"0"          report "T2: ip_rx.hdr.last_error_code not set correctly";
                assert ip_rx_start = '0'                                                 report "T2: ip_rx_start set when pkt not for us";
                assert ip_rx.data.data_in_valid = '0'                    report "T2: ip_rx.data.data_in_valid set when pkt not for us";
 
                mac_data_in <= x"25"; wait for clk_period;
                mac_data_in <= x"26"; wait for clk_period;
                mac_data_in <= x"27"; mac_data_in_last <= '1';wait for clk_period;
 
                assert ip_rx.data.data_in_last = '0'                     report "T2: ip_rx.data.data_in_last set";
 
                mac_data_in <= x"00";
                mac_data_in_last <= '0';
                mac_data_in_valid <= '0';
                wait for clk_period;
 
                assert ip_rx.data.data_in_valid = '0'                    report "T2: ip_rx.data.data_in_valid not cleared";
                assert ip_rx.data.data_in_last = '0'                     report "T2: ip_rx.data.data_in_last not cleared";
                assert ip_rx.hdr.num_frame_errors = x"00"               report "T2: ip_rx.hdr.num_frame_errors non zero at end of test";
                assert ip_rx.hdr.last_error_code = x"0"          report "T2: ip_rx.hdr.last_error_code indicates error at end of test";
                assert ip_rx_start = '0'                                                 report "T2: ip_rx_start not cleared";
 
                report "--- end of tests ---";
 
      wait;
   end process;
 
END;

Browse

Tools

Subversion Repositories udp_ip_stack

[/] [udp_ip_stack/] [trunk/] [bench/] [vhdl/] [IPv4_RX_tb.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	pjf	`--------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 17:32:02 06/03/2011`
6			`-- Design Name:`
7			`-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_RX_tb.vhd`
8			`-- Project Name: ip1`
9			`-- Target Device:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- VHDL Test Bench Created by ISE for module: IPv4_RX`
14			`--`
15			`-- Dependencies:`
16			`--`
17			`-- Revision:`
18			`-- Revision 0.01 - File Created`
19			`-- Additional Comments:`
20			`--`
21			`-- Notes:`
22			`-- This testbench has been automatically generated using types std_logic and`
23			`-- std_logic_vector for the ports of the unit under test. Xilinx recommends`
24			`-- that these types always be used for the top-level I/O of a design in order`
25			`-- to guarantee that the testbench will bind correctly to the post-implementation`
26			`-- simulation model.`
27			`--------------------------------------------------------------------------------`
28			`library IEEE;`
29			`use IEEE.STD_LOGIC_1164.ALL;`
30			`use IEEE.NUMERIC_STD.ALL;`
31			`use work.axi.all;`
32			`use work.ipv4_types.all;`
33			`use work.arp_types.all;`
34
35
36			`ENTITY IPv4_RX_tb IS`
37			`END IPv4_RX_tb;`
38
39			`ARCHITECTURE behavior OF IPv4_RX_tb IS`
40
41			`-- Component Declaration for the Unit Under Test (UUT)`
42
43			`COMPONENT IPv4_RX`
44			`PORT(`
45			`-- IP Layer signals`
46			`ip_rx : out ipv4_rx_type;`
47			`ip_rx_start : out std_logic; -- indicates receipt of ip frame.`
48			`-- system signals`
49			`clk : in STD_LOGIC; -- same clock used to clock mac data and ip data`
50			`reset : in STD_LOGIC;`
51			`our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);`
52			`-- MAC layer RX signals`
53			`mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)`
54			`mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock`
55			`mac_data_in_last : in STD_LOGIC -- indicates last data in frame`
56			`);`
57			`END COMPONENT;`
58
59
60			`--Inputs`
61			`signal clk : std_logic := '0';`
62			`signal reset : std_logic := '0';`
63			`signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');`
64			`signal mac_data_in : std_logic_vector(7 downto 0) := (others => '0');`
65			`signal mac_data_in_valid : std_logic := '0';`
66			`signal mac_data_in_last : std_logic := '0';`
67
68			`--Outputs`
69			`signal ip_rx_start : std_logic;`
70			`signal ip_rx : ipv4_rx_type;`
71
72			`-- Clock period definitions`
73			`constant clk_period : time := 8 ns;`
74
75			`BEGIN`
76
77			`-- Instantiate the Unit Under Test (UUT)`
78			`uut: IPv4_RX PORT MAP (`
79			`ip_rx => ip_rx,`
80			`ip_rx_start => ip_rx_start,`
81			`clk => clk,`
82			`reset => reset,`
83			`our_ip_address => our_ip_address,`
84			`mac_data_in => mac_data_in,`
85			`mac_data_in_valid => mac_data_in_valid,`
86			`mac_data_in_last => mac_data_in_last`
87			`);`
88
89			`-- Clock process definitions`
90			`clk_process :process`
91			`begin`
92			`clk <= '0';`
93			`wait for clk_period/2;`
94			`clk <= '1';`
95			`wait for clk_period/2;`
96			`end process;`
97
98
99			`-- Stimulus process`
100			`stim_proc: process`
101			`begin`
102			`-- hold reset state for 100 ns.`
103			`wait for 100 ns;`
104
105			`our_ip_address <= x"c0a80509"; -- 192.168.5.9`
106			`mac_data_in_valid <= '0';`
107			`mac_data_in_last <= '0';`
108
109			`reset <= '1';`
110			`wait for clk_period*10;`
111			`reset <= '0';`
112			`wait for clk_period*5;`
113
114			`-- check reset conditions`
115			`assert ip_rx_start = '0' report "ip_rx_start not initialised correctly on reset";`
116			`assert ip_rx.hdr.is_valid = '0' report "ip_rx.hdr.is_valid not initialised correctly on reset";`
117			`assert ip_rx.hdr.protocol = x"00" report "ip_rx.hdr.protocol not initialised correctly on reset";`
118			`assert ip_rx.hdr.data_length = x"0000" report "ip_rx.hdr.data_length not initialised correctly on reset";`
119			`assert ip_rx.hdr.src_ip_addr = x"00000000" report "ip_rx.hdr.src_ip_addr not initialised correctly on reset";`
120			`assert ip_rx.hdr.num_frame_errors = x"00" report "ip_rx.hdr.num_frame_errors not initialised correctly on reset";`
121			`assert ip_rx.data.data_in = x"00" report "ip_rx.data.data_in not initialised correctly on reset";`
122			`assert ip_rx.data.data_in_valid = '0' report "ip_rx.data.data_in_valid not initialised correctly on reset";`
123			`assert ip_rx.data.data_in_last = '0' report "ip_rx.data.data_in_last not initialised correctly on reset";`
124
125			`-- insert stimulus here`
126
127			`------------`
128			`-- TEST 1 -- basic functional rx test with received ip pkt`
129			`------------`
130
131			`report "T1: Send an eth frame with IP pkt dst ip_address c0a80509, dst mac 002320212223";`
132
133			`mac_data_in_valid <= '1';`
134			`-- dst MAC (bc)`
135			`mac_data_in <= x"00"; wait for clk_period;`
136			`mac_data_in <= x"23"; wait for clk_period;`
137			`mac_data_in <= x"20"; wait for clk_period;`
138			`mac_data_in <= x"21"; wait for clk_period;`
139			`mac_data_in <= x"22"; wait for clk_period;`
140			`mac_data_in <= x"23"; wait for clk_period;`
141			`-- src MAC`
142			`mac_data_in <= x"00"; wait for clk_period;`
143			`mac_data_in <= x"23"; wait for clk_period;`
144			`mac_data_in <= x"18"; wait for clk_period;`
145			`mac_data_in <= x"29"; wait for clk_period;`
146			`mac_data_in <= x"26"; wait for clk_period;`
147			`mac_data_in <= x"7c"; wait for clk_period;`
148			`-- type`
149			`mac_data_in <= x"08"; wait for clk_period; -- IP pkt`
150			`mac_data_in <= x"00"; wait for clk_period;`
151			`-- ver & HL / service type`
152			`mac_data_in <= x"45"; wait for clk_period;`
153			`mac_data_in <= x"00"; wait for clk_period;`
154			`-- total len`
155			`mac_data_in <= x"00"; wait for clk_period;`
156			`mac_data_in <= x"18"; wait for clk_period;`
157			`-- ID`
158			`mac_data_in <= x"00"; wait for clk_period;`
159			`mac_data_in <= x"00"; wait for clk_period;`
160			`-- flags & frag`
161			`mac_data_in <= x"00"; wait for clk_period;`
162			`mac_data_in <= x"00"; wait for clk_period;`
163			`-- TTL`
164			`mac_data_in <= x"00"; wait for clk_period;`
165			`-- Protocol`
166			`mac_data_in <= x"11"; wait for clk_period;`
167			`-- Header CKS`
168			`mac_data_in <= x"00"; wait for clk_period;`
169			`mac_data_in <= x"00"; wait for clk_period;`
170			`-- SRC IP`
171			`mac_data_in <= x"c0"; wait for clk_period;`
172			`mac_data_in <= x"a8"; wait for clk_period;`
173			`mac_data_in <= x"05"; wait for clk_period;`
174			`mac_data_in <= x"01"; wait for clk_period;`
175			`-- DST IP`
176			`mac_data_in <= x"c0"; wait for clk_period;`
177			`mac_data_in <= x"a8"; wait for clk_period;`
178			`mac_data_in <= x"05"; wait for clk_period;`
179			`mac_data_in <= x"09"; wait for clk_period;`
180
181			`-- user data`
182			`mac_data_in <= x"24"; wait for clk_period;`
183
184			`assert ip_rx.hdr.is_valid = '1' report "T1: ip_rx.hdr.is_valid not set";`
185			`assert ip_rx.hdr.protocol = x"11" report "T1: ip_rx.hdr.protocol not set correctly";`
186			`assert ip_rx.hdr.data_length = x"0004" report "T1: ip_rx.hdr.data_length not set correctly";`
187			`assert ip_rx.hdr.src_ip_addr = x"c0a80501" report "T1: ip_rx.hdr.src_ip_addr not set correctly";`
188			`assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors not set correctly";`
189			`assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code not set correctly";`
190			`assert ip_rx_start = '1' report "T1: ip_rx_start not set";`
191			`assert ip_rx.data.data_in_valid = '1' report "T1: ip_rx.data.data_in_valid not set";`
192
193			`mac_data_in <= x"25"; wait for clk_period;`
194			`mac_data_in <= x"26"; wait for clk_period;`
195			`mac_data_in <= x"27"; mac_data_in_last <= '1';wait for clk_period;`
196
197			`assert ip_rx.data.data_in_last = '1' report "T1: ip_rx.data.data_in_last not set";`
198
199			`mac_data_in <= x"00";`
200			`mac_data_in_last <= '0';`
201			`mac_data_in_valid <= '0';`
202			`wait for clk_period;`
203
204			`assert ip_rx.data.data_in_valid = '0' report "T1: ip_rx.data.data_in_valid not cleared";`
205			`assert ip_rx.data.data_in_last = '0' report "T1: ip_rx.data.data_in_last not cleared";`
206			`assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors non zero at end of test";`
207			`assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code indicates error at end of test";`
208			`assert ip_rx_start = '0' report "T1: ip_rx_start not cleared";`
209
210			`------------`
211			`-- TEST 2 -- basic functional rx test with received ip pkt that is not for us`
212			`------------`
213
214			`report "T2: Send an eth frame with IP pkt dst ip_address c0a80507, dst mac 002320212223";`
215
216			`mac_data_in_valid <= '1';`
217			`-- dst MAC (bc)`
218			`mac_data_in <= x"00"; wait for clk_period;`
219			`mac_data_in <= x"23"; wait for clk_period;`
220			`mac_data_in <= x"20"; wait for clk_period;`
221			`mac_data_in <= x"21"; wait for clk_period;`
222			`mac_data_in <= x"22"; wait for clk_period;`
223			`mac_data_in <= x"23"; wait for clk_period;`
224
225			`assert ip_rx.hdr.is_valid = '0' report "T2: ip_rx.hdr.is_valid remains set";`
226
227			`-- src MAC`
228			`mac_data_in <= x"00"; wait for clk_period;`
229			`mac_data_in <= x"23"; wait for clk_period;`
230			`mac_data_in <= x"18"; wait for clk_period;`
231			`mac_data_in <= x"29"; wait for clk_period;`
232			`mac_data_in <= x"26"; wait for clk_period;`
233			`mac_data_in <= x"7c"; wait for clk_period;`
234			`-- type`
235			`mac_data_in <= x"08"; wait for clk_period; -- IP pkt`
236			`mac_data_in <= x"00"; wait for clk_period;`
237			`-- ver & HL / service type`
238			`mac_data_in <= x"45"; wait for clk_period;`
239			`mac_data_in <= x"00"; wait for clk_period;`
240			`-- total len`
241			`mac_data_in <= x"00"; wait for clk_period;`
242			`mac_data_in <= x"18"; wait for clk_period;`
243			`-- ID`
244			`mac_data_in <= x"00"; wait for clk_period;`
245			`mac_data_in <= x"00"; wait for clk_period;`
246			`-- flags & frag`
247			`mac_data_in <= x"00"; wait for clk_period;`
248			`mac_data_in <= x"00"; wait for clk_period;`
249			`-- TTL`
250			`mac_data_in <= x"00"; wait for clk_period;`
251			`-- Protocol`
252			`mac_data_in <= x"11"; wait for clk_period;`
253			`-- Header CKS`
254			`mac_data_in <= x"00"; wait for clk_period;`
255			`mac_data_in <= x"00"; wait for clk_period;`
256			`-- SRC IP`
257			`mac_data_in <= x"c0"; wait for clk_period;`
258			`mac_data_in <= x"a8"; wait for clk_period;`
259			`mac_data_in <= x"05"; wait for clk_period;`
260			`mac_data_in <= x"02"; wait for clk_period;`
261			`-- DST IP`
262			`mac_data_in <= x"c0"; wait for clk_period;`
263			`mac_data_in <= x"a8"; wait for clk_period;`
264			`mac_data_in <= x"05"; wait for clk_period;`
265			`mac_data_in <= x"07"; wait for clk_period;`
266
267			`-- user data`
268			`mac_data_in <= x"24"; wait for clk_period;`
269
270			`assert ip_rx.hdr.is_valid = '1' report "T2: ip_rx.hdr.is_valid not set";`
271			`assert ip_rx.hdr.protocol = x"11" report "T2: ip_rx.hdr.protocol not set correctly";`
272			`assert ip_rx.hdr.data_length = x"0004" report "T2: ip_rx.hdr.data_length not set correctly";`
273			`assert ip_rx.hdr.src_ip_addr = x"c0a80502" report "T2: ip_rx.hdr.src_ip_addr not set correctly";`
274			`assert ip_rx.hdr.num_frame_errors = x"00" report "T2: ip_rx.hdr.num_frame_errors not set correctly";`
275			`assert ip_rx.hdr.last_error_code = x"0" report "T2: ip_rx.hdr.last_error_code not set correctly";`
276			`assert ip_rx_start = '0' report "T2: ip_rx_start set when pkt not for us";`
277			`assert ip_rx.data.data_in_valid = '0' report "T2: ip_rx.data.data_in_valid set when pkt not for us";`
278
279			`mac_data_in <= x"25"; wait for clk_period;`
280			`mac_data_in <= x"26"; wait for clk_period;`
281			`mac_data_in <= x"27"; mac_data_in_last <= '1';wait for clk_period;`
282
283			`assert ip_rx.data.data_in_last = '0' report "T2: ip_rx.data.data_in_last set";`
284
285			`mac_data_in <= x"00";`
286			`mac_data_in_last <= '0';`
287			`mac_data_in_valid <= '0';`
288			`wait for clk_period;`
289
290			`assert ip_rx.data.data_in_valid = '0' report "T2: ip_rx.data.data_in_valid not cleared";`
291			`assert ip_rx.data.data_in_last = '0' report "T2: ip_rx.data.data_in_last not cleared";`
292			`assert ip_rx.hdr.num_frame_errors = x"00" report "T2: ip_rx.hdr.num_frame_errors non zero at end of test";`
293			`assert ip_rx.hdr.last_error_code = x"0" report "T2: ip_rx.hdr.last_error_code indicates error at end of test";`
294			`assert ip_rx_start = '0' report "T2: ip_rx_start not cleared";`
295
296			`report "--- end of tests ---";`
297
298			`wait;`
299			`end process;`
300
301			`END;`