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pjf |
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16:53:03 06/10/2011
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-- Design Name:
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-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/UDP_RX_tb.vhd
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-- Project Name: ip1
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: UDP_RX
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.ipv4_types.all;
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ENTITY UDP_RX_tb IS
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END UDP_RX_tb;
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ARCHITECTURE behavior OF UDP_RX_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT UDP_RX
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PORT(
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-- UDP Layer signals
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udp_rxo : inout udp_rx_type;
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udp_rx_start : out std_logic; -- indicates receipt of udp header
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-- system signals
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clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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-- IP layer RX signals
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ip_rx_start : in std_logic; -- indicates receipt of ip header
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ip_rx : inout ipv4_rx_type
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal reset : std_logic := '0';
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signal ip_rx_start : std_logic := '0';
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--BiDirs
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signal udp_rxo : udp_rx_type;
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signal ip_rx : ipv4_rx_type;
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--Outputs
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signal udp_rx_start : std_logic;
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-- Clock period definitions
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constant clk_period : time := 8 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: UDP_RX PORT MAP (
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udp_rxo => udp_rxo,
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udp_rx_start => udp_rx_start,
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clk => clk,
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reset => reset,
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ip_rx_start => ip_rx_start,
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ip_rx => ip_rx
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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ip_rx_start <= '0';
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ip_rx.data.data_in_valid <= '0';
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ip_rx.data.data_in_last <= '0';
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ip_rx.hdr.is_valid <= '0';
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ip_rx.hdr.protocol <= (others => '0');
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ip_rx.hdr.num_frame_errors <= (others => '0');
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ip_rx.hdr.last_error_code <= (others => '0');
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ip_rx.hdr.is_broadcast <= '0';
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reset <= '1';
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wait for clk_period*10;
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reset <= '0';
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wait for clk_period*5;
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reset <= '0';
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-- check reset conditions
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assert udp_rx_start = '0' report "udp_rx_start not initialised correctly on reset";
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assert udp_rxo.hdr.is_valid = '0' report "udp_rxo.hdr.is_valid not initialised correctly on reset";
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assert udp_rxo.data.data_in = x"00" report "udp_rxo.data.data_in not initialised correctly on reset";
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assert udp_rxo.data.data_in_valid = '0' report "udp_rxo.data.data_in_valid not initialised correctly on reset";
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assert udp_rxo.data.data_in_last = '0' report "udp_rxo.data.data_in_last not initialised correctly on reset";
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-- insert stimulus here
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------------
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-- TEST 1 -- basic functional rx test with received ip pkt
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------------
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report "T1: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
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ip_rx_start <= '1';
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ip_rx.data.data_in_valid <= '0';
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ip_rx.data.data_in_last <= '0';
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ip_rx.hdr.is_valid <= '1';
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ip_rx.hdr.protocol <= x"11"; -- UDP
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ip_rx.hdr.data_length <= x"000b";
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ip_rx.hdr.src_ip_addr<= x"c0a80501";
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wait for clk_period*3;
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-- now send the data
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ip_rx.data.data_in_valid <= '1';
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ip_rx.data.data_in <= x"14"; wait for clk_period; -- src port
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ip_rx.data.data_in <= x"98"; wait for clk_period;
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ip_rx.data.data_in <= x"87"; wait for clk_period; -- dst port
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ip_rx.data.data_in <= x"24"; wait for clk_period;
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ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
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ip_rx.data.data_in <= x"0b"; wait for clk_period;
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ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
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ip_rx.data.data_in <= x"00"; wait for clk_period;
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-- udp hdr should be valid
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assert udp_rxo.hdr.is_valid = '1' report "T1: udp_rxo.hdr.is_valid not set";
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ip_rx.data.data_in <= x"41"; wait for clk_period; -- data
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assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T1: udp_rxo.hdr.src_ip_addr not set correctly";
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assert udp_rxo.hdr.src_port = x"1498" report "T1: udp_rxo.hdr.src_port not set correctly";
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assert udp_rxo.hdr.dst_port = x"8724" report "T1: udp_rxo.hdr.dst_port not set correctly";
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assert udp_rxo.hdr.data_length = x"0003" report "T1: udp_rxo.hdr.data_length not set correctly";
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assert udp_rx_start = '1' report "T1: udp_rx_start not set";
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assert udp_rxo.data.data_in_valid = '1' report "T1: udp_rxo.data.data_in_valid not set";
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ip_rx.data.data_in <= x"45"; wait for clk_period; -- data
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ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
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assert udp_rxo.data.data_in_last = '1' report "T1: udp_rxo.data.data_in_last not set";
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ip_rx_start <= '0';
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ip_rx.data.data_in_valid <= '0';
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ip_rx.data.data_in_last <= '0';
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ip_rx.hdr.is_valid <= '0';
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wait for clk_period;
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assert udp_rxo.data.data_in = x"00" report "T1: udp_rxo.data.data_in not cleared";
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assert udp_rxo.data.data_in_valid = '0' report "T1: udp_rxo.data.data_in_valid not cleared";
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assert udp_rxo.data.data_in_last = '0' report "T1: udp_rxo.data.data_in_last not cleared";
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wait for clk_period;
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------------
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-- TEST 2 -- ability to receive 2nd ip pkt
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------------
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report "T2: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x7623 to port x0365 and 5 bytes data";
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ip_rx_start <= '1';
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ip_rx.data.data_in_valid <= '0';
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ip_rx.data.data_in_last <= '0';
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ip_rx.hdr.is_valid <= '1';
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ip_rx.hdr.protocol <= x"11"; -- UDP
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ip_rx.hdr.data_length <= x"000b";
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ip_rx.hdr.src_ip_addr<= x"c0a80501";
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wait for clk_period*3;
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-- now send the data
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ip_rx.data.data_in_valid <= '1';
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ip_rx.data.data_in <= x"76"; wait for clk_period; -- src port
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ip_rx.data.data_in <= x"23"; wait for clk_period;
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ip_rx.data.data_in <= x"03"; wait for clk_period; -- dst port
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ip_rx.data.data_in <= x"65"; wait for clk_period;
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ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
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ip_rx.data.data_in <= x"0d"; wait for clk_period;
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ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
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ip_rx.data.data_in <= x"00"; wait for clk_period;
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-- udp hdr should be valid
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assert udp_rxo.hdr.is_valid = '1' report "T2: udp_rxo.hdr.is_valid not set";
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ip_rx.data.data_in <= x"17"; wait for clk_period; -- data
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assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T2: udp_rxo.hdr.src_ip_addr not set correctly";
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assert udp_rxo.hdr.src_port = x"7623" report "T2: udp_rxo.hdr.src_port not set correctly";
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assert udp_rxo.hdr.dst_port = x"0365" report "T2: udp_rxo.hdr.dst_port not set correctly";
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assert udp_rxo.hdr.data_length = x"0005" report "T2: udp_rxo.hdr.data_length not set correctly";
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assert udp_rx_start = '1' report "T2: udp_rx_start not set";
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assert udp_rxo.data.data_in_valid = '1' report "T2: udp_rxo.data.data_in_valid not set";
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ip_rx.data.data_in <= x"37"; wait for clk_period; -- data
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ip_rx.data.data_in <= x"57"; wait for clk_period; -- data
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ip_rx.data.data_in <= x"73"; wait for clk_period; -- data
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ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
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assert udp_rxo.data.data_in_last = '1' report "T2: udp_rxo.data.data_in_last not set";
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ip_rx_start <= '0';
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ip_rx.data.data_in_valid <= '0';
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ip_rx.data.data_in_last <= '0';
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ip_rx.hdr.is_valid <= '0';
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wait for clk_period;
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assert udp_rxo.data.data_in = x"00" report "T2: udp_rxo.data.data_in not cleared";
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assert udp_rxo.data.data_in_valid = '0' report "T2: udp_rxo.data.data_in_valid not cleared";
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assert udp_rxo.data.data_in_last = '0' report "T2: udp_rxo.data.data_in_last not cleared";
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------------
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-- TEST 3 -- ability to reject non-udp protocols
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------------
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report "T3: Send an ip frame with IP src ip_address c0a80501, protocol x12 from port x7623 to port x0365 and 5 bytes data";
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ip_rx_start <= '1';
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ip_rx.data.data_in_valid <= '0';
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ip_rx.data.data_in_last <= '0';
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ip_rx.hdr.is_valid <= '1';
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ip_rx.hdr.protocol <= x"12"; -- non-UDP
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ip_rx.hdr.data_length <= x"000b";
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ip_rx.hdr.src_ip_addr<= x"c0a80501";
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wait for clk_period*3;
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-- now send the data
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ip_rx.data.data_in_valid <= '1';
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ip_rx.data.data_in <= x"76"; wait for clk_period; -- src port
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ip_rx.data.data_in <= x"23"; wait for clk_period;
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ip_rx.data.data_in <= x"03"; wait for clk_period; -- dst port
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ip_rx.data.data_in <= x"65"; wait for clk_period;
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ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
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ip_rx.data.data_in <= x"0d"; wait for clk_period;
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ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
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ip_rx.data.data_in <= x"00"; wait for clk_period;
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-- udp hdr should be valid
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assert udp_rxo.hdr.is_valid = '0' report "T3: udp_rxo.hdr.is_valid incorrectly set";
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ip_rx.data.data_in <= x"17"; wait for clk_period; -- data
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assert udp_rx_start = '0' report "T3: udp_rx_start incorrectly set";
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assert udp_rxo.data.data_in_valid = '0' report "T3: udp_rxo.data.data_in_valid not set";
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ip_rx.data.data_in <= x"37"; wait for clk_period; -- data
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ip_rx.data.data_in <= x"57"; wait for clk_period; -- data
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ip_rx.data.data_in <= x"73"; wait for clk_period; -- data
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ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
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assert udp_rxo.data.data_in_last = '0' report "T3: udp_rxo.data.data_in_last incorrectly set";
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ip_rx_start <= '0';
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ip_rx.data.data_in_valid <= '0';
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ip_rx.data.data_in_last <= '0';
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ip_rx.hdr.is_valid <= '0';
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wait for clk_period;
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assert udp_rxo.data.data_in = x"00" report "T3: udp_rxo.data.data_in not cleared";
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assert udp_rxo.data.data_in_valid = '0' report "T3: udp_rxo.data.data_in_valid not cleared";
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assert udp_rxo.data.data_in_last = '0' report "T3: udp_rxo.data.data_in_last not cleared";
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wait for clk_period;
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------------
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-- TEST 4 -- Ability to receive UDP pkt after non-UDP pkt
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------------
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report "T4: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
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ip_rx_start <= '1';
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ip_rx.data.data_in_valid <= '0';
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ip_rx.data.data_in_last <= '0';
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ip_rx.hdr.is_valid <= '1';
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ip_rx.hdr.protocol <= x"11"; -- UDP
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| 281 |
|
|
ip_rx.hdr.data_length <= x"000b";
|
| 282 |
|
|
ip_rx.hdr.src_ip_addr<= x"c0a80501";
|
| 283 |
|
|
wait for clk_period*3;
|
| 284 |
|
|
-- now send the data
|
| 285 |
|
|
ip_rx.data.data_in_valid <= '1';
|
| 286 |
|
|
ip_rx.data.data_in <= x"14"; wait for clk_period; -- src port
|
| 287 |
|
|
ip_rx.data.data_in <= x"98"; wait for clk_period;
|
| 288 |
|
|
ip_rx.data.data_in <= x"87"; wait for clk_period; -- dst port
|
| 289 |
|
|
ip_rx.data.data_in <= x"24"; wait for clk_period;
|
| 290 |
|
|
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
|
| 291 |
|
|
ip_rx.data.data_in <= x"0b"; wait for clk_period;
|
| 292 |
|
|
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
|
| 293 |
|
|
ip_rx.data.data_in <= x"00"; wait for clk_period;
|
| 294 |
|
|
-- udp hdr should be valid
|
| 295 |
|
|
assert udp_rxo.hdr.is_valid = '1' report "T4: udp_rxo.hdr.is_valid not set";
|
| 296 |
|
|
|
| 297 |
|
|
ip_rx.data.data_in <= x"41"; wait for clk_period; -- data
|
| 298 |
|
|
|
| 299 |
|
|
assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T4: udp_rxo.hdr.src_ip_addr not set correctly";
|
| 300 |
|
|
assert udp_rxo.hdr.src_port = x"1498" report "T4: udp_rxo.hdr.src_port not set correctly";
|
| 301 |
|
|
assert udp_rxo.hdr.dst_port = x"8724" report "T4: udp_rxo.hdr.dst_port not set correctly";
|
| 302 |
|
|
assert udp_rxo.hdr.data_length = x"0003" report "T4: udp_rxo.hdr.data_length not set correctly";
|
| 303 |
|
|
assert udp_rx_start = '1' report "T4: udp_rx_start not set";
|
| 304 |
|
|
assert udp_rxo.data.data_in_valid = '1' report "T4: udp_rxo.data.data_in_valid not set";
|
| 305 |
|
|
|
| 306 |
|
|
ip_rx.data.data_in <= x"45"; wait for clk_period; -- data
|
| 307 |
|
|
ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
|
| 308 |
|
|
assert udp_rxo.data.data_in_last = '1' report "T4: udp_rxo.data.data_in_last not set";
|
| 309 |
|
|
ip_rx_start <= '0';
|
| 310 |
|
|
ip_rx.data.data_in_valid <= '0';
|
| 311 |
|
|
ip_rx.data.data_in_last <= '0';
|
| 312 |
|
|
ip_rx.hdr.is_valid <= '0';
|
| 313 |
|
|
wait for clk_period;
|
| 314 |
|
|
assert udp_rxo.data.data_in = x"00" report "T4: udp_rxo.data.data_in not cleared";
|
| 315 |
|
|
assert udp_rxo.data.data_in_valid = '0' report "T4: udp_rxo.data.data_in_valid not cleared";
|
| 316 |
|
|
assert udp_rxo.data.data_in_last = '0' report "T4: udp_rxo.data.data_in_last not cleared";
|
| 317 |
|
|
|
| 318 |
|
|
wait for clk_period;
|
| 319 |
|
|
|
| 320 |
|
|
report "--- end of tests ---";
|
| 321 |
|
|
|
| 322 |
|
|
wait;
|
| 323 |
|
|
end process;
|
| 324 |
|
|
|
| 325 |
|
|
END;
|
