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pjf |
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09:57:01 06/13/2011
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-- Design Name:
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-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/udp1/UDP_complete_nomac_tb.vhd
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-- Project Name: udp1
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: UDP_Complete_nomac
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.02 - Added test for IP broadcast tx
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-- Revision 0.03 - Added tests for ARP timeout
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.ipv4_types.all;
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use work.arp_types.all;
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ENTITY UDP_av2_complete_nomac_tb IS
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END UDP_av2_complete_nomac_tb;
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ARCHITECTURE behavior OF UDP_av2_complete_nomac_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT UDP_Complete_nomac
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generic (
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CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
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ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
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);
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Port (
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-- UDP TX signals
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udp_tx_start : in std_logic; -- indicates req to tx UDP
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udp_txi : in udp_tx_type; -- UDP tx cxns
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udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
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udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
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-- UDP RX signals
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udp_rx_start : out std_logic; -- indicates receipt of udp header
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udp_rxo : out udp_rx_type;
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-- IP RX signals
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ip_rx_hdr : out ipv4_rx_header_type;
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-- system signals
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rx_clk : in STD_LOGIC;
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tx_clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
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our_mac_address : in std_logic_vector (47 downto 0);
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control : in udp_control_type;
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-- status signals
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arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
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ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
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-- MAC Transmitter
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mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
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mac_tx_tvalid : out std_logic; -- tdata is valid
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mac_tx_tready : in std_logic; -- mac is ready to accept data
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mac_tx_tfirst : out std_logic; -- indicates first byte of frame
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mac_tx_tlast : out std_logic; -- indicates last byte of frame
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-- MAC Receiver
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mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
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mac_rx_tvalid : in std_logic; -- indicates tdata is valid
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mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
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mac_rx_tlast : in std_logic -- indicates last byte of the trame
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);
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END COMPONENT;
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type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT);
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type count_mode_type is (RST, INCR, HOLD);
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type set_clr_type is (SET, CLR, HOLD);
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--Inputs
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signal udp_tx_start_int : std_logic := '0';
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signal udp_tx_int : udp_tx_type;
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signal clk_int : std_logic := '0';
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signal reset : std_logic := '0';
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signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
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signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
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signal mac_tx_tready : std_logic := '0';
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signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
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signal mac_rx_tvalid : std_logic := '0';
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signal mac_rx_tlast : std_logic := '0';
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signal control : udp_control_type;
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--Outputs
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signal udp_rx_start_int : std_logic;
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signal udp_rx_int : udp_rx_type;
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signal ip_rx_hdr : ipv4_rx_header_type;
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signal udp_tx_result : std_logic_vector (1 downto 0);
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signal udp_tx_data_out_ready_int: std_logic;
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signal arp_pkt_count : std_logic_vector(7 downto 0);
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signal ip_pkt_count : std_logic_vector(7 downto 0);
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signal mac_tx_tdata : std_logic_vector(7 downto 0);
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signal mac_tx_tvalid : std_logic;
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signal mac_tx_tfirst : std_logic;
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signal mac_tx_tlast : std_logic;
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signal mac_rx_tready : std_logic;
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signal pbtx_led : std_logic;
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signal pbtx : std_logic := '0';
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-- state signals
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signal state : state_type;
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signal count : unsigned (7 downto 0);
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signal tx_hdr : udp_tx_header_type;
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signal tx_start_reg : std_logic;
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signal tx_started_reg : std_logic;
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signal tx_fin_reg : std_logic;
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-- control signals
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signal next_state : state_type;
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signal set_state : std_logic;
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signal set_count : count_mode_type;
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signal set_hdr : std_logic;
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signal set_tx_start : set_clr_type;
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signal set_last : std_logic;
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signal set_tx_started : set_clr_type;
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signal set_tx_fin : set_clr_type;
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signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0);
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-- Clock period definitions
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constant clk_period : time := 8 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: UDP_Complete_nomac
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generic map (
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CLOCK_FREQ => 10, -- artificially low count to enable pragmatic testing
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ARP_TIMEOUT => 20
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)
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PORT MAP (
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udp_tx_start => udp_tx_start_int,
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udp_txi => udp_tx_int,
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udp_tx_result => udp_tx_result,
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udp_tx_data_out_ready => udp_tx_data_out_ready_int,
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udp_rx_start => udp_rx_start_int,
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udp_rxo => udp_rx_int,
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ip_rx_hdr => ip_rx_hdr,
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rx_clk => clk_int,
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tx_clk => clk_int,
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reset => reset,
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our_ip_address => our_ip_address,
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our_mac_address => our_mac_address,
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control => control,
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arp_pkt_count => arp_pkt_count,
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ip_pkt_count => ip_pkt_count,
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mac_tx_tdata => mac_tx_tdata,
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mac_tx_tvalid => mac_tx_tvalid,
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mac_tx_tready => mac_tx_tready,
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mac_tx_tfirst => mac_tx_tfirst,
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mac_tx_tlast => mac_tx_tlast,
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mac_rx_tdata => mac_rx_tdata,
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mac_rx_tvalid => mac_rx_tvalid,
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mac_rx_tready => mac_rx_tready,
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mac_rx_tlast => mac_rx_tlast
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk_int <= '0';
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wait for clk_period/2;
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clk_int <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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our_ip_address <= x"c0a80509"; -- 192.168.5.9
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our_mac_address <= x"002320212223";
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control.ip_controls.arp_controls.clear_cache <= '0';
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mac_tx_tready <= '0';
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reset <= '1';
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wait for clk_period*10;
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reset <= '0';
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wait for clk_period*5;
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-- check reset conditions
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assert udp_tx_result = UDPTX_RESULT_NONE report "udp_tx_result not initialised correctly on reset";
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assert udp_tx_data_out_ready_int = '0' report "ip_udp_txitx.data.data_out_ready not initialised correctly on reset";
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assert mac_tx_tvalid = '0' report "mac_tx_tvalid not initialised correctly on reset";
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assert mac_tx_tlast = '0' report "mac_tx_tlast not initialised correctly on reset";
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assert arp_pkt_count = x"00" report "arp_pkt_count not initialised correctly on reset";
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assert ip_pkt_count = x"00" report "ip_pkt_count not initialised correctly on reset";
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assert udp_rx_start_int = '0' report "udp_rx_start not initialised correctly on reset";
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assert udp_rx_int.hdr.is_valid = '0' report "udp_rx_int.hdr.is_valid not initialised correctly on reset";
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assert udp_rx_int.hdr.data_length = x"0000" report "udp_rx_int.hdr.data_length not initialised correctly on reset";
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assert udp_rx_int.hdr.src_ip_addr = x"00000000" report "udp_rx_int.hdr.src_ip_addr not initialised correctly on reset";
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assert udp_rx_int.hdr.src_port = x"0000" report "udp_rx_int.hdr.src_port not initialised correctly on reset";
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assert udp_rx_int.hdr.dst_port = x"0000" report "udp_rx_int.hdr.dst_port not initialised correctly on reset";
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assert udp_rx_int.data.data_in = x"00" report "udp_rx_start.data.data_in not initialised correctly on reset";
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assert udp_rx_int.data.data_in_valid = '0' report "udp_rx_start.data.data_in_valid not initialised correctly on reset";
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assert udp_rx_int.data.data_in_last = '0' report "udp_rx_start.data.data_in_last not initialised correctly on reset";
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assert ip_rx_hdr.is_valid = '0' report "ip_rx_hdr.is_valid not initialised correctly on reset";
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assert ip_rx_hdr.protocol = x"00" report "ip_rx_hdr.protocol not initialised correctly on reset";
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assert ip_rx_hdr.data_length = x"0000" report "ip_rx_hdr.data_length not initialised correctly on reset";
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assert ip_rx_hdr.src_ip_addr = x"00000000" report "ip_rx_hdr.src_ip_addr not initialised correctly on reset";
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assert ip_rx_hdr.num_frame_errors = x"00" report "ip_rx_hdr.num_frame_errors not initialised correctly on reset";
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-- insert stimulus here
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------------
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-- TEST 1 -- send ARP request
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------------
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report "T1: Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1";
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mac_tx_tready <= '1';
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mac_rx_tvalid <= '1';
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-- dst MAC (bc)
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mac_rx_tdata <= x"ff"; wait for clk_period;
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mac_rx_tdata <= x"ff"; wait for clk_period;
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mac_rx_tdata <= x"ff"; wait for clk_period;
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mac_rx_tdata <= x"ff"; wait for clk_period;
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mac_rx_tdata <= x"ff"; wait for clk_period;
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mac_rx_tdata <= x"ff"; wait for clk_period;
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-- src MAC
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"23"; wait for clk_period;
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mac_rx_tdata <= x"18"; wait for clk_period;
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mac_rx_tdata <= x"29"; wait for clk_period;
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mac_rx_tdata <= x"26"; wait for clk_period;
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mac_rx_tdata <= x"7c"; wait for clk_period;
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-- type
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mac_rx_tdata <= x"08"; wait for clk_period;
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mac_rx_tdata <= x"06"; wait for clk_period;
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-- HW type
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"01"; wait for clk_period;
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-- Protocol type
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mac_rx_tdata <= x"08"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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-- HW size
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mac_rx_tdata <= x"06"; wait for clk_period;
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-- protocol size
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mac_rx_tdata <= x"04"; wait for clk_period;
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-- Opcode
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"01"; wait for clk_period;
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-- Sender MAC
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"23"; wait for clk_period;
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mac_rx_tdata <= x"18"; wait for clk_period;
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mac_rx_tdata <= x"29"; wait for clk_period;
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mac_rx_tdata <= x"26"; wait for clk_period;
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mac_rx_tdata <= x"7c"; wait for clk_period;
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-- Sender IP
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mac_rx_tdata <= x"c0"; wait for clk_period;
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mac_rx_tdata <= x"a8"; wait for clk_period;
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mac_rx_tdata <= x"05"; wait for clk_period;
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mac_rx_tdata <= x"01"; wait for clk_period;
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-- Target MAC
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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288 |
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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mac_rx_tdata <= x"00"; wait for clk_period;
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-- Target IP
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mac_rx_tdata <= x"c0"; wait for clk_period;
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mac_rx_tdata <= x"a8"; wait for clk_period;
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mac_rx_tdata <= x"05"; wait for clk_period;
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mac_rx_tdata <= x"09"; wait for clk_period;
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296 |
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mac_rx_tdata <= x"00"; wait for clk_period;
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297 |
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mac_rx_tdata <= x"00"; wait for clk_period;
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298 |
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mac_rx_tdata <= x"00"; wait for clk_period;
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299 |
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mac_rx_tlast <= '1';
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300 |
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mac_rx_tdata <= x"00"; wait for clk_period;
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301 |
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mac_rx_tlast <= '0';
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302 |
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mac_rx_tvalid <= '0';
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303 |
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304 |
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|
-- check we got the ARP pkt
|
305 |
|
|
assert arp_pkt_count = x"01" report "T1: arp_pkt_count wrong value";
|
306 |
|
|
assert ip_pkt_count = x"00" report "T1: ip_pkt_count wrong value";
|
307 |
|
|
assert udp_tx_result = UDPTX_RESULT_NONE report "T1: udp_tx_result wrong value";
|
308 |
|
|
assert udp_tx_data_out_ready_int = '0' report "T1: ip_udp_txitx.data.data_out_ready wrong value";
|
309 |
|
|
assert udp_rx_start_int = '0' report "T1: udp_rx_start wrong value";
|
310 |
|
|
assert udp_rx_int.hdr.is_valid = '0' report "T1: udp_rx_int.hdr.is_valid wrong value";
|
311 |
|
|
assert ip_rx_hdr.is_valid = '0' report "T1: ip_rx_hdr.is_valid wrong value";
|
312 |
|
|
|
313 |
|
|
-- check we tx a response
|
314 |
|
|
|
315 |
|
|
wait for clk_period*25;
|
316 |
|
|
assert mac_tx_tvalid = '1' report "T1: not transmitting a response";
|
317 |
|
|
wait for clk_period*25;
|
318 |
|
|
assert mac_tx_tvalid = '0' report "T1: tx held on for too long";
|
319 |
|
|
|
320 |
|
|
------------
|
321 |
|
|
-- TEST 2 -- send UDP pkt (same as sample from Java program)
|
322 |
|
|
------------
|
323 |
|
|
|
324 |
|
|
report "T2: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
|
325 |
|
|
|
326 |
|
|
mac_rx_tvalid <= '1';
|
327 |
|
|
-- dst MAC (bc)
|
328 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
329 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
330 |
|
|
mac_rx_tdata <= x"20"; wait for clk_period;
|
331 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
332 |
|
|
mac_rx_tdata <= x"22"; wait for clk_period;
|
333 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
334 |
|
|
-- src MAC
|
335 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
336 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
337 |
|
|
mac_rx_tdata <= x"18"; wait for clk_period;
|
338 |
|
|
mac_rx_tdata <= x"29"; wait for clk_period;
|
339 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
340 |
|
|
mac_rx_tdata <= x"7c"; wait for clk_period;
|
341 |
|
|
-- type
|
342 |
|
|
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
|
343 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
344 |
|
|
-- ver & HL / service type
|
345 |
|
|
mac_rx_tdata <= x"45"; wait for clk_period;
|
346 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
347 |
|
|
-- total len
|
348 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
349 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
350 |
|
|
-- ID
|
351 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
352 |
|
|
mac_rx_tdata <= x"7a"; wait for clk_period;
|
353 |
|
|
-- flags & frag
|
354 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
355 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
356 |
|
|
-- TTL
|
357 |
|
|
mac_rx_tdata <= x"80"; wait for clk_period;
|
358 |
|
|
-- Protocol
|
359 |
|
|
mac_rx_tdata <= x"11"; wait for clk_period;
|
360 |
|
|
-- Header CKS
|
361 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
362 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
363 |
|
|
-- SRC IP
|
364 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
365 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
366 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
367 |
|
|
mac_rx_tdata <= x"01"; wait for clk_period;
|
368 |
|
|
-- DST IP
|
369 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
370 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
371 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
372 |
|
|
mac_rx_tdata <= x"09"; wait for clk_period;
|
373 |
|
|
-- SRC port
|
374 |
|
|
mac_rx_tdata <= x"f4"; wait for clk_period;
|
375 |
|
|
mac_rx_tdata <= x"9a"; wait for clk_period;
|
376 |
|
|
-- DST port
|
377 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
378 |
|
|
mac_rx_tdata <= x"94"; wait for clk_period;
|
379 |
|
|
-- length
|
380 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
381 |
|
|
mac_rx_tdata <= x"0d"; wait for clk_period;
|
382 |
|
|
-- cks
|
383 |
|
|
mac_rx_tdata <= x"8b"; wait for clk_period;
|
384 |
|
|
mac_rx_tdata <= x"79"; wait for clk_period;
|
385 |
|
|
-- user data
|
386 |
|
|
mac_rx_tdata <= x"68"; wait for clk_period;
|
387 |
|
|
|
388 |
|
|
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
|
389 |
|
|
assert udp_rx_int.hdr.is_valid = '1' report "T2: udp_rx_int.hdr.is_valid not set";
|
390 |
|
|
assert udp_rx_int.hdr.data_length = x"0005" report "T2: udp_rx_int.hdr.data_length not set correctly";
|
391 |
|
|
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T2: udp_rx_int.hdr.src_ip_addr not set correctly";
|
392 |
|
|
assert udp_rx_int.hdr.src_port = x"f49a" report "T2: udp_rx_int.hdr.src_port not set correctly";
|
393 |
|
|
assert udp_rx_int.hdr.dst_port = x"2694" report "T2: udp_rx_int.hdr.dst_port not set correctly";
|
394 |
|
|
|
395 |
|
|
assert udp_rx_start_int = '1' report "T2: udp_rx_start not set";
|
396 |
|
|
assert udp_rx_int.data.data_in_valid = '1' report "T2: udp_rx_int.data.data_in_valid not set";
|
397 |
|
|
|
398 |
|
|
assert ip_rx_hdr.is_valid = '1' report "T2: ip_rx_hdr.is_valid not set";
|
399 |
|
|
assert ip_rx_hdr.protocol = x"11" report "T2: ip_rx_hdr.protocol not set correctly";
|
400 |
|
|
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T2: ip_rx.hdr.src_ip_addr not set correctly";
|
401 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T2: ip_rx.hdr.num_frame_errors not set correctly";
|
402 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T2: ip_rx.hdr.last_error_code not set correctly";
|
403 |
|
|
|
404 |
|
|
-- put the rest of the user data
|
405 |
|
|
mac_rx_tdata <= x"65"; wait for clk_period;
|
406 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
407 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
408 |
|
|
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
|
409 |
|
|
|
410 |
|
|
assert udp_rx_int.data.data_in_last = '1' report "T2: udp_rx_int.data.data_in_last not set";
|
411 |
|
|
|
412 |
|
|
mac_rx_tdata <= x"00";
|
413 |
|
|
mac_rx_tlast <= '0';
|
414 |
|
|
mac_rx_tvalid <= '0';
|
415 |
|
|
wait for clk_period;
|
416 |
|
|
|
417 |
|
|
assert udp_rx_int.data.data_in_valid = '0' report "T2: udp_rx_int.data.data_in_valid not cleared";
|
418 |
|
|
assert udp_rx_int.data.data_in_last = '0' report "T2: udp_rx_int.data.data_in_last not cleared";
|
419 |
|
|
assert udp_rx_start_int = '0' report "T2: udp_rx_start not cleared";
|
420 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T2: ip_rx_hdr.num_frame_errors non zero at end of test";
|
421 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T2: ip_rx_hdr.last_error_code indicates error at end of test";
|
422 |
|
|
assert ip_pkt_count = x"01" report "T2: ip pkt cnt incorrect";
|
423 |
|
|
|
424 |
|
|
wait for clk_period*20;
|
425 |
|
|
|
426 |
|
|
------------
|
427 |
|
|
-- TEST 3 -- send UDP pkt again (same as sample from Java program)
|
428 |
|
|
------------
|
429 |
|
|
|
430 |
|
|
report "T3: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
|
431 |
|
|
|
432 |
|
|
mac_rx_tvalid <= '1';
|
433 |
|
|
-- dst MAC (bc)
|
434 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
435 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
436 |
|
|
mac_rx_tdata <= x"20"; wait for clk_period;
|
437 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
438 |
|
|
mac_rx_tdata <= x"22"; wait for clk_period;
|
439 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
440 |
|
|
-- src MAC
|
441 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
442 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
443 |
|
|
mac_rx_tdata <= x"18"; wait for clk_period;
|
444 |
|
|
mac_rx_tdata <= x"29"; wait for clk_period;
|
445 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
446 |
|
|
mac_rx_tdata <= x"7c"; wait for clk_period;
|
447 |
|
|
-- type
|
448 |
|
|
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
|
449 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
450 |
|
|
-- ver & HL / service type
|
451 |
|
|
mac_rx_tdata <= x"45"; wait for clk_period;
|
452 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
453 |
|
|
-- total len
|
454 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
455 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
456 |
|
|
-- ID
|
457 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
458 |
|
|
mac_rx_tdata <= x"7a"; wait for clk_period;
|
459 |
|
|
-- flags & frag
|
460 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
461 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
462 |
|
|
-- TTL
|
463 |
|
|
mac_rx_tdata <= x"80"; wait for clk_period;
|
464 |
|
|
-- Protocol
|
465 |
|
|
mac_rx_tdata <= x"11"; wait for clk_period;
|
466 |
|
|
-- Header CKS
|
467 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
468 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
469 |
|
|
-- SRC IP
|
470 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
471 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
472 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
473 |
|
|
mac_rx_tdata <= x"01"; wait for clk_period;
|
474 |
|
|
-- DST IP
|
475 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
476 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
477 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
478 |
|
|
mac_rx_tdata <= x"09"; wait for clk_period;
|
479 |
|
|
-- SRC port
|
480 |
|
|
mac_rx_tdata <= x"f4"; wait for clk_period;
|
481 |
|
|
mac_rx_tdata <= x"9a"; wait for clk_period;
|
482 |
|
|
-- DST port
|
483 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
484 |
|
|
mac_rx_tdata <= x"94"; wait for clk_period;
|
485 |
|
|
-- length
|
486 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
487 |
|
|
mac_rx_tdata <= x"0d"; wait for clk_period;
|
488 |
|
|
-- cks
|
489 |
|
|
mac_rx_tdata <= x"8b"; wait for clk_period;
|
490 |
|
|
mac_rx_tdata <= x"79"; wait for clk_period;
|
491 |
|
|
-- user data
|
492 |
|
|
mac_rx_tdata <= x"68"; wait for clk_period;
|
493 |
|
|
|
494 |
|
|
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
|
495 |
|
|
assert udp_rx_int.hdr.is_valid = '1' report "T3: udp_rx_int.hdr.is_valid not set";
|
496 |
|
|
assert udp_rx_int.hdr.data_length = x"0005" report "T3: udp_rx_int.hdr.data_length not set correctly";
|
497 |
|
|
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T3: udp_rx_int.hdr.src_ip_addr not set correctly";
|
498 |
|
|
assert udp_rx_int.hdr.src_port = x"f49a" report "T3: udp_rx_int.hdr.src_port not set correctly";
|
499 |
|
|
assert udp_rx_int.hdr.dst_port = x"2694" report "T3: udp_rx_int.hdr.dst_port not set correctly";
|
500 |
|
|
|
501 |
|
|
assert udp_rx_start_int = '1' report "T3: udp_rx_start not set";
|
502 |
|
|
assert udp_rx_int.data.data_in_valid = '1' report "T3: udp_rx_int.data.data_in_valid not set";
|
503 |
|
|
|
504 |
|
|
assert ip_rx_hdr.is_valid = '1' report "T3: ip_rx_hdr.is_valid not set";
|
505 |
|
|
assert ip_rx_hdr.protocol = x"11" report "T3: ip_rx_hdr.protocol not set correctly";
|
506 |
|
|
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T3: ip_rx.hdr.src_ip_addr not set correctly";
|
507 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T3: ip_rx.hdr.num_frame_errors not set correctly";
|
508 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T3: ip_rx.hdr.last_error_code not set correctly";
|
509 |
|
|
|
510 |
|
|
-- put the rest of the user data
|
511 |
|
|
mac_rx_tdata <= x"65"; wait for clk_period;
|
512 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
513 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
514 |
|
|
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
|
515 |
|
|
|
516 |
|
|
assert udp_rx_int.data.data_in_last = '1' report "T3: udp_rx_int.data.data_in_last not set";
|
517 |
|
|
|
518 |
|
|
mac_rx_tdata <= x"00";
|
519 |
|
|
mac_rx_tlast <= '0';
|
520 |
|
|
mac_rx_tvalid <= '0';
|
521 |
|
|
wait for clk_period;
|
522 |
|
|
|
523 |
|
|
assert udp_rx_int.data.data_in_valid = '0' report "T3: udp_rx_int.data.data_in_valid not cleared";
|
524 |
|
|
assert udp_rx_int.data.data_in_last = '0' report "T3: udp_rx_int.data.data_in_last not cleared";
|
525 |
|
|
assert udp_rx_start_int = '0' report "T3: udp_rx_start not cleared";
|
526 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T3: ip_rx_hdr.num_frame_errors non zero at end of test";
|
527 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T3: ip_rx_hdr.last_error_code indicates error at end of test";
|
528 |
|
|
assert ip_pkt_count = x"02" report "T3: ip pkt cnt incorrect";
|
529 |
|
|
|
530 |
|
|
wait for clk_period*50;
|
531 |
|
|
|
532 |
|
|
------------
|
533 |
|
|
-- TEST 4 -- send UDP pkt with specific UDP data to force a broadcast tx in reply
|
534 |
|
|
------------
|
535 |
|
|
|
536 |
|
|
report "T4: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
|
537 |
|
|
|
538 |
|
|
mac_rx_tvalid <= '1';
|
539 |
|
|
-- dst MAC (bc)
|
540 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
541 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
542 |
|
|
mac_rx_tdata <= x"20"; wait for clk_period;
|
543 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
544 |
|
|
mac_rx_tdata <= x"22"; wait for clk_period;
|
545 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
546 |
|
|
-- src MAC
|
547 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
548 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
549 |
|
|
mac_rx_tdata <= x"18"; wait for clk_period;
|
550 |
|
|
mac_rx_tdata <= x"29"; wait for clk_period;
|
551 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
552 |
|
|
mac_rx_tdata <= x"7c"; wait for clk_period;
|
553 |
|
|
-- type
|
554 |
|
|
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
|
555 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
556 |
|
|
-- ver & HL / service type
|
557 |
|
|
mac_rx_tdata <= x"45"; wait for clk_period;
|
558 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
559 |
|
|
-- total len
|
560 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
561 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
562 |
|
|
-- ID
|
563 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
564 |
|
|
mac_rx_tdata <= x"7a"; wait for clk_period;
|
565 |
|
|
-- flags & frag
|
566 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
567 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
568 |
|
|
-- TTL
|
569 |
|
|
mac_rx_tdata <= x"80"; wait for clk_period;
|
570 |
|
|
-- Protocol
|
571 |
|
|
mac_rx_tdata <= x"11"; wait for clk_period;
|
572 |
|
|
-- Header CKS
|
573 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
574 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
575 |
|
|
-- SRC IP
|
576 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
577 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
578 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
579 |
|
|
mac_rx_tdata <= x"01"; wait for clk_period;
|
580 |
|
|
-- DST IP
|
581 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
582 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
583 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
584 |
|
|
mac_rx_tdata <= x"09"; wait for clk_period;
|
585 |
|
|
-- SRC port
|
586 |
|
|
mac_rx_tdata <= x"f4"; wait for clk_period;
|
587 |
|
|
mac_rx_tdata <= x"9a"; wait for clk_period;
|
588 |
|
|
-- DST port
|
589 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
590 |
|
|
mac_rx_tdata <= x"94"; wait for clk_period;
|
591 |
|
|
-- length
|
592 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
593 |
|
|
mac_rx_tdata <= x"0d"; wait for clk_period;
|
594 |
|
|
-- cks
|
595 |
|
|
mac_rx_tdata <= x"8b"; wait for clk_period;
|
596 |
|
|
mac_rx_tdata <= x"79"; wait for clk_period;
|
597 |
|
|
-- user data
|
598 |
|
|
mac_rx_tdata <= x"42"; wait for clk_period; -- First byte 'B' triggers a reply to broadcast addr
|
599 |
|
|
|
600 |
|
|
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
|
601 |
|
|
assert udp_rx_int.hdr.is_valid = '1' report "T4: udp_rx_int.hdr.is_valid not set";
|
602 |
|
|
assert udp_rx_int.hdr.data_length = x"0005" report "T4: udp_rx_int.hdr.data_length not set correctly";
|
603 |
|
|
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T4: udp_rx_int.hdr.src_ip_addr not set correctly";
|
604 |
|
|
assert udp_rx_int.hdr.src_port = x"f49a" report "T4: udp_rx_int.hdr.src_port not set correctly";
|
605 |
|
|
assert udp_rx_int.hdr.dst_port = x"2694" report "T4: udp_rx_int.hdr.dst_port not set correctly";
|
606 |
|
|
|
607 |
|
|
assert udp_rx_start_int = '1' report "T4: udp_rx_start not set";
|
608 |
|
|
assert udp_rx_int.data.data_in_valid = '1' report "T4: udp_rx_int.data.data_in_valid not set";
|
609 |
|
|
|
610 |
|
|
assert ip_rx_hdr.is_valid = '1' report "T4: ip_rx_hdr.is_valid not set";
|
611 |
|
|
assert ip_rx_hdr.protocol = x"11" report "T4: ip_rx_hdr.protocol not set correctly";
|
612 |
|
|
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T4: ip_rx.hdr.src_ip_addr not set correctly";
|
613 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T4: ip_rx.hdr.num_frame_errors not set correctly";
|
614 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T4: ip_rx.hdr.last_error_code not set correctly";
|
615 |
|
|
|
616 |
|
|
-- put the rest of the user data
|
617 |
|
|
mac_rx_tdata <= x"65"; wait for clk_period;
|
618 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
619 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
620 |
|
|
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
|
621 |
|
|
|
622 |
|
|
assert udp_rx_int.data.data_in_last = '1' report "T4: udp_rx_int.data.data_in_last not set";
|
623 |
|
|
|
624 |
|
|
mac_rx_tdata <= x"00";
|
625 |
|
|
mac_rx_tlast <= '0';
|
626 |
|
|
mac_rx_tvalid <= '0';
|
627 |
|
|
wait for clk_period;
|
628 |
|
|
|
629 |
|
|
report "T4: waiting for mac data tx";
|
630 |
|
|
wait until mac_tx_tvalid = '1';
|
631 |
|
|
report "T4: starting mac data tx";
|
632 |
|
|
wait for clk_period;
|
633 |
|
|
|
634 |
|
|
-- check the mac data being transmitted
|
635 |
|
|
assert mac_tx_tdata = x"ff" report "T4: incorrect dst mac 0"; wait for clk_period;
|
636 |
|
|
assert mac_tx_tdata = x"ff" report "T4: incorrect dst mac 1"; wait for clk_period;
|
637 |
|
|
assert mac_tx_tdata = x"ff" report "T4: incorrect dst mac 2"; wait for clk_period;
|
638 |
|
|
assert mac_tx_tdata = x"ff" report "T4: incorrect dst mac 3"; wait for clk_period;
|
639 |
|
|
assert mac_tx_tdata = x"ff" report "T4: incorrect dst mac 4"; wait for clk_period;
|
640 |
|
|
assert mac_tx_tdata = x"ff" report "T4: incorrect dst mac 5"; wait for clk_period;
|
641 |
|
|
|
642 |
|
|
assert mac_tx_tdata = x"00" report "T4: incorrect src mac 0"; wait for clk_period;
|
643 |
|
|
assert mac_tx_tdata = x"23" report "T4: incorrect src mac 1"; wait for clk_period;
|
644 |
|
|
assert mac_tx_tdata = x"20" report "T4: incorrect src mac 2"; wait for clk_period;
|
645 |
|
|
assert mac_tx_tdata = x"21" report "T4: incorrect src mac 3"; wait for clk_period;
|
646 |
|
|
assert mac_tx_tdata = x"22" report "T4: incorrect src mac 4"; wait for clk_period;
|
647 |
|
|
assert mac_tx_tdata = x"23" report "T4: incorrect src mac 5"; wait for clk_period;
|
648 |
|
|
|
649 |
|
|
assert mac_tx_tdata = x"08" report "T4: incorrect pkt_type 0"; wait for clk_period;
|
650 |
|
|
assert mac_tx_tdata = x"00" report "T4: incorrect pkt type 1"; wait for clk_period;
|
651 |
|
|
|
652 |
|
|
assert mac_tx_tdata = x"45" report "T4: incorrect ver.hlen"; wait for clk_period;
|
653 |
|
|
assert mac_tx_tdata = x"00" report "T4: incorrect srv type"; wait for clk_period;
|
654 |
|
|
assert mac_tx_tdata = x"00" report "T4: incorrect len 0"; wait for clk_period;
|
655 |
|
|
assert mac_tx_tdata = x"20" report "T4: incorrect len 1"; wait for clk_period;
|
656 |
|
|
|
657 |
|
|
assert mac_tx_tdata = x"00" report "T4: incorrect ident 0"; wait for clk_period;
|
658 |
|
|
assert mac_tx_tdata = x"00" report "T4: incorrect ident 1"; wait for clk_period;
|
659 |
|
|
assert mac_tx_tdata = x"00" report "T4: incorrect flag&frag 0"; wait for clk_period;
|
660 |
|
|
assert mac_tx_tdata = x"00" report "T4: incorrect flag&frag 1"; wait for clk_period;
|
661 |
|
|
|
662 |
|
|
assert mac_tx_tdata = x"80" report "T4: incorrect TTL"; wait for clk_period;
|
663 |
|
|
assert mac_tx_tdata = x"11" report "T4: incorrect protocol"; wait for clk_period;
|
664 |
|
|
assert mac_tx_tdata = x"75" report "T4: incorrect hdr.cks 0"; wait for clk_period;
|
665 |
|
|
assert mac_tx_tdata = x"1c" report "T4: incorrect hdr.cks 1"; wait for clk_period;
|
666 |
|
|
|
667 |
|
|
assert mac_tx_tdata = x"c0" report "T4: incorrect src ip 0"; wait for clk_period;
|
668 |
|
|
assert mac_tx_tdata = x"a8" report "T4: incorrect src ip 1"; wait for clk_period;
|
669 |
|
|
assert mac_tx_tdata = x"05" report "T4: incorrect src ip 2"; wait for clk_period;
|
670 |
|
|
assert mac_tx_tdata = x"09" report "T4: incorrect src ip 3"; wait for clk_period;
|
671 |
|
|
|
672 |
|
|
assert mac_tx_tdata = x"ff" report "T4: incorrect dst ip 0"; wait for clk_period;
|
673 |
|
|
assert mac_tx_tdata = x"ff" report "T4: incorrect dst ip 1"; wait for clk_period;
|
674 |
|
|
assert mac_tx_tdata = x"ff" report "T4: incorrect dst ip 2"; wait for clk_period;
|
675 |
|
|
assert mac_tx_tdata = x"ff" report "T4: incorrect dst ip 3"; wait for clk_period;
|
676 |
|
|
|
677 |
|
|
assert mac_tx_tdata = x"26" report "T4: incorrect src port 0"; wait for clk_period;
|
678 |
|
|
assert mac_tx_tdata = x"94" report "T4: incorrect src port 1"; wait for clk_period;
|
679 |
|
|
assert mac_tx_tdata = x"f4" report "T4: incorrect dst port 0"; wait for clk_period;
|
680 |
|
|
assert mac_tx_tdata = x"9a" report "T4: incorrect dst port 1"; wait for clk_period;
|
681 |
|
|
|
682 |
|
|
assert mac_tx_tdata = x"00" report "T4: incorrect udp len 0"; wait for clk_period;
|
683 |
|
|
assert mac_tx_tdata = x"0c" report "T4: incorrect udp len 1"; wait for clk_period;
|
684 |
|
|
assert mac_tx_tdata = x"00" report "T4: incorrect udp cks 0"; wait for clk_period;
|
685 |
|
|
assert mac_tx_tdata = x"00" report "T4: incorrect udp cks 1"; wait for clk_period;
|
686 |
|
|
|
687 |
|
|
assert mac_tx_tdata = x"40" report "T4: incorrect udp data 0"; wait for clk_period;
|
688 |
|
|
assert mac_tx_tdata = x"41" report "T4: incorrect udp data 1"; wait for clk_period;
|
689 |
|
|
|
690 |
|
|
assert mac_tx_tdata = x"42" report "T4: incorrect udp data 2";
|
691 |
|
|
assert mac_tx_tlast = '0' report "T4: tlast asserted too soon"; wait for clk_period;
|
692 |
|
|
assert mac_tx_tdata = x"43" report "T4: incorrect udp data 3";
|
693 |
|
|
assert mac_tx_tlast = '1' report "T4: tlast not asserted"; wait for clk_period;
|
694 |
|
|
|
695 |
|
|
assert udp_tx_result = IPTX_RESULT_SENT report "T4: TX did not complete";
|
696 |
|
|
|
697 |
|
|
assert udp_rx_int.data.data_in_valid = '0' report "T4: udp_rx_int.data.data_in_valid not cleared";
|
698 |
|
|
assert udp_rx_int.data.data_in_last = '0' report "T4: udp_rx_int.data.data_in_last not cleared";
|
699 |
|
|
assert udp_rx_start_int = '0' report "T4: udp_rx_start not cleared";
|
700 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T4: ip_rx_hdr.num_frame_errors non zero at end of test";
|
701 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T4: ip_rx_hdr.last_error_code indicates error at end of test";
|
702 |
|
|
assert ip_pkt_count = x"03" report "T4: ip pkt cnt incorrect";
|
703 |
|
|
|
704 |
|
|
------------
|
705 |
|
|
-- TEST 5 -- send UDP pkt with dst=bc addr to ensure we can receive broadcast tx
|
706 |
|
|
------------
|
707 |
|
|
|
708 |
|
|
report "T5: Send UDP IP pkt dst ip_address bc, from port f49a to port 2694";
|
709 |
|
|
|
710 |
|
|
mac_rx_tvalid <= '1';
|
711 |
|
|
-- dst MAC (bc)
|
712 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
713 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
714 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
715 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
716 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
717 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
718 |
|
|
-- src MAC
|
719 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
720 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
721 |
|
|
mac_rx_tdata <= x"18"; wait for clk_period;
|
722 |
|
|
mac_rx_tdata <= x"29"; wait for clk_period;
|
723 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
724 |
|
|
mac_rx_tdata <= x"7c"; wait for clk_period;
|
725 |
|
|
-- type
|
726 |
|
|
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
|
727 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
728 |
|
|
-- ver & HL / service type
|
729 |
|
|
mac_rx_tdata <= x"45"; wait for clk_period;
|
730 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
731 |
|
|
-- total len
|
732 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
733 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
734 |
|
|
-- ID
|
735 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
736 |
|
|
mac_rx_tdata <= x"7a"; wait for clk_period;
|
737 |
|
|
-- flags & frag
|
738 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
739 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
740 |
|
|
-- TTL
|
741 |
|
|
mac_rx_tdata <= x"80"; wait for clk_period;
|
742 |
|
|
-- Protocol
|
743 |
|
|
mac_rx_tdata <= x"11"; wait for clk_period;
|
744 |
|
|
-- Header CKS
|
745 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
746 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
747 |
|
|
-- SRC IP
|
748 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
749 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
750 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
751 |
|
|
mac_rx_tdata <= x"01"; wait for clk_period;
|
752 |
|
|
-- DST IP
|
753 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
754 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
755 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
756 |
|
|
mac_rx_tdata <= x"ff"; wait for clk_period;
|
757 |
|
|
-- SRC port
|
758 |
|
|
mac_rx_tdata <= x"f4"; wait for clk_period;
|
759 |
|
|
mac_rx_tdata <= x"9a"; wait for clk_period;
|
760 |
|
|
-- DST port
|
761 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
762 |
|
|
mac_rx_tdata <= x"94"; wait for clk_period;
|
763 |
|
|
-- length
|
764 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
765 |
|
|
mac_rx_tdata <= x"0d"; wait for clk_period;
|
766 |
|
|
-- cks
|
767 |
|
|
mac_rx_tdata <= x"8b"; wait for clk_period;
|
768 |
|
|
mac_rx_tdata <= x"79"; wait for clk_period;
|
769 |
|
|
-- user data
|
770 |
|
|
mac_rx_tdata <= x"68"; wait for clk_period;
|
771 |
|
|
|
772 |
|
|
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
|
773 |
|
|
assert udp_rx_int.hdr.is_valid = '1' report "T5: udp_rx_int.hdr.is_valid not set";
|
774 |
|
|
assert udp_rx_int.hdr.data_length = x"0005" report "T5: udp_rx_int.hdr.data_length not set correctly";
|
775 |
|
|
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T5: udp_rx_int.hdr.src_ip_addr not set correctly";
|
776 |
|
|
assert udp_rx_int.hdr.src_port = x"f49a" report "T5: udp_rx_int.hdr.src_port not set correctly";
|
777 |
|
|
assert udp_rx_int.hdr.dst_port = x"2694" report "T5: udp_rx_int.hdr.dst_port not set correctly";
|
778 |
|
|
|
779 |
|
|
assert udp_rx_start_int = '1' report "T5: udp_rx_start not set";
|
780 |
|
|
assert udp_rx_int.data.data_in_valid = '1' report "T5: udp_rx_int.data.data_in_valid not set";
|
781 |
|
|
|
782 |
|
|
assert ip_rx_hdr.is_valid = '1' report "T5: ip_rx_hdr.is_valid not set";
|
783 |
|
|
assert ip_rx_hdr.protocol = x"11" report "T5: ip_rx_hdr.protocol not set correctly";
|
784 |
|
|
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T5: ip_rx.hdr.src_ip_addr not set correctly";
|
785 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T5: ip_rx.hdr.num_frame_errors not set correctly";
|
786 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T5: ip_rx.hdr.last_error_code not set correctly";
|
787 |
|
|
|
788 |
|
|
-- put the rest of the user data
|
789 |
|
|
mac_rx_tdata <= x"65"; wait for clk_period;
|
790 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
791 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
792 |
|
|
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
|
793 |
|
|
|
794 |
|
|
assert udp_rx_int.data.data_in_last = '1' report "T5: udp_rx_int.data.data_in_last not set";
|
795 |
|
|
|
796 |
|
|
mac_rx_tdata <= x"00";
|
797 |
|
|
mac_rx_tlast <= '0';
|
798 |
|
|
mac_rx_tvalid <= '0';
|
799 |
|
|
|
800 |
|
|
report "T5: waiting for mac data tx";
|
801 |
|
|
if mac_tx_tvalid = '0' then
|
802 |
|
|
wait until mac_tx_tvalid = '1';
|
803 |
|
|
wait for clk_period;
|
804 |
|
|
end if;
|
805 |
|
|
report "T5: starting mac data tx";
|
806 |
|
|
|
807 |
|
|
-- check the mac data being transmitted
|
808 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect dst mac 0"; wait for clk_period;
|
809 |
|
|
assert mac_tx_tdata = x"23" report "T5: incorrect dst mac 1"; wait for clk_period;
|
810 |
|
|
assert mac_tx_tdata = x"18" report "T5: incorrect dst mac 2"; wait for clk_period;
|
811 |
|
|
assert mac_tx_tdata = x"29" report "T5: incorrect dst mac 3"; wait for clk_period;
|
812 |
|
|
assert mac_tx_tdata = x"26" report "T5: incorrect dst mac 4"; wait for clk_period;
|
813 |
|
|
assert mac_tx_tdata = x"7c" report "T5: incorrect dst mac 5"; wait for clk_period;
|
814 |
|
|
|
815 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect src mac 0"; wait for clk_period;
|
816 |
|
|
assert mac_tx_tdata = x"23" report "T5: incorrect src mac 1"; wait for clk_period;
|
817 |
|
|
assert mac_tx_tdata = x"20" report "T5: incorrect src mac 2"; wait for clk_period;
|
818 |
|
|
assert mac_tx_tdata = x"21" report "T5: incorrect src mac 3"; wait for clk_period;
|
819 |
|
|
assert mac_tx_tdata = x"22" report "T5: incorrect src mac 4"; wait for clk_period;
|
820 |
|
|
assert mac_tx_tdata = x"23" report "T5: incorrect src mac 5"; wait for clk_period;
|
821 |
|
|
|
822 |
|
|
assert mac_tx_tdata = x"08" report "T5: incorrect pkt_type 0"; wait for clk_period;
|
823 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect pkt type 1"; wait for clk_period;
|
824 |
|
|
|
825 |
|
|
assert mac_tx_tdata = x"45" report "T5: incorrect ver.hlen"; wait for clk_period;
|
826 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect srv type"; wait for clk_period;
|
827 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect len 0"; wait for clk_period;
|
828 |
|
|
assert mac_tx_tdata = x"20" report "T5: incorrect len 1"; wait for clk_period;
|
829 |
|
|
|
830 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect ident 0"; wait for clk_period;
|
831 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect ident 1"; wait for clk_period;
|
832 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect flag&frag 0"; wait for clk_period;
|
833 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect flag&frag 1"; wait for clk_period;
|
834 |
|
|
|
835 |
|
|
assert mac_tx_tdata = x"80" report "T5: incorrect TTL"; wait for clk_period;
|
836 |
|
|
assert mac_tx_tdata = x"11" report "T5: incorrect protocol"; wait for clk_period;
|
837 |
|
|
assert mac_tx_tdata = x"af" report "T5: incorrect hdr.cks 0"; wait for clk_period;
|
838 |
|
|
assert mac_tx_tdata = x"72" report "T5: incorrect hdr.cks 1"; wait for clk_period;
|
839 |
|
|
|
840 |
|
|
assert mac_tx_tdata = x"c0" report "T5: incorrect src ip 0"; wait for clk_period;
|
841 |
|
|
assert mac_tx_tdata = x"a8" report "T5: incorrect src ip 1"; wait for clk_period;
|
842 |
|
|
assert mac_tx_tdata = x"05" report "T5: incorrect src ip 2"; wait for clk_period;
|
843 |
|
|
assert mac_tx_tdata = x"09" report "T5: incorrect src ip 3"; wait for clk_period;
|
844 |
|
|
|
845 |
|
|
assert mac_tx_tdata = x"c0" report "T5: incorrect dst ip 0"; wait for clk_period;
|
846 |
|
|
assert mac_tx_tdata = x"a8" report "T5: incorrect dst ip 1"; wait for clk_period;
|
847 |
|
|
assert mac_tx_tdata = x"05" report "T5: incorrect dst ip 2"; wait for clk_period;
|
848 |
|
|
assert mac_tx_tdata = x"01" report "T5: incorrect dst ip 3"; wait for clk_period;
|
849 |
|
|
|
850 |
|
|
assert mac_tx_tdata = x"26" report "T5: incorrect src port 0"; wait for clk_period;
|
851 |
|
|
assert mac_tx_tdata = x"94" report "T5: incorrect src port 1"; wait for clk_period;
|
852 |
|
|
assert mac_tx_tdata = x"f4" report "T5: incorrect dst port 0"; wait for clk_period;
|
853 |
|
|
assert mac_tx_tdata = x"9a" report "T5: incorrect dst port 1"; wait for clk_period;
|
854 |
|
|
|
855 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect udp len 0"; wait for clk_period;
|
856 |
|
|
assert mac_tx_tdata = x"0c" report "T5: incorrect udp len 1"; wait for clk_period;
|
857 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect udp cks 0"; wait for clk_period;
|
858 |
|
|
assert mac_tx_tdata = x"00" report "T5: incorrect udp cks 1"; wait for clk_period;
|
859 |
|
|
|
860 |
|
|
assert mac_tx_tdata = x"50" report "T5: incorrect udp data 0"; wait for clk_period;
|
861 |
|
|
assert mac_tx_tdata = x"51" report "T5: incorrect udp data 1"; wait for clk_period;
|
862 |
|
|
|
863 |
|
|
assert mac_tx_tdata = x"52" report "T5: incorrect udp data 2";
|
864 |
|
|
assert mac_tx_tlast = '0' report "T5: tlast asserted too soon"; wait for clk_period;
|
865 |
|
|
assert mac_tx_tdata = x"53" report "T5: incorrect udp data 3";
|
866 |
|
|
assert mac_tx_tlast = '1' report "T5: tlast not asserted"; wait for clk_period;
|
867 |
|
|
|
868 |
|
|
assert udp_tx_result = IPTX_RESULT_SENT report "T5: TX did not complete";
|
869 |
|
|
|
870 |
|
|
assert udp_rx_int.data.data_in_valid = '0' report "T5: udp_rx_int.data.data_in_valid not cleared";
|
871 |
|
|
assert udp_rx_int.data.data_in_last = '0' report "T5: udp_rx_int.data.data_in_last not cleared";
|
872 |
|
|
assert udp_rx_start_int = '0' report "T5: udp_rx_start not cleared";
|
873 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T5: ip_rx_hdr.num_frame_errors non zero at end of test";
|
874 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T5: ip_rx_hdr.last_error_code indicates error at end of test";
|
875 |
|
|
assert ip_pkt_count = x"04" report "T5: ip pkt cnt incorrect";
|
876 |
|
|
|
877 |
|
|
|
878 |
|
|
------------
|
879 |
|
|
-- TEST 6 -- send UDP pkt with data to trigger the sending of a pkt to unknown IP addr to force an ARP timeout
|
880 |
|
|
------------
|
881 |
|
|
|
882 |
|
|
report "T6: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694 with data x43 to trig tx to unknown IP";
|
883 |
|
|
|
884 |
|
|
mac_rx_tvalid <= '1';
|
885 |
|
|
-- dst MAC (bc)
|
886 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
887 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
888 |
|
|
mac_rx_tdata <= x"20"; wait for clk_period;
|
889 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
890 |
|
|
mac_rx_tdata <= x"22"; wait for clk_period;
|
891 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
892 |
|
|
-- src MAC
|
893 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
894 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
895 |
|
|
mac_rx_tdata <= x"18"; wait for clk_period;
|
896 |
|
|
mac_rx_tdata <= x"29"; wait for clk_period;
|
897 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
898 |
|
|
mac_rx_tdata <= x"7c"; wait for clk_period;
|
899 |
|
|
-- type
|
900 |
|
|
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
|
901 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
902 |
|
|
-- ver & HL / service type
|
903 |
|
|
mac_rx_tdata <= x"45"; wait for clk_period;
|
904 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
905 |
|
|
-- total len
|
906 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
907 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
908 |
|
|
-- ID
|
909 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
910 |
|
|
mac_rx_tdata <= x"7a"; wait for clk_period;
|
911 |
|
|
-- flags & frag
|
912 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
913 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
914 |
|
|
-- TTL
|
915 |
|
|
mac_rx_tdata <= x"80"; wait for clk_period;
|
916 |
|
|
-- Protocol
|
917 |
|
|
mac_rx_tdata <= x"11"; wait for clk_period;
|
918 |
|
|
-- Header CKS
|
919 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
920 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
921 |
|
|
-- SRC IP
|
922 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
923 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
924 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
925 |
|
|
mac_rx_tdata <= x"01"; wait for clk_period;
|
926 |
|
|
-- DST IP
|
927 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
928 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
929 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
930 |
|
|
mac_rx_tdata <= x"09"; wait for clk_period;
|
931 |
|
|
-- SRC port
|
932 |
|
|
mac_rx_tdata <= x"f4"; wait for clk_period;
|
933 |
|
|
mac_rx_tdata <= x"9a"; wait for clk_period;
|
934 |
|
|
-- DST port
|
935 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
936 |
|
|
mac_rx_tdata <= x"94"; wait for clk_period;
|
937 |
|
|
-- length
|
938 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
939 |
|
|
mac_rx_tdata <= x"0d"; wait for clk_period;
|
940 |
|
|
-- cks
|
941 |
|
|
mac_rx_tdata <= x"8b"; wait for clk_period;
|
942 |
|
|
mac_rx_tdata <= x"79"; wait for clk_period;
|
943 |
|
|
-- user data
|
944 |
|
|
mac_rx_tdata <= x"43"; wait for clk_period; -- First byte 'C' triggers a reply to unknown addr
|
945 |
|
|
|
946 |
|
|
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
|
947 |
|
|
assert udp_rx_int.hdr.is_valid = '1' report "T6: udp_rx_int.hdr.is_valid not set";
|
948 |
|
|
assert udp_rx_int.hdr.data_length = x"0005" report "T6: udp_rx_int.hdr.data_length not set correctly";
|
949 |
|
|
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T6: udp_rx_int.hdr.src_ip_addr not set correctly";
|
950 |
|
|
assert udp_rx_int.hdr.src_port = x"f49a" report "T6: udp_rx_int.hdr.src_port not set correctly";
|
951 |
|
|
assert udp_rx_int.hdr.dst_port = x"2694" report "T6: udp_rx_int.hdr.dst_port not set correctly";
|
952 |
|
|
|
953 |
|
|
assert udp_rx_start_int = '1' report "T6: udp_rx_start not set";
|
954 |
|
|
assert udp_rx_int.data.data_in_valid = '1' report "T6: udp_rx_int.data.data_in_valid not set";
|
955 |
|
|
|
956 |
|
|
assert ip_rx_hdr.is_valid = '1' report "T6: ip_rx_hdr.is_valid not set";
|
957 |
|
|
assert ip_rx_hdr.protocol = x"11" report "T6: ip_rx_hdr.protocol not set correctly";
|
958 |
|
|
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T6: ip_rx.hdr.src_ip_addr not set correctly";
|
959 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T6: ip_rx.hdr.num_frame_errors not set correctly";
|
960 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T6: ip_rx.hdr.last_error_code not set correctly";
|
961 |
|
|
|
962 |
|
|
-- put the rest of the user data
|
963 |
|
|
mac_rx_tdata <= x"65"; wait for clk_period;
|
964 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
965 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
966 |
|
|
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
|
967 |
|
|
|
968 |
|
|
assert udp_rx_int.data.data_in_last = '1' report "T6: udp_rx_int.data.data_in_last not set";
|
969 |
|
|
|
970 |
|
|
mac_rx_tdata <= x"00";
|
971 |
|
|
mac_rx_tlast <= '0';
|
972 |
|
|
mac_rx_tvalid <= '0';
|
973 |
|
|
wait for clk_period;
|
974 |
|
|
|
975 |
|
|
report "T6: waiting for mac data tx";
|
976 |
|
|
wait until mac_tx_tvalid = '1';
|
977 |
|
|
report "T6: starting mac data tx";
|
978 |
|
|
wait for clk_period;
|
979 |
|
|
|
980 |
|
|
-- check the mac data being transmitted is valid ARP request
|
981 |
|
|
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 0"; wait for clk_period;
|
982 |
|
|
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 1"; wait for clk_period;
|
983 |
|
|
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 2"; wait for clk_period;
|
984 |
|
|
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 3"; wait for clk_period;
|
985 |
|
|
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 4"; wait for clk_period;
|
986 |
|
|
assert mac_tx_tdata = x"ff" report "T6: incorrect dst mac 5"; wait for clk_period;
|
987 |
|
|
|
988 |
|
|
assert mac_tx_tdata = x"00" report "T6: incorrect src mac 0"; wait for clk_period;
|
989 |
|
|
assert mac_tx_tdata = x"23" report "T6: incorrect src mac 1"; wait for clk_period;
|
990 |
|
|
assert mac_tx_tdata = x"20" report "T6: incorrect src mac 2"; wait for clk_period;
|
991 |
|
|
assert mac_tx_tdata = x"21" report "T6: incorrect src mac 3"; wait for clk_period;
|
992 |
|
|
assert mac_tx_tdata = x"22" report "T6: incorrect src mac 4"; wait for clk_period;
|
993 |
|
|
assert mac_tx_tdata = x"23" report "T6: incorrect src mac 5"; wait for clk_period;
|
994 |
|
|
|
995 |
|
|
assert mac_tx_tdata = x"08" report "T6: incorrect pkt_type 0"; wait for clk_period;
|
996 |
|
|
assert mac_tx_tdata = x"06" report "T6: incorrect pkt type 1"; wait for clk_period;
|
997 |
|
|
|
998 |
|
|
assert mac_tx_tdata = x"00" report "T6: incorrect HW type.0"; wait for clk_period;
|
999 |
|
|
assert mac_tx_tdata = x"01" report "T6: incorrect HW type.1"; wait for clk_period;
|
1000 |
|
|
assert mac_tx_tdata = x"08" report "T6: incorrect prot.0"; wait for clk_period;
|
1001 |
|
|
assert mac_tx_tdata = x"00" report "T6: incorrect prot.1"; wait for clk_period;
|
1002 |
|
|
assert mac_tx_tdata = x"06" report "T6: incorrect HW size"; wait for clk_period;
|
1003 |
|
|
assert mac_tx_tdata = x"04" report "T6: incorrect prot size"; wait for clk_period;
|
1004 |
|
|
assert mac_tx_tdata = x"00" report "T6: incorrect opcode.0"; wait for clk_period;
|
1005 |
|
|
assert mac_tx_tdata = x"01" report "T6: incorrect opcode.1"; wait for clk_period;
|
1006 |
|
|
|
1007 |
|
|
assert mac_tx_tdata = x"00" report "T6: incorrect sndr mac 0"; wait for clk_period;
|
1008 |
|
|
assert mac_tx_tdata = x"23" report "T6: incorrect sndr mac 1"; wait for clk_period;
|
1009 |
|
|
assert mac_tx_tdata = x"20" report "T6: incorrect sndr mac 2"; wait for clk_period;
|
1010 |
|
|
assert mac_tx_tdata = x"21" report "T6: incorrect sndr mac 3"; wait for clk_period;
|
1011 |
|
|
assert mac_tx_tdata = x"22" report "T6: incorrect sndr mac 4"; wait for clk_period;
|
1012 |
|
|
assert mac_tx_tdata = x"23" report "T6: incorrect sndr mac 5"; wait for clk_period;
|
1013 |
|
|
|
1014 |
|
|
assert mac_tx_tdata = x"c0" report "T6: incorrect sndr ip 0"; wait for clk_period;
|
1015 |
|
|
assert mac_tx_tdata = x"a8" report "T6: incorrect sndr ip 1"; wait for clk_period;
|
1016 |
|
|
assert mac_tx_tdata = x"05" report "T6: incorrect sndr ip 2"; wait for clk_period;
|
1017 |
|
|
assert mac_tx_tdata = x"09" report "T6: incorrect sndr ip 3"; wait for clk_period;
|
1018 |
|
|
|
1019 |
18 |
pjf |
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 0"; wait for clk_period;
|
1020 |
|
|
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 1"; wait for clk_period;
|
1021 |
|
|
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 2"; wait for clk_period;
|
1022 |
|
|
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 3"; wait for clk_period;
|
1023 |
|
|
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 4"; wait for clk_period;
|
1024 |
|
|
assert mac_tx_tdata = x"FF" report "T6: incorrect trg mac 5"; wait for clk_period;
|
1025 |
11 |
pjf |
|
1026 |
|
|
assert mac_tx_tdata = x"c0" report "T6: incorrect trg ip 0"; wait for clk_period;
|
1027 |
|
|
assert mac_tx_tdata = x"bb" report "T6: incorrect trg ip 1"; wait for clk_period;
|
1028 |
|
|
assert mac_tx_tdata = x"cc" report "T6: incorrect trg ip 2";
|
1029 |
|
|
assert mac_tx_tlast = '0' report "T6: tlast asserted too soon";
|
1030 |
|
|
wait for clk_period;
|
1031 |
|
|
|
1032 |
|
|
assert mac_tx_tdata = x"dd" report "T6: incorrect trg ip 3";
|
1033 |
|
|
assert mac_tx_tlast = '1' report "T6: tlast should be set";
|
1034 |
|
|
wait for clk_period;
|
1035 |
|
|
|
1036 |
|
|
assert udp_tx_result = IPTX_RESULT_SENDING report "T6: TX should still be in sending phase";
|
1037 |
|
|
|
1038 |
|
|
assert udp_rx_int.data.data_in_valid = '0' report "T6: udp_rx_int.data.data_in_valid not cleared";
|
1039 |
|
|
assert udp_rx_int.data.data_in_last = '0' report "T6: udp_rx_int.data.data_in_last not cleared";
|
1040 |
|
|
assert udp_rx_start_int = '0' report "T6: udp_rx_start not cleared";
|
1041 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T6: ip_rx_hdr.num_frame_errors non zero at end of test";
|
1042 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T6: ip_rx_hdr.last_error_code indicates error at end of test";
|
1043 |
|
|
assert ip_pkt_count = x"05" report "T6: ip pkt cnt incorrect";
|
1044 |
|
|
|
1045 |
|
|
-- check for error on tx as a result of ARP timeout
|
1046 |
|
|
|
1047 |
|
|
wait for clk_period*10*20;
|
1048 |
|
|
assert udp_tx_result = IPTX_RESULT_ERR report "T6: TX should resulkt in error (arp timeout)";
|
1049 |
|
|
|
1050 |
|
|
wait for clk_period*10;
|
1051 |
|
|
|
1052 |
|
|
------------
|
1053 |
|
|
-- TEST 7 -- send UDP pkt again to ensure that we can rx a pkt and tx after a timeout
|
1054 |
|
|
------------
|
1055 |
|
|
|
1056 |
|
|
report "T7: Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694";
|
1057 |
|
|
|
1058 |
|
|
mac_rx_tvalid <= '1';
|
1059 |
|
|
-- dst MAC (bc)
|
1060 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
1061 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
1062 |
|
|
mac_rx_tdata <= x"20"; wait for clk_period;
|
1063 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
1064 |
|
|
mac_rx_tdata <= x"22"; wait for clk_period;
|
1065 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
1066 |
|
|
-- src MAC
|
1067 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
1068 |
|
|
mac_rx_tdata <= x"23"; wait for clk_period;
|
1069 |
|
|
mac_rx_tdata <= x"18"; wait for clk_period;
|
1070 |
|
|
mac_rx_tdata <= x"29"; wait for clk_period;
|
1071 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
1072 |
|
|
mac_rx_tdata <= x"7c"; wait for clk_period;
|
1073 |
|
|
-- type
|
1074 |
|
|
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
|
1075 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
1076 |
|
|
-- ver & HL / service type
|
1077 |
|
|
mac_rx_tdata <= x"45"; wait for clk_period;
|
1078 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
1079 |
|
|
-- total len
|
1080 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
1081 |
|
|
mac_rx_tdata <= x"21"; wait for clk_period;
|
1082 |
|
|
-- ID
|
1083 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
1084 |
|
|
mac_rx_tdata <= x"7a"; wait for clk_period;
|
1085 |
|
|
-- flags & frag
|
1086 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
1087 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
1088 |
|
|
-- TTL
|
1089 |
|
|
mac_rx_tdata <= x"80"; wait for clk_period;
|
1090 |
|
|
-- Protocol
|
1091 |
|
|
mac_rx_tdata <= x"11"; wait for clk_period;
|
1092 |
|
|
-- Header CKS
|
1093 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
1094 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
1095 |
|
|
-- SRC IP
|
1096 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
1097 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
1098 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
1099 |
|
|
mac_rx_tdata <= x"01"; wait for clk_period;
|
1100 |
|
|
-- DST IP
|
1101 |
|
|
mac_rx_tdata <= x"c0"; wait for clk_period;
|
1102 |
|
|
mac_rx_tdata <= x"a8"; wait for clk_period;
|
1103 |
|
|
mac_rx_tdata <= x"05"; wait for clk_period;
|
1104 |
|
|
mac_rx_tdata <= x"09"; wait for clk_period;
|
1105 |
|
|
-- SRC port
|
1106 |
|
|
mac_rx_tdata <= x"f4"; wait for clk_period;
|
1107 |
|
|
mac_rx_tdata <= x"9a"; wait for clk_period;
|
1108 |
|
|
-- DST port
|
1109 |
|
|
mac_rx_tdata <= x"26"; wait for clk_period;
|
1110 |
|
|
mac_rx_tdata <= x"94"; wait for clk_period;
|
1111 |
|
|
-- length
|
1112 |
|
|
mac_rx_tdata <= x"00"; wait for clk_period;
|
1113 |
|
|
mac_rx_tdata <= x"0d"; wait for clk_period;
|
1114 |
|
|
-- cks
|
1115 |
|
|
mac_rx_tdata <= x"8b"; wait for clk_period;
|
1116 |
|
|
mac_rx_tdata <= x"79"; wait for clk_period;
|
1117 |
|
|
-- user data
|
1118 |
|
|
mac_rx_tdata <= x"68"; wait for clk_period;
|
1119 |
|
|
|
1120 |
|
|
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
|
1121 |
|
|
assert udp_rx_int.hdr.is_valid = '1' report "T7: udp_rx_int.hdr.is_valid not set";
|
1122 |
|
|
assert udp_rx_int.hdr.data_length = x"0005" report "T7: udp_rx_int.hdr.data_length not set correctly";
|
1123 |
|
|
assert udp_rx_int.hdr.src_ip_addr = x"c0a80501" report "T7: udp_rx_int.hdr.src_ip_addr not set correctly";
|
1124 |
|
|
assert udp_rx_int.hdr.src_port = x"f49a" report "T7: udp_rx_int.hdr.src_port not set correctly";
|
1125 |
|
|
assert udp_rx_int.hdr.dst_port = x"2694" report "T7: udp_rx_int.hdr.dst_port not set correctly";
|
1126 |
|
|
|
1127 |
|
|
assert udp_rx_start_int = '1' report "T7: udp_rx_start not set";
|
1128 |
|
|
assert udp_rx_int.data.data_in_valid = '1' report "T7: udp_rx_int.data.data_in_valid not set";
|
1129 |
|
|
|
1130 |
|
|
assert ip_rx_hdr.is_valid = '1' report "T7: ip_rx_hdr.is_valid not set";
|
1131 |
|
|
assert ip_rx_hdr.protocol = x"11" report "T7: ip_rx_hdr.protocol not set correctly";
|
1132 |
|
|
assert ip_rx_hdr.src_ip_addr = x"c0a80501" report "T7: ip_rx.hdr.src_ip_addr not set correctly";
|
1133 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T7: ip_rx.hdr.num_frame_errors not set correctly";
|
1134 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T7: ip_rx.hdr.last_error_code not set correctly";
|
1135 |
|
|
|
1136 |
|
|
-- put the rest of the user data
|
1137 |
|
|
mac_rx_tdata <= x"65"; wait for clk_period;
|
1138 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
1139 |
|
|
mac_rx_tdata <= x"6c"; wait for clk_period;
|
1140 |
|
|
mac_rx_tdata <= x"6f"; mac_rx_tlast <= '1'; wait for clk_period;
|
1141 |
|
|
|
1142 |
|
|
assert udp_rx_int.data.data_in_last = '1' report "T7: udp_rx_int.data.data_in_last not set";
|
1143 |
|
|
|
1144 |
|
|
mac_rx_tdata <= x"00";
|
1145 |
|
|
mac_rx_tlast <= '0';
|
1146 |
|
|
mac_rx_tvalid <= '0';
|
1147 |
|
|
wait for clk_period*2;
|
1148 |
|
|
|
1149 |
|
|
-- the mac address will be cached, so udp tx should occur straight away
|
1150 |
|
|
assert udp_tx_result = IPTX_RESULT_SENDING report "T7: TX should be sending";
|
1151 |
|
|
|
1152 |
|
|
report "T7: waiting for mac data tx";
|
1153 |
|
|
if mac_tx_tvalid = '0' then
|
1154 |
|
|
wait until mac_tx_tvalid = '1';
|
1155 |
|
|
wait for clk_period;
|
1156 |
|
|
end if;
|
1157 |
|
|
report "T7: starting mac data tx";
|
1158 |
|
|
|
1159 |
|
|
-- check the mac data being transmitted
|
1160 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect dst mac 0"; wait for clk_period;
|
1161 |
|
|
assert mac_tx_tdata = x"23" report "T7: incorrect dst mac 1"; wait for clk_period;
|
1162 |
|
|
assert mac_tx_tdata = x"18" report "T7: incorrect dst mac 2"; wait for clk_period;
|
1163 |
|
|
assert mac_tx_tdata = x"29" report "T7: incorrect dst mac 3"; wait for clk_period;
|
1164 |
|
|
assert mac_tx_tdata = x"26" report "T7: incorrect dst mac 4"; wait for clk_period;
|
1165 |
|
|
assert mac_tx_tdata = x"7c" report "T7: incorrect dst mac 5"; wait for clk_period;
|
1166 |
|
|
|
1167 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect src mac 0"; wait for clk_period;
|
1168 |
|
|
assert mac_tx_tdata = x"23" report "T7: incorrect src mac 1"; wait for clk_period;
|
1169 |
|
|
assert mac_tx_tdata = x"20" report "T7: incorrect src mac 2"; wait for clk_period;
|
1170 |
|
|
assert mac_tx_tdata = x"21" report "T7: incorrect src mac 3"; wait for clk_period;
|
1171 |
|
|
assert mac_tx_tdata = x"22" report "T7: incorrect src mac 4"; wait for clk_period;
|
1172 |
|
|
assert mac_tx_tdata = x"23" report "T7: incorrect src mac 5"; wait for clk_period;
|
1173 |
|
|
|
1174 |
|
|
assert mac_tx_tdata = x"08" report "T7: incorrect pkt_type 0"; wait for clk_period;
|
1175 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect pkt type 1"; wait for clk_period;
|
1176 |
|
|
|
1177 |
|
|
assert mac_tx_tdata = x"45" report "T7: incorrect ver.hlen"; wait for clk_period;
|
1178 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect srv type"; wait for clk_period;
|
1179 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect len 0"; wait for clk_period;
|
1180 |
|
|
assert mac_tx_tdata = x"20" report "T7: incorrect len 1"; wait for clk_period;
|
1181 |
|
|
|
1182 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect ident 0"; wait for clk_period;
|
1183 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect ident 1"; wait for clk_period;
|
1184 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect flag&frag 0"; wait for clk_period;
|
1185 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect flag&frag 1"; wait for clk_period;
|
1186 |
|
|
|
1187 |
|
|
assert mac_tx_tdata = x"80" report "T7: incorrect TTL"; wait for clk_period;
|
1188 |
|
|
assert mac_tx_tdata = x"11" report "T7: incorrect protocol"; wait for clk_period;
|
1189 |
|
|
assert mac_tx_tdata = x"af" report "T7: incorrect hdr.cks 0"; wait for clk_period;
|
1190 |
|
|
assert mac_tx_tdata = x"72" report "T7: incorrect hdr.cks 1"; wait for clk_period;
|
1191 |
|
|
|
1192 |
|
|
assert mac_tx_tdata = x"c0" report "T7: incorrect src ip 0"; wait for clk_period;
|
1193 |
|
|
assert mac_tx_tdata = x"a8" report "T7: incorrect src ip 1"; wait for clk_period;
|
1194 |
|
|
assert mac_tx_tdata = x"05" report "T7: incorrect src ip 2"; wait for clk_period;
|
1195 |
|
|
assert mac_tx_tdata = x"09" report "T7: incorrect src ip 3"; wait for clk_period;
|
1196 |
|
|
|
1197 |
|
|
assert mac_tx_tdata = x"c0" report "T7: incorrect dst ip 0"; wait for clk_period;
|
1198 |
|
|
assert mac_tx_tdata = x"a8" report "T7: incorrect dst ip 1"; wait for clk_period;
|
1199 |
|
|
assert mac_tx_tdata = x"05" report "T7: incorrect dst ip 2"; wait for clk_period;
|
1200 |
|
|
assert mac_tx_tdata = x"01" report "T7: incorrect dst ip 3"; wait for clk_period;
|
1201 |
|
|
|
1202 |
|
|
assert mac_tx_tdata = x"26" report "T7: incorrect src port 0"; wait for clk_period;
|
1203 |
|
|
assert mac_tx_tdata = x"94" report "T7: incorrect src port 1"; wait for clk_period;
|
1204 |
|
|
assert mac_tx_tdata = x"f4" report "T7: incorrect dst port 0"; wait for clk_period;
|
1205 |
|
|
assert mac_tx_tdata = x"9a" report "T7: incorrect dst port 1"; wait for clk_period;
|
1206 |
|
|
|
1207 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect udp len 0"; wait for clk_period;
|
1208 |
|
|
assert mac_tx_tdata = x"0c" report "T7: incorrect udp len 1"; wait for clk_period;
|
1209 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect udp cks 0"; wait for clk_period;
|
1210 |
|
|
assert mac_tx_tdata = x"00" report "T7: incorrect udp cks 1"; wait for clk_period;
|
1211 |
|
|
|
1212 |
|
|
assert mac_tx_tdata = x"40" report "T7: incorrect udp data 0"; wait for clk_period;
|
1213 |
|
|
assert mac_tx_tdata = x"41" report "T7: incorrect udp data 1"; wait for clk_period;
|
1214 |
|
|
|
1215 |
|
|
assert mac_tx_tdata = x"42" report "T7: incorrect udp data 2";
|
1216 |
|
|
assert mac_tx_tlast = '0' report "T7: tlast asserted too soon"; wait for clk_period;
|
1217 |
|
|
assert mac_tx_tdata = x"43" report "T7: incorrect udp data 3";
|
1218 |
|
|
assert mac_tx_tlast = '1' report "T7: tlast not asserted"; wait for clk_period;
|
1219 |
|
|
|
1220 |
|
|
assert udp_tx_result = IPTX_RESULT_SENT report "T7: TX did not complete";
|
1221 |
|
|
|
1222 |
|
|
assert udp_rx_int.data.data_in_valid = '0' report "T7: udp_rx_int.data.data_in_valid not cleared";
|
1223 |
|
|
assert udp_rx_int.data.data_in_last = '0' report "T7: udp_rx_int.data.data_in_last not cleared";
|
1224 |
|
|
assert udp_rx_start_int = '0' report "T7: udp_rx_start not cleared";
|
1225 |
|
|
assert ip_rx_hdr.num_frame_errors = x"00" report "T7: ip_rx_hdr.num_frame_errors non zero at end of test";
|
1226 |
|
|
assert ip_rx_hdr.last_error_code = x"0" report "T7: ip_rx_hdr.last_error_code indicates error at end of test";
|
1227 |
|
|
assert ip_pkt_count = x"06" report "T7: ip pkt cnt incorrect";
|
1228 |
|
|
|
1229 |
|
|
|
1230 |
|
|
|
1231 |
|
|
report "--- end of tests ---";
|
1232 |
|
|
wait;
|
1233 |
|
|
end process;
|
1234 |
|
|
|
1235 |
|
|
-- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received.
|
1236 |
|
|
|
1237 |
|
|
-- TX response process - COMB
|
1238 |
|
|
tx_proc_combinatorial: process(
|
1239 |
|
|
-- inputs
|
1240 |
|
|
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result, ip_rx_hdr,
|
1241 |
|
|
udp_tx_int.data.data_out_valid, PBTX,
|
1242 |
|
|
-- state
|
1243 |
|
|
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg,
|
1244 |
|
|
-- controls
|
1245 |
|
|
next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
|
1246 |
|
|
set_tx_started, set_tx_fin, first_byte_rx
|
1247 |
|
|
)
|
1248 |
|
|
begin
|
1249 |
|
|
-- set output_followers
|
1250 |
|
|
udp_tx_int.hdr <= tx_hdr;
|
1251 |
|
|
udp_tx_int.data.data_out_last <= set_last;
|
1252 |
|
|
udp_tx_start_int <= tx_start_reg;
|
1253 |
|
|
|
1254 |
|
|
-- set control signal defaults
|
1255 |
|
|
next_state <= IDLE;
|
1256 |
|
|
set_state <= '0';
|
1257 |
|
|
set_count <= HOLD;
|
1258 |
|
|
set_hdr <= '0';
|
1259 |
|
|
set_tx_start <= HOLD;
|
1260 |
|
|
set_last <= '0';
|
1261 |
|
|
set_tx_started <= HOLD;
|
1262 |
|
|
set_tx_fin <= HOLD;
|
1263 |
|
|
first_byte_rx <= (others => '0');
|
1264 |
|
|
|
1265 |
|
|
-- FSM
|
1266 |
|
|
case state is
|
1267 |
|
|
|
1268 |
|
|
when IDLE =>
|
1269 |
|
|
udp_tx_int.data.data_out <= (others => '0');
|
1270 |
|
|
udp_tx_int.data.data_out_valid <= '0';
|
1271 |
|
|
if udp_rx_start_int = '1' or PBTX = '1' then
|
1272 |
|
|
if udp_rx_start_int = '1' then
|
1273 |
|
|
first_byte_rx <= udp_rx_int.data.data_in;
|
1274 |
|
|
else
|
1275 |
|
|
first_byte_rx <= x"00";
|
1276 |
|
|
end if;
|
1277 |
|
|
set_tx_fin <= CLR;
|
1278 |
|
|
set_count <= RST;
|
1279 |
|
|
set_hdr <= '1';
|
1280 |
|
|
if udp_rx_int.data.data_in_last = '1' then
|
1281 |
|
|
set_tx_started <= SET;
|
1282 |
|
|
set_tx_start <= SET;
|
1283 |
|
|
next_state <= DATA_OUT;
|
1284 |
|
|
set_state <= '1';
|
1285 |
|
|
else
|
1286 |
|
|
next_state <= WAIT_RX_DONE;
|
1287 |
|
|
set_state <= '1';
|
1288 |
|
|
end if;
|
1289 |
|
|
end if;
|
1290 |
|
|
|
1291 |
|
|
when WAIT_RX_DONE =>
|
1292 |
|
|
-- wait until RX pkt fully received
|
1293 |
|
|
if udp_rx_int.data.data_in_last = '1' then
|
1294 |
|
|
set_tx_started <= SET;
|
1295 |
|
|
set_tx_start <= SET;
|
1296 |
|
|
next_state <= DATA_OUT;
|
1297 |
|
|
set_state <= '1';
|
1298 |
|
|
end if;
|
1299 |
|
|
|
1300 |
|
|
when DATA_OUT =>
|
1301 |
|
|
if udp_tx_result = UDPTX_RESULT_ERR then
|
1302 |
|
|
-- have an error from the IP TX layer, clear down the TX
|
1303 |
|
|
set_tx_start <= CLR;
|
1304 |
|
|
set_tx_fin <= SET;
|
1305 |
|
|
set_tx_started <= CLR;
|
1306 |
|
|
next_state <= IDLE;
|
1307 |
|
|
set_state <= '1';
|
1308 |
|
|
else
|
1309 |
|
|
if udp_tx_result = UDPTX_RESULT_SENDING then
|
1310 |
|
|
set_tx_start <= CLR; -- reset out start req as soon as we know we are sending
|
1311 |
|
|
end if;
|
1312 |
|
|
if ip_rx_hdr.is_broadcast = '1' then
|
1313 |
|
|
udp_tx_int.data.data_out <= std_logic_vector(count) or x"50";
|
1314 |
|
|
else
|
1315 |
|
|
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
|
1316 |
|
|
end if;
|
1317 |
|
|
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
|
1318 |
|
|
if udp_tx_data_out_ready_int = '1' then
|
1319 |
|
|
if unsigned(count) = x"03" then
|
1320 |
|
|
set_last <= '1';
|
1321 |
|
|
set_tx_fin <= SET;
|
1322 |
|
|
set_tx_started <= CLR;
|
1323 |
|
|
next_state <= IDLE;
|
1324 |
|
|
set_state <= '1';
|
1325 |
|
|
else
|
1326 |
|
|
set_count <= INCR;
|
1327 |
|
|
end if;
|
1328 |
|
|
end if;
|
1329 |
|
|
end if;
|
1330 |
|
|
|
1331 |
|
|
end case;
|
1332 |
|
|
end process;
|
1333 |
|
|
|
1334 |
|
|
|
1335 |
|
|
|
1336 |
|
|
-- TX response process - SEQ
|
1337 |
|
|
tx_proc_sequential: process(clk_int)
|
1338 |
|
|
begin
|
1339 |
|
|
if rising_edge(clk_int) then
|
1340 |
|
|
if reset = '1' then
|
1341 |
|
|
-- reset state variables
|
1342 |
|
|
state <= IDLE;
|
1343 |
|
|
count <= x"00";
|
1344 |
|
|
tx_start_reg <= '0';
|
1345 |
|
|
tx_hdr.dst_ip_addr <= (others => '0');
|
1346 |
|
|
tx_hdr.dst_port <= (others => '0');
|
1347 |
|
|
tx_hdr.src_port <= (others => '0');
|
1348 |
|
|
tx_hdr.data_length <= (others => '0');
|
1349 |
|
|
tx_hdr.checksum <= (others => '0');
|
1350 |
|
|
tx_started_reg <= '0';
|
1351 |
|
|
tx_fin_reg <= '0';
|
1352 |
|
|
PBTX_LED <= '0';
|
1353 |
|
|
else
|
1354 |
|
|
PBTX_LED <= PBTX;
|
1355 |
|
|
|
1356 |
|
|
-- Next rx_state processing
|
1357 |
|
|
if set_state = '1' then
|
1358 |
|
|
state <= next_state;
|
1359 |
|
|
else
|
1360 |
|
|
state <= state;
|
1361 |
|
|
end if;
|
1362 |
|
|
|
1363 |
|
|
-- count processing
|
1364 |
|
|
case set_count is
|
1365 |
|
|
when RST => count <= x"00";
|
1366 |
|
|
when INCR => count <= count + 1;
|
1367 |
|
|
when HOLD => count <= count;
|
1368 |
|
|
end case;
|
1369 |
|
|
|
1370 |
|
|
-- set tx hdr
|
1371 |
|
|
if set_hdr = '1' then
|
1372 |
|
|
-- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP
|
1373 |
|
|
if first_byte_rx = x"42" then
|
1374 |
|
|
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr
|
1375 |
|
|
elsif first_byte_rx = x"43" then
|
1376 |
|
|
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout
|
1377 |
|
|
else
|
1378 |
|
|
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender
|
1379 |
|
|
end if;
|
1380 |
|
|
tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
|
1381 |
|
|
tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
|
1382 |
|
|
tx_hdr.data_length <= x"0004";
|
1383 |
|
|
tx_hdr.checksum <= x"0000";
|
1384 |
|
|
else
|
1385 |
|
|
tx_hdr <= tx_hdr;
|
1386 |
|
|
end if;
|
1387 |
|
|
|
1388 |
|
|
-- set tx start signal
|
1389 |
|
|
case set_tx_start is
|
1390 |
|
|
when SET => tx_start_reg <= '1';
|
1391 |
|
|
when CLR => tx_start_reg <= '0';
|
1392 |
|
|
when HOLD => tx_start_reg <= tx_start_reg;
|
1393 |
|
|
end case;
|
1394 |
|
|
|
1395 |
|
|
-- set tx started signal
|
1396 |
|
|
case set_tx_started is
|
1397 |
|
|
when SET => tx_started_reg <= '1';
|
1398 |
|
|
when CLR => tx_started_reg <= '0';
|
1399 |
|
|
when HOLD => tx_started_reg <= tx_started_reg;
|
1400 |
|
|
end case;
|
1401 |
|
|
|
1402 |
|
|
-- set tx finished signal
|
1403 |
|
|
case set_tx_fin is
|
1404 |
|
|
when SET => tx_fin_reg <= '1';
|
1405 |
|
|
when CLR => tx_fin_reg <= '0';
|
1406 |
|
|
when HOLD => tx_fin_reg <= tx_fin_reg;
|
1407 |
|
|
end case;
|
1408 |
|
|
|
1409 |
|
|
|
1410 |
|
|
end if;
|
1411 |
|
|
end if;
|
1412 |
|
|
|
1413 |
|
|
end process;
|
1414 |
|
|
|
1415 |
|
|
END;
|