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pjf |
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-- Company:
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-- Engineer:
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--
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-- Create Date: 07:38:43 02/13/2012
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-- Design Name:
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-- Module Name: arp_STORE_tb.vhd
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-- Project Name: udp3
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: arp_STORE_br
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use ieee.std_logic_unsigned.all;
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use work.arp_types.all;
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ENTITY arp_STORE_tb IS
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END arp_STORE_tb;
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ARCHITECTURE behavior OF arp_STORE_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT arp_STORE_br
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generic (
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MAX_ARP_ENTRIES : integer := 256 -- max entries in the store
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);
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PORT(
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-- read signals
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read_req : in arp_store_rdrequest_t; -- requesting a '1' or store
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read_result : out arp_store_result_t; -- the result
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-- write signals
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write_req : in arp_store_wrrequest_t; -- requesting a '1' or store
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-- control and status signals
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clear_store : in std_logic; -- erase all entries
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entry_count : out unsigned(7 downto 0); -- how many entries currently in store
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-- system signals
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clk : in std_logic;
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reset : in STD_LOGIC
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);
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END COMPONENT;
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--Inputs
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signal read_req : arp_store_rdrequest_t;
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signal write_req : arp_store_wrrequest_t;
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signal clear_store : std_logic := '0';
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signal clk : std_logic := '0';
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signal reset : std_logic := '0';
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--Outputs
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signal read_result : arp_store_result_t;
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signal entry_count : unsigned(7 downto 0); -- how many entries currently in store
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-- Clock period definitions
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constant clk_period : time := 8 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: arp_STORE_br
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generic map (
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MAX_ARP_ENTRIES => 4
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)
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PORT MAP (
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read_req => read_req,
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read_result => read_result,
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write_req => write_req,
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clear_store => clear_store,
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entry_count => entry_count,
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clk => clk,
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reset => reset
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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read_req.req <= '0';
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read_req.ip <= (others => '0');
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write_req.req <= '0';
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write_req.entry.ip <= (others => '0');
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write_req.entry.mac <= (others => '0');
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reset <= '1';
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-- hold reset state
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wait for clk_period*10;
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reset <= '0';
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-- insert stimulus here
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report "T1 - look for something when store is empty";
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read_req.ip <= x"12345678";
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read_req.req <= '1';
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wait for clk_period*4;
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assert read_result.status = NOT_FOUND report "T1: expected NOT_FOUND";
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wait for clk_period;
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read_req.req <= '0';
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pjf |
wait for clk_period*2;
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pjf |
assert read_result.status = IDLE report "T1: expected IDLE";
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assert entry_count = x"00" report "T1: wrong entry count";
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report "T2 - insert first entry into store";
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write_req.entry.ip <= x"12345678";
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write_req.entry.mac <= x"002398127645";
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write_req.req <= '1';
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wait for clk_period;
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write_req.req <= '0';
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wait until read_result.status = IDLE;
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wait for clk_period;
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assert entry_count = x"01" report "T2: wrong entry count";
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report "T3 - check if can find this single entry";
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read_req.ip <= x"12345678";
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read_req.req <= '1';
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wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
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wait for clk_period;
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assert read_result.status = FOUND report "T3: expected FOUND";
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assert read_result.entry.ip = x"12345678" report "T3: wrong ip addr";
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assert read_result.entry.mac = x"002398127645" report "T3: wrong mac addr";
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wait for clk_period;
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read_req.req <= '0';
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pjf |
wait for clk_period*3;
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pjf |
assert read_result.status = IDLE report "T3: expected IDLE";
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report "T4 - check unable to find missing entry with one entry in store";
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read_req.ip <= x"12345679";
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read_req.req <= '1';
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wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
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wait for clk_period;
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assert read_result.status = NOT_FOUND report "T4: expected NOT_FOUND";
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wait for clk_period;
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read_req.req <= '0';
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pjf |
wait for clk_period*3;
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pjf |
assert read_result.status = IDLE report "T4: expected IDLE";
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report "T5 - insert 2nd entry into store and check can find both entries";
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write_req.entry.ip <= x"12345679";
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write_req.entry.mac <= x"101202303404";
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write_req.req <= '1';
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wait for clk_period;
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write_req.req <= '0';
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wait until read_result.status = IDLE;
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wait for clk_period;
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assert entry_count = x"02" report "T4: wrong entry count";
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read_req.ip <= x"12345678";
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read_req.req <= '1';
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wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
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wait for clk_period;
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assert read_result.status = FOUND report "T5.1: expected FOUND";
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assert read_result.entry.ip = x"12345678" report "T5.1: wrong ip addr";
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assert read_result.entry.mac = x"002398127645" report "T5.1: wrong mac addr";
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read_req.req <= '0';
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pjf |
wait for clk_period*3;
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pjf |
assert read_result.status = IDLE report "T5.1: expected IDLE";
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read_req.ip <= x"12345679";
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read_req.req <= '1';
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wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
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wait for clk_period;
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assert read_result.status = FOUND report "T5.2: expected FOUND";
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assert read_result.entry.ip = x"12345679" report "T5.2: wrong ip addr";
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assert read_result.entry.mac = x"101202303404" report "T5.2: wrong mac addr";
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read_req.req <= '0';
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pjf |
wait for clk_period*3;
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pjf |
assert read_result.status = IDLE report "T5.2: expected IDLE";
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report "T6 - insert 2 more entries so that the store is full. check can find all";
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write_req.entry.ip <= x"1234567a";
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write_req.entry.mac <= x"10120230340a";
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write_req.req <= '1';
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wait for clk_period;
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write_req.req <= '0';
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wait until read_result.status = IDLE;
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wait for clk_period;
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write_req.entry.ip <= x"1234567b";
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write_req.entry.mac <= x"10120230340b";
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write_req.req <= '1';
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wait for clk_period;
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write_req.req <= '0';
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wait until read_result.status = IDLE;
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wait for clk_period;
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assert entry_count = x"04" report "T6: wrong entry count";
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read_req.ip <= x"12345678";
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read_req.req <= '1';
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wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
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wait for clk_period;
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assert read_result.status = FOUND report "T6.1: expected FOUND";
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assert read_result.entry.ip = x"12345678" report "T6.1: wrong ip addr";
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assert read_result.entry.mac = x"002398127645" report "T6.1: wrong mac addr";
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read_req.req <= '0';
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pjf |
wait for clk_period*3;
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pjf |
assert read_result.status = IDLE report "T6.1: expected IDLE";
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read_req.ip <= x"12345679";
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read_req.req <= '1';
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wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
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wait for clk_period;
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assert read_result.status = FOUND report "T6.2: expected FOUND";
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assert read_result.entry.ip = x"12345679" report "T6.2: wrong ip addr";
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assert read_result.entry.mac = x"101202303404" report "T6.2: wrong mac addr";
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read_req.req <= '0';
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pjf |
wait for clk_period*3;
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10 |
pjf |
assert read_result.status = IDLE report "T6.2: expected IDLE";
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read_req.ip <= x"1234567a";
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read_req.req <= '1';
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wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
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wait for clk_period;
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assert read_result.status = FOUND report "T6.3: expected FOUND";
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assert read_result.entry.ip = x"1234567a" report "T6.3: wrong ip addr";
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assert read_result.entry.mac = x"10120230340a" report "T6.3: wrong mac addr";
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read_req.req <= '0';
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18 |
pjf |
wait for clk_period*3;
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10 |
pjf |
assert read_result.status = IDLE report "T6.3: expected IDLE";
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read_req.ip <= x"1234567b";
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read_req.req <= '1';
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wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
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wait for clk_period;
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assert read_result.status = FOUND report "T6.4: expected FOUND";
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assert read_result.entry.ip = x"1234567b" report "T6.4: wrong ip addr";
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assert read_result.entry.mac = x"10120230340b" report "T6.4: wrong mac addr";
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read_req.req <= '0';
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18 |
pjf |
wait for clk_period*3;
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10 |
pjf |
assert read_result.status = IDLE report "T6.4: expected IDLE";
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report "T7 - with store full, check that we dont find missing item";
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read_req.ip <= x"1233367b";
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read_req.req <= '1';
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wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
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wait for clk_period;
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assert read_result.status = NOT_FOUND report "T7: expected NOT_FOUND";
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read_req.req <= '0';
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255 |
18 |
pjf |
wait for clk_period*3;
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256 |
10 |
pjf |
assert read_result.status = IDLE report "T7: expected IDLE";
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257 |
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report "T8 - insert additional entry into store - will erase one of the others";
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259 |
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write_req.entry.ip <= x"12345699";
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260 |
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write_req.entry.mac <= x"992398127699";
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261 |
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write_req.req <= '1';
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262 |
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wait for clk_period;
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263 |
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write_req.req <= '0';
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264 |
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wait until read_result.status = IDLE;
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wait for clk_period;
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266 |
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assert entry_count = x"04" report "T8: wrong entry count";
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267 |
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read_req.ip <= x"12345699";
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268 |
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read_req.req <= '1';
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269 |
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wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
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270 |
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wait for clk_period;
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assert read_result.status = FOUND report "T8: expected FOUND";
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272 |
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assert read_result.entry.ip = x"12345699" report "T8: wrong ip addr";
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273 |
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assert read_result.entry.mac = x"992398127699" report "T8: wrong mac addr";
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274 |
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read_req.req <= '0';
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275 |
18 |
pjf |
wait for clk_period*3;
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276 |
10 |
pjf |
assert read_result.status = IDLE report "T8: expected IDLE";
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277 |
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278 |
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report "T9 - clear the store and ensure cant find something that was there";
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279 |
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clear_store <= '1';
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280 |
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wait for clk_period;
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281 |
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clear_store <= '0';
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282 |
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wait for clk_period;
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283 |
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assert entry_count = x"00" report "T9: wrong entry count";
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284 |
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read_req.ip <= x"12345699";
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285 |
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read_req.req <= '1';
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286 |
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wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
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287 |
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wait for clk_period;
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288 |
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assert read_result.status = NOT_FOUND report "T9: expected NOT_FOUND";
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289 |
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read_req.req <= '0';
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290 |
18 |
pjf |
wait for clk_period*3;
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291 |
10 |
pjf |
assert read_result.status = IDLE report "T9: expected IDLE";
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292 |
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|
293 |
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report "T10 - refill the store with three entries";
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294 |
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write_req.entry.ip <= x"12345675";
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295 |
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write_req.entry.mac <= x"10120230340a";
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296 |
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write_req.req <= '1';
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297 |
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wait for clk_period;
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298 |
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write_req.req <= '0';
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299 |
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wait until read_result.status = IDLE;
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300 |
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wait for clk_period;
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301 |
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write_req.entry.ip <= x"12345676";
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302 |
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write_req.entry.mac <= x"10120230340b";
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303 |
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write_req.req <= '1';
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304 |
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wait for clk_period;
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305 |
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write_req.req <= '0';
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306 |
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wait until read_result.status = IDLE;
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307 |
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wait for clk_period;
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308 |
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write_req.entry.ip <= x"12345677";
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309 |
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write_req.entry.mac <= x"10120230340c";
|
310 |
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write_req.req <= '1';
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311 |
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wait for clk_period;
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312 |
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write_req.req <= '0';
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313 |
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wait until read_result.status = IDLE;
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314 |
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wait for clk_period;
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315 |
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assert entry_count = x"03" report "T10: wrong entry count";
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316 |
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317 |
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report "T11 - check middle entry, then change it and check again";
|
318 |
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read_req.ip <= x"12345676";
|
319 |
|
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read_req.req <= '1';
|
320 |
|
|
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
|
321 |
|
|
wait for clk_period;
|
322 |
|
|
assert read_result.status = FOUND report "T11.1: expected FOUND";
|
323 |
|
|
assert read_result.entry.ip = x"12345676" report "T11.1: wrong ip addr";
|
324 |
|
|
assert read_result.entry.mac = x"10120230340b" report "T11.1: wrong mac addr";
|
325 |
|
|
read_req.req <= '0';
|
326 |
18 |
pjf |
wait for clk_period*3;
|
327 |
10 |
pjf |
assert read_result.status = IDLE report "T11.1: expected IDLE";
|
328 |
|
|
write_req.entry.ip <= x"12345676";
|
329 |
|
|
write_req.entry.mac <= x"10120990340b";
|
330 |
|
|
write_req.req <= '1';
|
331 |
|
|
wait for clk_period;
|
332 |
|
|
write_req.req <= '0';
|
333 |
|
|
wait for clk_period;
|
334 |
|
|
assert entry_count = x"03" report "T11: wrong entry count";
|
335 |
|
|
read_req.ip <= x"12345676";
|
336 |
|
|
read_req.req <= '1';
|
337 |
|
|
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
|
338 |
|
|
wait for clk_period;
|
339 |
|
|
assert read_result.status = FOUND report "T11.2: expected FOUND";
|
340 |
|
|
assert read_result.entry.ip = x"12345676" report "T11.2: wrong ip addr";
|
341 |
|
|
assert read_result.entry.mac = x"10120990340b" report "T11.2: wrong mac addr";
|
342 |
|
|
read_req.req <= '0';
|
343 |
18 |
pjf |
wait for clk_period*3;
|
344 |
10 |
pjf |
assert read_result.status = IDLE report "T11.2: expected IDLE";
|
345 |
|
|
|
346 |
|
|
report "T12 - check 2nd write at beginning";
|
347 |
|
|
-- clear store, write 1st entry, overwrite the entry, and check
|
348 |
|
|
clear_store <= '1';
|
349 |
|
|
wait for clk_period;
|
350 |
|
|
clear_store <= '0';
|
351 |
|
|
wait for clk_period;
|
352 |
|
|
assert entry_count = x"00" report "T12.1: wrong entry count";
|
353 |
|
|
write_req.entry.ip <= x"12345678";
|
354 |
|
|
write_req.entry.mac <= x"002398127645";
|
355 |
|
|
write_req.req <= '1';
|
356 |
|
|
wait for clk_period;
|
357 |
|
|
write_req.req <= '0';
|
358 |
|
|
wait until read_result.status = IDLE;
|
359 |
|
|
wait for clk_period;
|
360 |
|
|
assert entry_count = x"01" report "T12.2: wrong entry count";
|
361 |
|
|
write_req.entry.ip <= x"12345678";
|
362 |
|
|
write_req.entry.mac <= x"002398127647";
|
363 |
|
|
write_req.req <= '1';
|
364 |
|
|
wait for clk_period;
|
365 |
|
|
write_req.req <= '0';
|
366 |
|
|
wait until read_result.status = IDLE;
|
367 |
|
|
wait for clk_period;
|
368 |
|
|
assert entry_count = x"01" report "T12.3: wrong entry count";
|
369 |
|
|
read_req.ip <= x"12345678";
|
370 |
|
|
read_req.req <= '1';
|
371 |
|
|
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
|
372 |
|
|
wait for clk_period;
|
373 |
|
|
assert read_result.status = FOUND report "T12.4: expected FOUND";
|
374 |
|
|
assert read_result.entry.ip = x"12345678" report "T12.4: wrong ip addr";
|
375 |
|
|
assert read_result.entry.mac = x"002398127647" report "T12.4: wrong mac addr";
|
376 |
|
|
read_req.req <= '0';
|
377 |
18 |
pjf |
wait for clk_period*3;
|
378 |
10 |
pjf |
assert read_result.status = IDLE report "T12.5: expected IDLE";
|
379 |
|
|
|
380 |
|
|
report "--- end of tests ---";
|
381 |
|
|
wait;
|
382 |
|
|
end process;
|
383 |
|
|
|
384 |
|
|
END;
|