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-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
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-- File : v6_emac_v2_1_fifo_block.vhd
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-- Version : 2.1
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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-- Description: This is the FIFO Block level vhdl wrapper for the Virtex-6
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-- Embedded Tri-Mode Ethernet MAC. This wrapper enhances the
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-- standard MAC core with an example FIFO. The interface to
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-- this FIFO is designed to the AXI-S specification.
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-- Please refer to core documentation for
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-- additional FIFO and AXI-S information.
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--
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-- _________________________________________________________
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-- | |
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-- | FIFO BLOCK LEVEL WRAPPER |
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-- | |
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-- | _____________________ ______________________ |
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-- | | _________________ | | | |
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-- | | | | | | | |
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-- -------->| | TX AXI FIFO | |---->| Tx Tx |--------->
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-- | | | | | | AXI-S PHY | |
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-- | | |_________________| | | I/F I/F | |
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-- | | | | | |
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-- AXI | | 10/100/1G | | V6 EMAC CORE | |
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-- Stream | | ETHERNET FIFO | | BLOCK WRAPPER | | PHY I/F
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-- | | | | | |
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-- | | _________________ | | | |
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-- | | | | | | | |
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-- <--------| | RX AXI FIFO | |<----| Rx Rx |<---------
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-- | | | | | | AXI-S PHY | |
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-- | | |_________________| | | I/F I/F | |
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-- | |_____________________| |______________________| |
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-- | |
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-- |_________________________________________________________|
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--
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library unisim;
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use unisim.vcomponents.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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--------------------------------------------------------------------------------
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-- The module declaration for the fifo block level wrapper.
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--------------------------------------------------------------------------------
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entity v6_emac_v2_1_fifo_block is
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port(
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gtx_clk : in std_logic;
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-- Receiver Statistics Interface
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-----------------------------------------
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rx_mac_aclk : out std_logic;
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rx_reset : out std_logic;
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rx_statistics_vector : out std_logic_vector(27 downto 0);
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rx_statistics_valid : out std_logic;
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-- Receiver (AXI-S) Interface
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------------------------------------------
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rx_fifo_clock : in std_logic;
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rx_fifo_resetn : in std_logic;
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rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
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rx_axis_fifo_tvalid : out std_logic;
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rx_axis_fifo_tready : in std_logic;
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rx_axis_fifo_tlast : out std_logic;
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-- Transmitter Statistics Interface
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--------------------------------------------
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tx_mac_aclk : out std_logic;
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tx_reset : out std_logic;
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tx_ifg_delay : in std_logic_vector(7 downto 0);
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tx_statistics_vector : out std_logic_vector(31 downto 0);
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tx_statistics_valid : out std_logic;
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-- Transmitter (AXI-S) Interface
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---------------------------------------------
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tx_fifo_clock : in std_logic;
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tx_fifo_resetn : in std_logic;
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tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
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tx_axis_fifo_tvalid : in std_logic;
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tx_axis_fifo_tready : out std_logic;
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tx_axis_fifo_tlast : in std_logic;
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-- MAC Control Interface
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--------------------------
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pause_req : in std_logic;
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pause_val : in std_logic_vector(15 downto 0);
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-- Reference clock for IDELAYCTRL's
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refclk : in std_logic;
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-- GMII Interface
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-------------------
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gmii_txd : out std_logic_vector(7 downto 0);
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gmii_tx_en : out std_logic;
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gmii_tx_er : out std_logic;
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gmii_tx_clk : out std_logic;
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gmii_rxd : in std_logic_vector(7 downto 0);
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gmii_rx_dv : in std_logic;
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gmii_rx_er : in std_logic;
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gmii_rx_clk : in std_logic;
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gmii_col : in std_logic;
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gmii_crs : in std_logic;
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mii_tx_clk : in std_logic;
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-- Initial Unicast Address Value
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unicast_address : in std_logic_vector(47 downto 0);
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-- asynchronous reset
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glbl_rstn : in std_logic;
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rx_axi_rstn : in std_logic;
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tx_axi_rstn : in std_logic
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);
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end v6_emac_v2_1_fifo_block;
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architecture wrapper of v6_emac_v2_1_fifo_block is
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------------------------------------------------------------------------------
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-- Component declaration for the block level
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------------------------------------------------------------------------------
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component v6_emac_v2_1_block
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port(
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gtx_clk : in std_logic;
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-- Receiver Interface
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----------------------------
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rx_statistics_vector : out std_logic_vector(27 downto 0);
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rx_statistics_valid : out std_logic;
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rx_mac_aclk : out std_logic;
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rx_reset : out std_logic;
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rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
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rx_axis_mac_tvalid : out std_logic;
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rx_axis_mac_tlast : out std_logic;
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rx_axis_mac_tuser : out std_logic;
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-- Transmitter Interface
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-------------------------------
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tx_ifg_delay : in std_logic_vector(7 downto 0);
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tx_statistics_vector : out std_logic_vector(31 downto 0);
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tx_statistics_valid : out std_logic;
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tx_mac_aclk : out std_logic;
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tx_reset : out std_logic;
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tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
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tx_axis_mac_tvalid : in std_logic;
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tx_axis_mac_tlast : in std_logic;
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tx_axis_mac_tuser : in std_logic;
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tx_axis_mac_tready : out std_logic;
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tx_collision : out std_logic;
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tx_retransmit : out std_logic;
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-- MAC Control Interface
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------------------------
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pause_req : in std_logic;
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pause_val : in std_logic_vector(15 downto 0);
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-- Reference clock for IDELAYCTRL's
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refclk : in std_logic;
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-- GMII Interface
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-----------------
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gmii_txd : out std_logic_vector(7 downto 0);
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gmii_tx_en : out std_logic;
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gmii_tx_er : out std_logic;
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gmii_tx_clk : out std_logic;
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gmii_rxd : in std_logic_vector(7 downto 0);
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gmii_rx_dv : in std_logic;
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gmii_rx_er : in std_logic;
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gmii_rx_clk : in std_logic;
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gmii_col : in std_logic;
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gmii_crs : in std_logic;
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mii_tx_clk : in std_logic;
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-- Initial Unicast Address Value
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unicast_address : in std_logic_vector(47 downto 0);
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-- asynchronous reset
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-----------------
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glbl_rstn : in std_logic;
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rx_axi_rstn : in std_logic;
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tx_axi_rstn : in std_logic
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);
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end component;
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------------------------------------------------------------------------------
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-- Component declaration for the fifo
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------------------------------------------------------------------------------
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component ten_100_1g_eth_fifo
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generic (
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FULL_DUPLEX_ONLY : boolean := false); -- If fifo is to be used only in full
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-- duplex set to true for optimised implementation
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port (
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tx_fifo_aclk : in std_logic;
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tx_fifo_resetn : in std_logic;
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tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
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tx_axis_fifo_tvalid : in std_logic;
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tx_axis_fifo_tlast : in std_logic;
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tx_axis_fifo_tready : out std_logic;
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tx_mac_aclk : in std_logic;
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tx_mac_resetn : in std_logic;
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tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
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tx_axis_mac_tvalid : out std_logic;
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tx_axis_mac_tlast : out std_logic;
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tx_axis_mac_tready : in std_logic;
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tx_axis_mac_tuser : out std_logic;
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tx_fifo_overflow : out std_logic;
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tx_fifo_status : out std_logic_vector(3 downto 0);
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tx_collision : in std_logic;
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tx_retransmit : in std_logic;
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rx_fifo_aclk : in std_logic;
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rx_fifo_resetn : in std_logic;
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rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
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rx_axis_fifo_tvalid : out std_logic;
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rx_axis_fifo_tlast : out std_logic;
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rx_axis_fifo_tready : in std_logic;
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rx_mac_aclk : in std_logic;
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rx_mac_resetn : in std_logic;
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rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
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rx_axis_mac_tvalid : in std_logic;
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rx_axis_mac_tlast : in std_logic;
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rx_axis_mac_tready : out std_logic;
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rx_axis_mac_tuser : in std_logic;
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rx_fifo_status : out std_logic_vector(3 downto 0);
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rx_fifo_overflow : out std_logic
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);
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end component;
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------------------------------------------------------------------------------
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-- Internal signals used in this fifo block level wrapper.
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------------------------------------------------------------------------------
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-- Note: KEEP attributes preserve signal names so they can be displayed in
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-- simulator wave windows
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signal rx_mac_aclk_int : std_logic; -- MAC Rx clock
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signal tx_mac_aclk_int : std_logic; -- MAC Tx clock
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signal rx_reset_int : std_logic; -- MAC Rx reset
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signal tx_reset_int : std_logic; -- MAC Tx reset
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signal tx_mac_resetn : std_logic;
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signal rx_mac_resetn : std_logic;
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-- MAC receiver client I/F
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signal rx_axis_mac_tdata : std_logic_vector(7 downto 0);
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signal rx_axis_mac_tvalid : std_logic;
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signal rx_axis_mac_tlast : std_logic;
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signal rx_axis_mac_tuser : std_logic;
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-- MAC transmitter client I/F
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signal tx_axis_mac_tdata : std_logic_vector(7 downto 0);
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signal tx_axis_mac_tvalid : std_logic;
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signal tx_axis_mac_tready : std_logic;
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signal tx_axis_mac_tlast : std_logic;
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signal tx_axis_mac_tuser : std_logic;
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signal tx_collision : std_logic;
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signal tx_retransmit : std_logic;
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-- Note: KEEP attributes preserve signal names so they can be displayed in
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-- simulator wave windows
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attribute keep : string;
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attribute keep of rx_axis_mac_tdata : signal is "true";
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attribute keep of rx_axis_mac_tvalid : signal is "true";
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attribute keep of rx_axis_mac_tlast : signal is "true";
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attribute keep of rx_axis_mac_tuser : signal is "true";
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attribute keep of tx_axis_mac_tdata : signal is "true";
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attribute keep of tx_axis_mac_tvalid : signal is "true";
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attribute keep of tx_axis_mac_tready : signal is "true";
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attribute keep of tx_axis_mac_tlast : signal is "true";
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attribute keep of tx_axis_mac_tuser : signal is "true";
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begin
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------------------------------------------------------------------------------
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-- Connect the output clock signals
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337 |
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------------------------------------------------------------------------------
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338 |
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|
339 |
|
|
rx_mac_aclk <= rx_mac_aclk_int;
|
340 |
|
|
tx_mac_aclk <= tx_mac_aclk_int;
|
341 |
|
|
rx_reset <= rx_reset_int;
|
342 |
|
|
tx_reset <= tx_reset_int;
|
343 |
|
|
|
344 |
|
|
------------------------------------------------------------------------------
|
345 |
|
|
-- Instantiate the Tri-Mode EMAC Block wrapper
|
346 |
|
|
------------------------------------------------------------------------------
|
347 |
|
|
v6emac_block : v6_emac_v2_1_block
|
348 |
|
|
port map(
|
349 |
|
|
gtx_clk => gtx_clk,
|
350 |
|
|
|
351 |
|
|
-- Client Receiver Interface
|
352 |
|
|
rx_statistics_vector => rx_statistics_vector,
|
353 |
|
|
rx_statistics_valid => rx_statistics_valid,
|
354 |
|
|
|
355 |
|
|
rx_mac_aclk => rx_mac_aclk_int,
|
356 |
|
|
rx_reset => rx_reset_int,
|
357 |
|
|
rx_axis_mac_tdata => rx_axis_mac_tdata,
|
358 |
|
|
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
|
359 |
|
|
rx_axis_mac_tlast => rx_axis_mac_tlast,
|
360 |
|
|
rx_axis_mac_tuser => rx_axis_mac_tuser,
|
361 |
|
|
|
362 |
|
|
-- Client Transmitter Interface
|
363 |
|
|
tx_ifg_delay => tx_ifg_delay,
|
364 |
|
|
tx_statistics_vector => tx_statistics_vector,
|
365 |
|
|
tx_statistics_valid => tx_statistics_valid,
|
366 |
|
|
|
367 |
|
|
tx_mac_aclk => tx_mac_aclk_int,
|
368 |
|
|
tx_reset => tx_reset_int,
|
369 |
|
|
tx_axis_mac_tdata => tx_axis_mac_tdata ,
|
370 |
|
|
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
|
371 |
|
|
tx_axis_mac_tlast => tx_axis_mac_tlast,
|
372 |
|
|
tx_axis_mac_tuser => tx_axis_mac_tuser,
|
373 |
|
|
tx_axis_mac_tready => tx_axis_mac_tready,
|
374 |
|
|
tx_collision => tx_collision,
|
375 |
|
|
tx_retransmit => tx_retransmit,
|
376 |
|
|
|
377 |
|
|
-- Flow Control
|
378 |
|
|
pause_req => pause_req,
|
379 |
|
|
pause_val => pause_val,
|
380 |
|
|
|
381 |
|
|
-- Reference clock for IDELAYCTRL's
|
382 |
|
|
refclk => refclk,
|
383 |
|
|
|
384 |
|
|
-- GMII Interface
|
385 |
|
|
gmii_txd => gmii_txd,
|
386 |
|
|
gmii_tx_en => gmii_tx_en,
|
387 |
|
|
gmii_tx_er => gmii_tx_er,
|
388 |
|
|
gmii_tx_clk => gmii_tx_clk,
|
389 |
|
|
gmii_rxd => gmii_rxd,
|
390 |
|
|
gmii_rx_dv => gmii_rx_dv,
|
391 |
|
|
gmii_rx_er => gmii_rx_er,
|
392 |
|
|
gmii_rx_clk => gmii_rx_clk,
|
393 |
|
|
gmii_crs => gmii_crs,
|
394 |
|
|
gmii_col => gmii_col,
|
395 |
|
|
mii_tx_clk => mii_tx_clk,
|
396 |
|
|
|
397 |
|
|
unicast_address => unicast_address,
|
398 |
|
|
|
399 |
|
|
-- asynchronous reset
|
400 |
|
|
glbl_rstn => glbl_rstn,
|
401 |
|
|
rx_axi_rstn => rx_axi_rstn,
|
402 |
|
|
tx_axi_rstn => tx_axi_rstn
|
403 |
|
|
|
404 |
|
|
);
|
405 |
|
|
|
406 |
|
|
|
407 |
|
|
------------------------------------------------------------------------------
|
408 |
|
|
-- Instantiate the user side FIFO
|
409 |
|
|
------------------------------------------------------------------------------
|
410 |
|
|
-- create inverted mac resets as the FIFO expects AXI compliant resets
|
411 |
|
|
tx_mac_resetn <= not tx_reset_int;
|
412 |
|
|
rx_mac_resetn <= not rx_reset_int;
|
413 |
|
|
|
414 |
|
|
|
415 |
|
|
user_side_FIFO : ten_100_1g_eth_fifo
|
416 |
|
|
generic map(
|
417 |
|
|
FULL_DUPLEX_ONLY => false
|
418 |
|
|
)
|
419 |
|
|
port map(
|
420 |
|
|
-- Transmit FIFO MAC TX Interface
|
421 |
|
|
tx_fifo_aclk => tx_fifo_clock,
|
422 |
|
|
tx_fifo_resetn => tx_fifo_resetn,
|
423 |
|
|
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
|
424 |
|
|
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
|
425 |
|
|
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
|
426 |
|
|
tx_axis_fifo_tready => tx_axis_fifo_tready,
|
427 |
|
|
|
428 |
|
|
tx_mac_aclk => tx_mac_aclk_int,
|
429 |
|
|
tx_mac_resetn => tx_mac_resetn,
|
430 |
|
|
tx_axis_mac_tdata => tx_axis_mac_tdata,
|
431 |
|
|
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
|
432 |
|
|
tx_axis_mac_tlast => tx_axis_mac_tlast,
|
433 |
|
|
tx_axis_mac_tready => tx_axis_mac_tready,
|
434 |
|
|
tx_axis_mac_tuser => tx_axis_mac_tuser,
|
435 |
|
|
|
436 |
|
|
tx_fifo_overflow => open,
|
437 |
|
|
tx_fifo_status => open,
|
438 |
|
|
tx_collision => tx_collision,
|
439 |
|
|
tx_retransmit => tx_retransmit,
|
440 |
|
|
|
441 |
|
|
rx_fifo_aclk => rx_fifo_clock,
|
442 |
|
|
rx_fifo_resetn => rx_fifo_resetn,
|
443 |
|
|
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
|
444 |
|
|
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
|
445 |
|
|
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
|
446 |
|
|
rx_axis_fifo_tready => rx_axis_fifo_tready,
|
447 |
|
|
|
448 |
|
|
rx_mac_aclk => rx_mac_aclk_int,
|
449 |
|
|
rx_mac_resetn => rx_mac_resetn,
|
450 |
|
|
rx_axis_mac_tdata => rx_axis_mac_tdata,
|
451 |
|
|
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
|
452 |
|
|
rx_axis_mac_tlast => rx_axis_mac_tlast,
|
453 |
|
|
rx_axis_mac_tready => open, -- not used as MAC cannot throttle
|
454 |
|
|
rx_axis_mac_tuser => rx_axis_mac_tuser,
|
455 |
|
|
|
456 |
|
|
rx_fifo_status => open,
|
457 |
|
|
rx_fifo_overflow => open
|
458 |
|
|
);
|
459 |
|
|
|
460 |
|
|
|
461 |
|
|
end wrapper;
|