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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:01:00 06/11/2011
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-- Design Name:
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-- Module Name: UDP_integration_example - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.ipv4_types.all;
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use work.arp_types.all;
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entity UDP_integration_example is
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port (
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-- System signals
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------------------
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reset : in std_logic; -- asynchronous reset
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clk_in_p : in std_logic; -- 200MHz clock input from board
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clk_in_n : in std_logic;
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-- System controls
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------------------
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PBTX : in std_logic;
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PB_DO_SECOND_TX : in std_logic;
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DO_SECOND_TX_LED : out std_logic;
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pjf |
UDP_RX : out std_logic;
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UDP_Start : out std_logic;
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PBTX_LED : out std_logic;
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TX_Started : out std_logic;
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TX_Completed : out std_logic;
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TX_RSLT_0 : out std_logic;
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TX_RSLT_1 : out std_logic;
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pjf |
reset_leds : in std_logic;
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display : out std_logic_vector(7 downto 0);
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-- GMII Interface
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-----------------
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phy_resetn : out std_logic;
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gmii_txd : out std_logic_vector(7 downto 0);
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gmii_tx_en : out std_logic;
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gmii_tx_er : out std_logic;
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gmii_tx_clk : out std_logic;
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gmii_rxd : in std_logic_vector(7 downto 0);
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gmii_rx_dv : in std_logic;
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gmii_rx_er : in std_logic;
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gmii_rx_clk : in std_logic;
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gmii_col : in std_logic;
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gmii_crs : in std_logic;
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mii_tx_clk : in std_logic
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);
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end UDP_integration_example;
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architecture Behavioral of UDP_integration_example is
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pjf |
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2 |
pjf |
------------------------------------------------------------------------------
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pjf |
-- Component Declaration for the complete UDP layer
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pjf |
------------------------------------------------------------------------------
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component UDP_Complete
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generic (
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CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
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ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
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ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
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MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
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);
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Port (
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-- UDP TX signals
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udp_tx_start : in std_logic; -- indicates req to tx UDP
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udp_txi : in udp_tx_type; -- UDP tx cxns
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udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
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udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
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-- UDP RX signals
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udp_rx_start : out std_logic; -- indicates receipt of udp header
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udp_rxo : out udp_rx_type;
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-- IP RX signals
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ip_rx_hdr : out ipv4_rx_header_type;
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-- system signals
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clk_in_p : in std_logic; -- 200MHz clock input from board
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clk_in_n : in std_logic;
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clk_out : out std_logic;
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reset : in STD_LOGIC;
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our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
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our_mac_address : in std_logic_vector (47 downto 0);
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control : in udp_control_type;
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-- status signals
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arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
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ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
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-- GMII Interface
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phy_resetn : out std_logic;
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gmii_txd : out std_logic_vector(7 downto 0);
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gmii_tx_en : out std_logic;
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gmii_tx_er : out std_logic;
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gmii_tx_clk : out std_logic;
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gmii_rxd : in std_logic_vector(7 downto 0);
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gmii_rx_dv : in std_logic;
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gmii_rx_er : in std_logic;
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gmii_rx_clk : in std_logic;
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gmii_col : in std_logic;
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gmii_crs : in std_logic;
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mii_tx_clk : in std_logic
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);
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end component;
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pjf |
-- for UDP_block : UDP_Complete use configuration work.UDP_Complete.udpc_multi_slot_arp;
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pjf |
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pjf |
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type state_type is (IDLE, WAIT_RX_DONE, DATA_OUT, PAUSE, CHECK_SECOND_TX, SET_SEC_HDR);
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type count_mode_type is (RST, INCR, HOLD);
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type set_clr_type is (SET, CLR, HOLD);
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type sec_tx_ctrl_type is (CLR,PRIME,DO,HOLD);
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pjf |
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-- system signals
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signal clk_int : std_logic;
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signal our_mac : STD_LOGIC_VECTOR (47 downto 0);
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signal our_ip : STD_LOGIC_VECTOR (31 downto 0);
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signal udp_tx_int : udp_tx_type;
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signal udp_tx_result_int : std_logic_vector (1 downto 0);
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signal udp_tx_data_out_ready_int : std_logic;
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signal udp_rx_int : udp_rx_type;
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signal udp_tx_start_int : std_logic;
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signal udp_rx_start_int : std_logic;
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signal arp_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0);
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signal ip_pkt_count_int : STD_LOGIC_VECTOR(7 downto 0);
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signal ip_rx_hdr_int : ipv4_rx_header_type;
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-- state signals
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signal state : state_type;
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signal count : unsigned (7 downto 0);
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signal tx_hdr : udp_tx_header_type;
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signal tx_start_reg : std_logic;
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signal tx_started_reg : std_logic;
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signal tx_fin_reg : std_logic;
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signal prime_second_tx : std_logic; -- if want to do a 2nd tx after the first
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signal do_second_tx : std_logic; -- if need to do a 2nd tx as next tx
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pjf |
-- control signals
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signal next_state : state_type;
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signal set_state : std_logic;
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signal set_count : count_mode_type;
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signal set_hdr : std_logic;
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signal set_tx_start : set_clr_type;
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signal set_last : std_logic;
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signal set_tx_started : set_clr_type;
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signal set_tx_fin : set_clr_type;
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signal first_byte_rx : STD_LOGIC_VECTOR(7 downto 0);
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signal control_int : udp_control_type;
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signal set_second_tx : sec_tx_ctrl_type;
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pjf |
begin
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process (
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pjf |
our_ip, our_mac, udp_tx_result_int, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int,
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pjf |
udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
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pjf |
reset, tx_started_reg, tx_fin_reg, tx_start_reg, state, prime_second_tx, do_second_tx, set_second_tx,
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PB_DO_SECOND_TX, do_second_tx
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)
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begin
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-- set up our local addresses and default controls
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our_ip <= x"c0a80119"; -- 192.168.1.25
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our_mac <= x"002320212223";
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pjf |
control_int.ip_controls.arp_controls.clear_cache <= '0';
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pjf |
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-- determine RX good and error LEDs
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if udp_rx_int.hdr.is_valid = '1' then
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UDP_RX <= '1';
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else
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UDP_RX <= '0';
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end if;
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pjf |
UDP_Start <= udp_rx_start_int;
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TX_Started <= tx_start_reg; --tx_started_reg;
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TX_Completed <= tx_fin_reg;
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TX_RSLT_0 <= udp_tx_result_int(0);
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TX_RSLT_1 <= udp_tx_result_int(1);
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pjf |
DO_SECOND_TX_LED <= prime_second_tx;
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pjf |
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-- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
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display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
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pjf |
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-- display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
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case state is
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when IDLE => display (3 downto 0) <= "0001";
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when WAIT_RX_DONE => display (3 downto 0) <= "0010";
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when DATA_OUT => display (3 downto 0) <= "0011";
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when PAUSE => display (3 downto 0) <= "0100";
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when CHECK_SECOND_TX => display (3 downto 0) <= "0101";
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when SET_SEC_HDR => display (3 downto 0) <= "0110";
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pjf |
end case;
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pjf |
end process;
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pjf |
-- AUTO TX process - on receipt of any UDP pkt, send a response. data sent is modified if a broadcast was received.
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pjf |
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pjf |
-- TX response process - COMB
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pjf |
tx_proc_combinatorial: process(
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-- inputs
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pjf |
udp_rx_start_int, udp_rx_int, udp_tx_data_out_ready_int, udp_tx_result_int, ip_rx_hdr_int,
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pjf |
udp_tx_int.data.data_out_valid, PBTX, PB_DO_SECOND_TX,
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pjf |
-- state
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pjf |
state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, prime_second_tx, do_second_tx,
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pjf |
-- controls
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next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
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pjf |
set_tx_started, set_tx_fin, first_byte_rx, set_second_tx
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pjf |
)
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begin
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-- set output_followers
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udp_tx_int.hdr <= tx_hdr;
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udp_tx_int.data.data_out_last <= set_last;
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udp_tx_start_int <= tx_start_reg;
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-- set control signal defaults
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next_state <= IDLE;
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set_state <= '0';
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set_count <= HOLD;
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set_hdr <= '0';
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set_tx_start <= HOLD;
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set_last <= '0';
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set_tx_started <= HOLD;
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set_tx_fin <= HOLD;
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pjf |
first_byte_rx <= (others => '0');
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pjf |
udp_tx_int.data.data_out <= (others => '0');
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udp_tx_int.data.data_out_valid <= '0';
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pjf |
set_second_tx <= HOLD;
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2 |
pjf |
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10 |
pjf |
if PB_DO_SECOND_TX = '1' then
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set_second_tx <= PRIME;
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end if;
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2 |
pjf |
-- FSM
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case state is
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when IDLE =>
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udp_tx_int.data.data_out_valid <= '0';
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if udp_rx_start_int = '1' or PBTX = '1' then
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pjf |
if udp_rx_start_int = '1' then
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first_byte_rx <= udp_rx_int.data.data_in;
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else
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first_byte_rx <= x"00";
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end if;
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8 |
pjf |
set_tx_fin <= CLR;
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set_count <= RST;
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set_hdr <= '1';
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if udp_rx_int.data.data_in_last = '1' then
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set_tx_started <= SET;
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set_tx_start <= SET;
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next_state <= DATA_OUT;
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set_state <= '1';
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else
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next_state <= WAIT_RX_DONE;
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set_state <= '1';
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end if;
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end if;
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when WAIT_RX_DONE =>
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-- wait until RX pkt fully received
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if udp_rx_int.data.data_in_last = '1' then
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2 |
pjf |
set_tx_started <= SET;
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set_tx_start <= SET;
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next_state <= DATA_OUT;
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set_state <= '1';
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end if;
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276 |
8 |
pjf |
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2 |
pjf |
when DATA_OUT =>
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278 |
8 |
pjf |
if udp_tx_result_int = UDPTX_RESULT_ERR then
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-- have an error from the IP TX layer, clear down the TX
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set_tx_start <= CLR;
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set_tx_fin <= SET;
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set_tx_started <= CLR;
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283 |
10 |
pjf |
set_second_tx <= CLR;
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284 |
8 |
pjf |
next_state <= IDLE;
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285 |
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set_state <= '1';
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else
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if udp_tx_result_int = UDPTX_RESULT_SENDING then
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set_tx_start <= CLR; -- reset out start req as soon as we know we are sending
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end if;
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if ip_rx_hdr_int.is_broadcast = '1' then
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udp_tx_int.data.data_out <= std_logic_vector(count) or x"50";
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2 |
pjf |
else
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8 |
pjf |
udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
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2 |
pjf |
end if;
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295 |
8 |
pjf |
udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
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if udp_tx_data_out_ready_int = '1' then
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if unsigned(count) = x"03" then
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set_last <= '1';
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set_tx_fin <= SET;
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set_tx_started <= CLR;
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301 |
10 |
pjf |
next_state <= PAUSE;
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302 |
8 |
pjf |
set_state <= '1';
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else
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set_count <= INCR;
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end if;
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end if;
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2 |
pjf |
end if;
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308 |
10 |
pjf |
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309 |
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when PAUSE =>
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next_state <= CHECK_SECOND_TX;
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311 |
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set_state <= '1';
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312 |
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|
314 |
|
|
when CHECK_SECOND_TX =>
|
315 |
|
|
if prime_second_tx = '1' then
|
316 |
|
|
set_second_tx <= DO;
|
317 |
|
|
next_state <= SET_SEC_HDR;
|
318 |
|
|
set_state <= '1';
|
319 |
|
|
else
|
320 |
|
|
set_second_tx <= CLR;
|
321 |
|
|
next_state <= IDLE;
|
322 |
|
|
set_state <= '1';
|
323 |
|
|
end if;
|
324 |
2 |
pjf |
|
325 |
10 |
pjf |
when SET_SEC_HDR =>
|
326 |
|
|
set_hdr <= '1';
|
327 |
|
|
set_tx_started <= SET;
|
328 |
|
|
set_tx_start <= SET;
|
329 |
|
|
next_state <= DATA_OUT;
|
330 |
|
|
set_state <= '1';
|
331 |
|
|
|
332 |
2 |
pjf |
end case;
|
333 |
|
|
end process;
|
334 |
|
|
|
335 |
|
|
|
336 |
|
|
|
337 |
|
|
-- TX response process - SEQ
|
338 |
|
|
tx_proc_sequential: process(clk_int)
|
339 |
|
|
begin
|
340 |
|
|
if rising_edge(clk_int) then
|
341 |
|
|
if reset = '1' then
|
342 |
|
|
-- reset state variables
|
343 |
|
|
state <= IDLE;
|
344 |
|
|
count <= x"00";
|
345 |
|
|
tx_start_reg <= '0';
|
346 |
|
|
tx_hdr.dst_ip_addr <= (others => '0');
|
347 |
|
|
tx_hdr.dst_port <= (others => '0');
|
348 |
|
|
tx_hdr.src_port <= (others => '0');
|
349 |
|
|
tx_hdr.data_length <= (others => '0');
|
350 |
|
|
tx_hdr.checksum <= (others => '0');
|
351 |
|
|
tx_started_reg <= '0';
|
352 |
|
|
tx_fin_reg <= '0';
|
353 |
|
|
PBTX_LED <= '0';
|
354 |
10 |
pjf |
do_second_tx <= '0';
|
355 |
|
|
prime_second_tx <= '0';
|
356 |
2 |
pjf |
else
|
357 |
|
|
PBTX_LED <= PBTX;
|
358 |
|
|
|
359 |
|
|
-- Next rx_state processing
|
360 |
|
|
if set_state = '1' then
|
361 |
|
|
state <= next_state;
|
362 |
|
|
else
|
363 |
|
|
state <= state;
|
364 |
|
|
end if;
|
365 |
|
|
|
366 |
|
|
-- count processing
|
367 |
|
|
case set_count is
|
368 |
|
|
when RST => count <= x"00";
|
369 |
|
|
when INCR => count <= count + 1;
|
370 |
|
|
when HOLD => count <= count;
|
371 |
|
|
end case;
|
372 |
|
|
|
373 |
|
|
-- set tx hdr
|
374 |
|
|
if set_hdr = '1' then
|
375 |
10 |
pjf |
-- select the dst addr of the tx:
|
376 |
|
|
-- if do_second_tx, to solaris box
|
377 |
|
|
-- otherwise control according to first byte of received data:
|
378 |
|
|
-- B = broadcast
|
379 |
|
|
-- C = to dummy address to test timeout
|
380 |
|
|
-- D to solaris box
|
381 |
|
|
-- otherwise, direct to sender
|
382 |
|
|
if do_second_tx = '1' then
|
383 |
|
|
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5
|
384 |
|
|
elsif first_byte_rx = x"42" then
|
385 |
8 |
pjf |
tx_hdr.dst_ip_addr <= IP_BC_ADDR; -- send to Broadcast addr
|
386 |
|
|
elsif first_byte_rx = x"43" then
|
387 |
|
|
tx_hdr.dst_ip_addr <= x"c0bbccdd"; -- set dst unknown so get ARP timeout
|
388 |
10 |
pjf |
elsif first_byte_rx = x"44" then
|
389 |
|
|
tx_hdr.dst_ip_addr <= x"c0a80005"; -- set dst to solaris box at 192.168.0.5
|
390 |
6 |
pjf |
else
|
391 |
8 |
pjf |
tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr; -- reply to sender
|
392 |
6 |
pjf |
end if;
|
393 |
2 |
pjf |
tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
|
394 |
|
|
tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
|
395 |
|
|
tx_hdr.data_length <= x"0004";
|
396 |
|
|
tx_hdr.checksum <= x"0000";
|
397 |
|
|
else
|
398 |
|
|
tx_hdr <= tx_hdr;
|
399 |
|
|
end if;
|
400 |
|
|
|
401 |
|
|
-- set tx start signal
|
402 |
|
|
case set_tx_start is
|
403 |
|
|
when SET => tx_start_reg <= '1';
|
404 |
|
|
when CLR => tx_start_reg <= '0';
|
405 |
|
|
when HOLD => tx_start_reg <= tx_start_reg;
|
406 |
|
|
end case;
|
407 |
|
|
|
408 |
|
|
-- set tx started signal
|
409 |
|
|
case set_tx_started is
|
410 |
|
|
when SET => tx_started_reg <= '1';
|
411 |
|
|
when CLR => tx_started_reg <= '0';
|
412 |
|
|
when HOLD => tx_started_reg <= tx_started_reg;
|
413 |
|
|
end case;
|
414 |
|
|
|
415 |
|
|
-- set tx finished signal
|
416 |
|
|
case set_tx_fin is
|
417 |
|
|
when SET => tx_fin_reg <= '1';
|
418 |
|
|
when CLR => tx_fin_reg <= '0';
|
419 |
|
|
when HOLD => tx_fin_reg <= tx_fin_reg;
|
420 |
|
|
end case;
|
421 |
10 |
pjf |
|
422 |
|
|
-- set do_second_tx
|
423 |
|
|
case set_second_tx is
|
424 |
|
|
when PRIME =>
|
425 |
|
|
prime_second_tx <= '1';
|
426 |
|
|
when DO =>
|
427 |
|
|
prime_second_tx <= '0';
|
428 |
|
|
do_second_tx <= '1';
|
429 |
|
|
when CLR =>
|
430 |
|
|
prime_second_tx <= '0';
|
431 |
|
|
do_second_tx <= '0';
|
432 |
|
|
when HOLD =>
|
433 |
|
|
prime_second_tx <= prime_second_tx;
|
434 |
|
|
do_second_tx <= do_second_tx;
|
435 |
|
|
end case;
|
436 |
2 |
pjf |
|
437 |
|
|
end if;
|
438 |
|
|
end if;
|
439 |
|
|
|
440 |
|
|
end process;
|
441 |
8 |
pjf |
|
442 |
2 |
pjf |
|
443 |
|
|
|
444 |
|
|
------------------------------------------------------------------------------
|
445 |
|
|
-- Instantiate the UDP layer
|
446 |
|
|
------------------------------------------------------------------------------
|
447 |
8 |
pjf |
UDP_block : UDP_Complete
|
448 |
|
|
generic map (
|
449 |
10 |
pjf |
ARP_TIMEOUT => 10 -- timeout in seconds
|
450 |
8 |
pjf |
)
|
451 |
|
|
PORT MAP (
|
452 |
2 |
pjf |
-- UDP interface
|
453 |
|
|
udp_tx_start => udp_tx_start_int,
|
454 |
|
|
udp_txi => udp_tx_int,
|
455 |
|
|
udp_tx_result => udp_tx_result_int,
|
456 |
|
|
udp_tx_data_out_ready=> udp_tx_data_out_ready_int,
|
457 |
|
|
udp_rx_start => udp_rx_start_int,
|
458 |
|
|
udp_rxo => udp_rx_int,
|
459 |
|
|
-- IP RX signals
|
460 |
|
|
ip_rx_hdr => ip_rx_hdr_int,
|
461 |
|
|
-- System interface
|
462 |
|
|
clk_in_p => clk_in_p,
|
463 |
|
|
clk_in_n => clk_in_n,
|
464 |
|
|
clk_out => clk_int,
|
465 |
|
|
reset => reset,
|
466 |
|
|
our_ip_address => our_ip,
|
467 |
|
|
our_mac_address => our_mac,
|
468 |
8 |
pjf |
control => control_int,
|
469 |
2 |
pjf |
-- status signals
|
470 |
|
|
arp_pkt_count => arp_pkt_count_int,
|
471 |
|
|
ip_pkt_count => ip_pkt_count_int,
|
472 |
|
|
-- GMII Interface
|
473 |
|
|
-----------------
|
474 |
|
|
phy_resetn => phy_resetn,
|
475 |
|
|
gmii_txd => gmii_txd,
|
476 |
|
|
gmii_tx_en => gmii_tx_en,
|
477 |
|
|
gmii_tx_er => gmii_tx_er,
|
478 |
|
|
gmii_tx_clk => gmii_tx_clk,
|
479 |
|
|
gmii_rxd => gmii_rxd,
|
480 |
|
|
gmii_rx_dv => gmii_rx_dv,
|
481 |
|
|
gmii_rx_er => gmii_rx_er,
|
482 |
|
|
gmii_rx_clk => gmii_rx_clk,
|
483 |
|
|
gmii_col => gmii_col,
|
484 |
|
|
gmii_crs => gmii_crs,
|
485 |
|
|
mii_tx_clk => mii_tx_clk
|
486 |
|
|
);
|
487 |
|
|
|
488 |
|
|
|
489 |
|
|
end Behavioral;
|
490 |
|
|
|