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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [ml605/] [xv6mac_straight.vhd] - Blame information for rev 33

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--------------------------------------------------------------------------------
2
-- Project    : low latency UDP
3
-- File       : xv6mac_straight
4
-- Version    : 0.0
5
-------------------------------------------------------------------------------
6
--
7
--
8
-- Description:  This is an adaptation of the Xilinx V6 MAC layer, but without the FIFOs
9
--
10
--
11
--
12
--    ---------------------------------------------------------------------
13
--    | EXAMPLE DESIGN WRAPPER                                            |
14
--    |           --------------------------------------------------------|
15
--    |           |FIFO BLOCK WRAPPER                                     |
16
--    |           |                                                       |
17
--    |           |                                                       |
18
--    |           |              -----------------------------------------|
19
--    |           |              | BLOCK LEVEL WRAPPER                    |
20
--    |           |              |    ---------------------               |
21
--    |           |              |    |   V6 EMAC CORE    |               |
22
--    |           |              |    |                   |               |
23
--    |           |              |    |                   |               |
24
--    |           |              |    |                   |               |
25
--    |           |              |    |                   |               |
26
--    |           |              |    |                   |               |
27
--    | |      |  |              |    |                   |  ---------    |
28
--    | |      |->|->----------->|--|--->| Tx            Tx  |--|       |--->|
29
--    | |      |  |              |    | AXI-S         PHY |  |       |    |
30
--    | |      |  |              |    | I/F           I/F |  |       |    |
31
--    | |      |  |              |    |                   |  | PHY   |    |
32
--    | |      |  |              |    |                   |  | I/F   |    |
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--    | |      |  |              |    |                   |  |       |    |
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--    | |      |  |              |    | Rx            Rx  |  |       |    |
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--    | |      |  |              |    | AX)-S         PHY |  |       |    |
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--    | |      |<-|<-------------|----| I/F           I/F |<-|       |<---|
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--    | |      |  |              |    |                   |  ---------    |
38
--    | --------  |              |    ---------------------               |
39
--    |           |              |                                        |
40
--    |           |              -----------------------------------------|
41
--    |           --------------------------------------------------------|
42
--    ---------------------------------------------------------------------
43
--
44
--------------------------------------------------------------------------------
45
 
46
library unisim;
47
use unisim.vcomponents.all;
48
 
49
library ieee;
50
use ieee.std_logic_1164.all;
51
use ieee.std_logic_unsigned.all;
52
use ieee.numeric_std.all;
53
 
54
entity xv6mac_straight is
55
    port (
56
                -- System controls
57
                ------------------
58
      glbl_rst                      : in  std_logic;                                    -- asynchronous reset
59
      mac_reset                         : in  std_logic;                                                        -- reset mac layer
60
      clk_in_p                                  : in  std_logic;                                        -- 200MHz clock input from board
61
      clk_in_n                                  : in  std_logic;
62
 
63
                -- MAC Transmitter (AXI-S) Interface
64
      ---------------------------------------------
65
      mac_tx_clock                              : out  std_logic;                                                       -- data sampled on rising edge
66
      mac_tx_tdata                              : in  std_logic_vector(7 downto 0);      -- data byte to tx
67
      mac_tx_tvalid                             : in  std_logic;                                                        -- tdata is valid
68
      mac_tx_tready                             : out std_logic;                                                        -- mac is ready to accept data
69
      mac_tx_tlast                              : in  std_logic;                                                        -- indicates last byte of frame
70
 
71
      -- MAC Receiver (AXI-S) Interface
72
      ------------------------------------------
73
      mac_rx_clock                              : out  std_logic;                                                       -- data valid on rising edge
74
      mac_rx_tdata                              : out std_logic_vector(7 downto 0);      -- data byte received
75
      mac_rx_tvalid                             : out std_logic;                                                        -- indicates tdata is valid
76
      mac_rx_tready                             : in  std_logic;                                                        -- tells mac that we are ready to take data
77
      mac_rx_tlast                              : out std_logic;                                                        -- indicates last byte of the trame
78
 
79
      -- GMII Interface
80
      -----------------     
81
      phy_resetn                                : out std_logic;
82
      gmii_txd                      : out std_logic_vector(7 downto 0);
83
      gmii_tx_en                    : out std_logic;
84
      gmii_tx_er                    : out std_logic;
85
      gmii_tx_clk                   : out std_logic;
86
      gmii_rxd                      : in  std_logic_vector(7 downto 0);
87
      gmii_rx_dv                    : in  std_logic;
88
      gmii_rx_er                    : in  std_logic;
89
      gmii_rx_clk                   : in  std_logic;
90
      gmii_col                      : in  std_logic;
91
      gmii_crs                      : in  std_logic;
92
      mii_tx_clk                    : in  std_logic
93
                );
94
end xv6mac_straight;
95
 
96
architecture wrapper of xv6mac_straight is
97
 
98
  ------------------------------------------------------------------------------
99
  -- Component declaration for the internal mac layer
100
  ------------------------------------------------------------------------------
101
  component mac_layer_v2_2_block
102
   port(
103
      gtx_clk                       : in std_logic;
104
 
105
      -- Receiver Interface
106
      ----------------------------
107
      rx_statistics_vector          : out std_logic_vector(27 downto 0);
108
      rx_statistics_valid           : out std_logic;
109
 
110
      rx_mac_aclk                   : out std_logic;
111
      rx_reset                      : out std_logic;
112
      rx_axis_mac_tdata             : out std_logic_vector(7 downto 0);
113
      rx_axis_mac_tvalid            : out std_logic;
114
      rx_axis_mac_tlast             : out std_logic;
115
      rx_axis_mac_tuser             : out std_logic;
116
 
117
      -- Transmitter Interface
118
      -------------------------------
119
      tx_ifg_delay                  : in std_logic_vector(7 downto 0);
120
      tx_statistics_vector          : out std_logic_vector(31 downto 0);
121
      tx_statistics_valid           : out std_logic;
122
 
123
      tx_reset                      : out std_logic;
124
      tx_axis_mac_tdata             : in std_logic_vector(7 downto 0);
125
      tx_axis_mac_tvalid            : in std_logic;
126
      tx_axis_mac_tlast             : in std_logic;
127
      tx_axis_mac_tuser             : in std_logic;
128
      tx_axis_mac_tready            : out std_logic;
129
      tx_collision                  : out std_logic;
130
      tx_retransmit                 : out std_logic;
131
 
132
      -- MAC Control Interface
133
      ------------------------
134
      pause_req                     : in std_logic;
135
      pause_val                     : in std_logic_vector(15 downto 0);
136
 
137
      -- Reference clock for IDELAYCTRL's
138
      refclk                        : in std_logic;
139
 
140
      -- GMII Interface
141
      -----------------
142
      gmii_txd                      : out std_logic_vector(7 downto 0);
143
      gmii_tx_en                    : out std_logic;
144
      gmii_tx_er                    : out std_logic;
145
      gmii_tx_clk                   : out std_logic;
146
      gmii_rxd                      : in std_logic_vector(7 downto 0);
147
      gmii_rx_dv                    : in std_logic;
148
      gmii_rx_er                    : in std_logic;
149
      gmii_rx_clk                   : in std_logic;
150
 
151
      -- asynchronous reset
152
      -----------------
153
      glbl_rstn                     : in std_logic;
154
      rx_axi_rstn                   : in std_logic;
155
      tx_axi_rstn                   : in std_logic
156
 
157
      );
158
  end component;
159
 
160
 
161
  ------------------------------------------------------------------------------
162
  -- Component Declaration for the Clock generator
163
  ------------------------------------------------------------------------------
164
 
165
   component clk_wiz_v2_2
166
   port (
167
      -- Clock in ports
168
      CLK_IN1_P                 : in  std_logic;
169
      CLK_IN1_N                 : in  std_logic;
170
      -- Clock out ports
171
      CLK_OUT1                  : out std_logic;
172
      CLK_OUT2                  : out std_logic;
173
      CLK_OUT3                  : out std_logic;
174
      -- Status and control signals
175
      RESET                     : in  std_logic;
176
      LOCKED                    : out std_logic
177
   );
178
   end component;
179
 
180
 
181
  ------------------------------------------------------------------------------
182
  -- Component declaration for the reset synchroniser
183
  ------------------------------------------------------------------------------
184
  component reset_sync_v2_2
185
  port (
186
     reset_in                   : in  std_logic;    -- Active high asynchronous reset
187
     enable                     : in  std_logic;
188
     clk                        : in  std_logic;    -- clock to be sync'ed to
189
     reset_out                  : out std_logic     -- "Synchronised" reset signal
190
  );
191
  end component;
192
 
193
  ------------------------------------------------------------------------------
194
  -- Component declaration for the synchroniser
195
  ------------------------------------------------------------------------------
196
  component sync_block_v2_2
197
  port (
198
     clk                        : in  std_logic;
199
     data_in                    : in  std_logic;
200
     data_out                   : out std_logic
201
  );
202
  end component;
203
 
204
   ------------------------------------------------------------------------------
205
   -- Constants used in this top level wrapper.
206
   ------------------------------------------------------------------------------
207
   constant BOARD_PHY_ADDR                  : std_logic_vector(7 downto 0)  := "00000111";
208
 
209
 
210
   ------------------------------------------------------------------------------
211
   -- internal signals used in this top level wrapper.
212
   ------------------------------------------------------------------------------
213
 
214
   -- example design clocks
215
   signal gtx_clk_bufg                      : std_logic;
216
   signal refclk_bufg                       : std_logic;
217
   signal rx_mac_aclk                       : std_logic;
218
 
219
        -- tx handshaking
220
        signal mac_tx_tready_int                                                : std_logic;
221
        signal tx_full_reg                                                              : std_logic;
222
        signal tx_full_val                                                              : std_logic;
223
        signal tx_data_reg                                                              : std_logic_vector(7 downto 0);
224
        signal tx_last_reg                                                              : std_logic;
225
        signal set_tx_reg                                                                       : std_logic;
226
 
227
   signal phy_resetn_int                    : std_logic;
228
 
229
   -- resets (and reset generation)
230
   signal local_chk_reset                   : std_logic;
231
   signal chk_reset_int                     : std_logic;
232
   signal chk_pre_resetn                    : std_logic := '0';
233
   signal chk_resetn                        : std_logic := '0';
234
   signal dcm_locked                        : std_logic;
235
 
236
   signal glbl_rst_int                      : std_logic;
237
   signal phy_reset_count                   : unsigned(5 downto 0);
238
   signal glbl_rst_intn                     : std_logic;
239
 
240
        -- pipeline register for RX signals
241
        signal rx_data_val                                                              : std_logic_vector(7 downto 0);
242
        signal rx_tvalid_val                                                            : std_logic;
243
        signal rx_tlast_val                                                             : std_logic;
244
        signal rx_data_reg                                                              : std_logic_vector(7 downto 0);
245
        signal rx_tvalid_reg                                                            : std_logic;
246
        signal rx_tlast_reg                                                             : std_logic;
247
 
248
  attribute keep : string;
249
  attribute keep of gtx_clk_bufg             : signal is "true";
250
  attribute keep of refclk_bufg              : signal is "true";
251
  attribute keep of mac_tx_tready_int        : signal is "true";
252
  attribute keep of tx_full_reg                 : signal is "true";
253
 
254
 
255
  ------------------------------------------------------------------------------
256
  -- Begin architecture
257
  ------------------------------------------------------------------------------
258
 
259
begin
260
 
261
        combinatorial: process (
262
                rx_data_reg, rx_tvalid_reg, rx_tlast_reg,
263
                mac_tx_tvalid, mac_tx_tready_int, tx_full_reg, tx_full_val, set_tx_reg
264
                )
265
        begin
266
                -- output followers
267
      mac_rx_tdata  <= rx_data_reg;
268
      mac_rx_tvalid <= rx_tvalid_reg;
269
      mac_rx_tlast  <= rx_tlast_reg;
270
                mac_tx_tready <= not (tx_full_reg and not mac_tx_tready_int);           -- if not full, we are ready to accept
271
 
272
                -- control defaults
273
                tx_full_val <= tx_full_reg;
274
                set_tx_reg <= '0';
275
 
276
                -- tx handshaking logic
277
                if mac_tx_tvalid = '1' then
278
                        tx_full_val <= '1';
279
                        set_tx_reg <= '1';
280
                elsif mac_tx_tready_int = '1' then
281
                        tx_full_val <= '0';
282
                end if;
283
 
284
        end process;
285
 
286
   sequential: process(gtx_clk_bufg)
287
   begin
288
                if rising_edge(gtx_clk_bufg) then
289
                        if chk_resetn = '0' then
290
                                -- reset state variables
291
                                rx_data_reg <= (others => '0');
292
                                rx_tvalid_reg <= '0';
293
                                rx_tlast_reg <= '0';
294
                                tx_full_reg <= '0';
295
                                tx_data_reg <= (others => '0');
296
                                tx_last_reg <= '0';
297
                        else
298
                                -- register rx data
299
                                rx_data_reg <= rx_data_val;
300
                                rx_tvalid_reg <= rx_tvalid_val;
301
                                rx_tlast_reg <= rx_tlast_val;
302
 
303
                                -- process tx tvalid and tready
304
                                tx_full_reg <= tx_full_val;
305
                                if set_tx_reg = '1' then
306
                                        tx_data_reg <= mac_tx_tdata;
307
                                        tx_last_reg <= mac_tx_tlast;
308
                                else
309
                                        tx_data_reg <= tx_data_reg;
310
                                        tx_last_reg <= tx_last_reg;
311
                                end if;
312
                        end if;
313
                end if;
314
        end process;
315
 
316
   ------------------------------------------------------------------------------
317
   -- Instantiate the Tri-Mode EMAC Block wrapper
318
   ------------------------------------------------------------------------------
319
   v6emac_block : mac_layer_v2_2_block
320
   port map(
321
      gtx_clk               => gtx_clk_bufg,
322
 
323
      -- Client Receiver Interface
324
      rx_statistics_vector  => open,
325
      rx_statistics_valid   => open,
326
 
327
      rx_mac_aclk           => open,
328
      rx_reset              => open,
329
      rx_axis_mac_tdata     => rx_data_val,
330
      rx_axis_mac_tvalid    => rx_tvalid_val,
331
      rx_axis_mac_tlast     => rx_tlast_val,
332
      rx_axis_mac_tuser     => open,
333
 
334
      -- Client Transmitter Interface
335
      tx_ifg_delay          => x"00",
336
      tx_statistics_vector  => open,
337
      tx_statistics_valid   => open,
338
 
339
      tx_reset              => open,
340
      tx_axis_mac_tdata     => tx_data_reg,
341
      tx_axis_mac_tvalid    => tx_full_reg,
342
      tx_axis_mac_tlast     => tx_last_reg,
343
      tx_axis_mac_tuser     => '0',
344
      tx_axis_mac_tready    => mac_tx_tready_int,
345
      tx_collision          => open,
346
      tx_retransmit         => open,
347
 
348
      -- Flow Control
349
      pause_req             => '0',
350
      pause_val             => x"0000",
351
 
352
      -- Reference clock for IDELAYCTRL's
353
      refclk                => refclk_bufg,
354
 
355
      -- GMII Interface
356
      gmii_txd              => gmii_txd,
357
      gmii_tx_en            => gmii_tx_en,
358
      gmii_tx_er            => gmii_tx_er,
359
      gmii_tx_clk           => gmii_tx_clk,
360
      gmii_rxd              => gmii_rxd,
361
      gmii_rx_dv            => gmii_rx_dv,
362
      gmii_rx_er            => gmii_rx_er,
363
      gmii_rx_clk           => gmii_rx_clk,
364
 
365
      -- asynchronous reset
366
      glbl_rstn             => chk_resetn,
367
      rx_axi_rstn           => '1',
368
      tx_axi_rstn           => '1'
369
   );
370
 
371
 
372
 
373
   ------------------------------------------------------------------------------
374
   -- Clock logic to generate required clocks from the 200MHz on board
375
   -- if 125MHz is available directly this can be removed
376
   ------------------------------------------------------------------------------
377
   clock_generator : clk_wiz_v2_2
378
   port map (
379
      -- Clock in ports
380
      CLK_IN1_P         => clk_in_p,
381
      CLK_IN1_N         => clk_in_n,
382
      -- Clock out ports
383
      CLK_OUT1          => gtx_clk_bufg,
384
      CLK_OUT2          => open,
385
      CLK_OUT3          => refclk_bufg,
386
      -- Status and control signals
387
      RESET             => glbl_rst,
388
      LOCKED            => dcm_locked
389
   );
390
 
391
   -----------------
392
   -- global reset
393
   glbl_reset_gen : reset_sync_v2_2
394
   port map (
395
      clk               => gtx_clk_bufg,
396
      enable            => dcm_locked,
397
      reset_in          => glbl_rst,
398
      reset_out         => glbl_rst_int
399
   );
400
 
401
   glbl_rst_intn <= not glbl_rst_int;
402
 
403
   -- generate the user side clocks
404
        mac_tx_clock <= gtx_clk_bufg;
405
        mac_rx_clock <= gtx_clk_bufg;
406
 
407
   ------------------------------------------------------------------------------
408
   -- Generate resets 
409
   ------------------------------------------------------------------------------
410
   -- in each case the async reset is first captured and then synchronised
411
 
412
 
413
  local_chk_reset <= glbl_rst or mac_reset;
414
 
415
  -----------------
416
  -- data check reset
417
   chk_reset_gen : reset_sync_v2_2
418
   port map (
419
       clk              => gtx_clk_bufg,
420
       enable           => dcm_locked,
421
       reset_in         => local_chk_reset,
422
       reset_out        => chk_reset_int
423
   );
424
 
425
   -- Create fully synchronous reset in the gtx clock domain.
426
   gen_chk_reset : process (gtx_clk_bufg)
427
   begin
428
     if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
429
       if chk_reset_int = '1' then
430
         chk_pre_resetn   <= '0';
431
         chk_resetn       <= '0';
432
       else
433
         chk_pre_resetn   <= '1';
434
         chk_resetn       <= chk_pre_resetn;
435
       end if;
436
     end if;
437
   end process gen_chk_reset;
438
 
439
 
440
   -----------------
441
   -- PHY reset
442
   -- the phy reset output (active low) needs to be held for at least 10x25MHZ cycles
443
   -- this is derived using the 125MHz available and a 6 bit counter
444
   gen_phy_reset : process (gtx_clk_bufg)
445
   begin
446
     if gtx_clk_bufg'event and gtx_clk_bufg = '1' then
447
       if glbl_rst_intn = '0' then
448
         phy_resetn_int       <= '0';
449
         phy_reset_count      <= (others => '0');
450
       else
451
          if phy_reset_count /= "111111" then
452
             phy_reset_count <= phy_reset_count + "000001";
453
          else
454
             phy_resetn_int   <= '1';
455
          end if;
456
       end if;
457
     end if;
458
   end process gen_phy_reset;
459
 
460
   phy_resetn <= phy_resetn_int;
461
 
462
 
463
end wrapper;

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