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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Test Bench Library                                         ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////  Modifications: Alfredo Luiz Foltran Fialho                 ////
////                 alfoltran@opencores.org                     ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/usb1_funct/////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: tests_lib.v,v 1.1 2004-05-10 19:23:26 alfoltran Exp $
//
//  $Date: 2004-05-10 19:23:26 $
//  $Revision: 1.1 $
//  $Author: alfoltran $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//               Revision 1.1  2002/09/25 06:10:10  rudi
//               Added Test Bench
//
//
//
//
//
//
//
 
 
task show_errors;
 
begin
 
$display("\n");
$display("     +--------------------+");
$display("     |  Total ERRORS: %0d   |", error_cnt);
$display("     +--------------------+");
 
end
endtask
 
task recv_packet;
output  [3:0]    pid;
output          size;
 
integer         del, size,n;
reg     [15:0]   crc16r;
reg     [7:0]    x,y;
 
begin
crc16r = 16'hffff;
utmi_recv_pack(size);
 
if (size != 1)
begin
for(n=1;n<size-2;n=n+1)
   begin
        y = txmem[n];
        x[7] = y[0];
        x[6] = y[1];
        x[5] = y[2];
        x[4] = y[3];
        x[3] = y[4];
        x[2] = y[5];
        x[1] = y[6];
        x[0] = y[7];
        crc16r = crc16(crc16r, x);
   end
 
y = crc16r[15:8];
x[7] = y[0];
x[6] = y[1];
x[5] = y[2];
x[4] = y[3];
x[3] = y[4];
x[2] = y[5];
x[1] = y[6];
x[0] = y[7];
crc16r[15:8] = ~x;
 
y = crc16r[7:0];
x[7] = y[0];
x[6] = y[1];
x[5] = y[2];
x[4] = y[3];
x[3] = y[4];
x[2] = y[5];
x[1] = y[6];
x[0] = y[7];
crc16r[7:0] = ~x;
 
if(crc16r !== {txmem[n], txmem[n+1]})
$display("ERROR: CRC Mismatch: Expected: %h, Got: %h%h (%t)",
                crc16r, txmem[n], txmem[n+1], $time);
 
for(n=0;n<size-3;n=n+1)
        buffer1[buffer1_last+n] = txmem[n+1];
buffer1_last = buffer1_last+n;
 
end
else    size = 3;
 
// Check PID
x = txmem[0];
 
if(x[7:4] !== ~x[3:0])
$display("ERROR: Pid Checksum mismatch: Top: %h Bottom: %h (%t)",
                x[7:4], x[3:0], $time);
pid = x[3:0];
size=size-3;
end
endtask
 
 
 
task send_token;
input   [6:0]    fa;
input   [3:0]    ep;
input   [3:0]    pid;
 
reg     [15:0]   tmp_data;
reg     [10:0]   x,y;
integer         len;
 
begin
 
tmp_data = {fa, ep, 5'h0};
if(pid == `USBF_T_PID_ACK)      len = 1;
else                            len = 3;
 
y = {fa, ep};
x[10] = y[4];
x[9] = y[5];
x[8] = y[6];
x[7] = y[7];
x[6] = y[8];
x[5] = y[9];
x[4] = y[10];
x[3] = y[0];
x[2] = y[1];
x[1] = y[2];
x[0] = y[3];
 
y[4:0]  = crc5( 5'h1f, x );
tmp_data[4:0]  = ~y[4:0];
tmp_data[15:5] = x;
txmem[0] = {~pid, pid};  // PID
txmem[1] = {    tmp_data[8],tmp_data[9],tmp_data[10],tmp_data[11],
                tmp_data[12],tmp_data[13],tmp_data[14],tmp_data[15]};
txmem[2] = {    tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],
                tmp_data[4],tmp_data[5],tmp_data[6],tmp_data[7]};
utmi_send_pack(len);
end
endtask
 
 
task send_sof;
input   [10:0]   frmn;
 
reg     [15:0]   tmp_data;
reg     [10:0]   x,y;
begin
 
y = frmn;
x[10] = y[0];
x[9] = y[1];
x[8] = y[2];
x[7] = y[3];
x[6] = y[4];
x[5] = y[5];
x[4] = y[6];
x[3] = y[7];
x[2] = y[8];
x[1] = y[9];
x[0] = y[10];
 
tmp_data[15:5] = x;
y[4:0]  = crc5( 5'h1f, x );
tmp_data[4:0]  = ~y[4:0];
txmem[0] = {~`USBF_T_PID_SOF, `USBF_T_PID_SOF};  // PID
txmem[1] = {    tmp_data[8],tmp_data[9],tmp_data[10],tmp_data[11],
                tmp_data[12],tmp_data[13],tmp_data[14],tmp_data[15]};
txmem[2] = {    tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],
                tmp_data[4],tmp_data[5],tmp_data[6],tmp_data[7]};
txmem[1] =      frmn[7:0];
txmem[2] = {    tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],
                tmp_data[4], frmn[10:8] };
utmi_send_pack(3);
end
endtask
 
 
function [4:0] crc5;
input   [4:0]    crc_in;
input   [10:0]   din;
reg     [4:0]    crc_out;
 
begin
 
crc5[0] =        din[10] ^ din[9] ^ din[6] ^ din[5] ^ din[3] ^
                din[0] ^ crc_in[0] ^ crc_in[3] ^ crc_in[4];
crc5[1] =       din[10] ^ din[7] ^ din[6] ^ din[4] ^ din[1] ^
                crc_in[0] ^ crc_in[1] ^ crc_in[4];
crc5[2] =       din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[6] ^
                din[3] ^ din[2] ^ din[0] ^ crc_in[0] ^ crc_in[1] ^
                crc_in[2] ^ crc_in[3] ^ crc_in[4];
crc5[3] =       din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[4] ^ din[3] ^
                din[1] ^ crc_in[1] ^ crc_in[2] ^ crc_in[3] ^ crc_in[4];
crc5[4] =       din[10] ^ din[9] ^ din[8] ^ din[5] ^ din[4] ^ din[2] ^
                crc_in[2] ^ crc_in[3] ^ crc_in[4];
end
endfunction
 
 
task send_data;
input   [3:0]    pid;
input           len;
input           mode;
integer         n, len, mode, delay;
reg     [15:0]   crc16r;
reg     [7:0]    x,y;
 
begin
txmem[0] = {~pid, pid};  // PID
crc16r = 16'hffff;
for(n=0;n<len;n=n+1)
   begin
        if(mode==1)     y = buffer1[buffer1_last+n];
        else            y = n;
        x[7] = y[0];
        x[6] = y[1];
        x[5] = y[2];
        x[4] = y[3];
        x[3] = y[4];
        x[2] = y[5];
        x[1] = y[6];
        x[0] = y[7];
        txmem[n+1] = y;
        crc16r = crc16(crc16r, x);
   end
 
buffer1_last = buffer1_last + n;
y = crc16r[15:8];
x[7] = y[0];
x[6] = y[1];
x[5] = y[2];
x[4] = y[3];
x[3] = y[4];
x[2] = y[5];
x[1] = y[6];
x[0] = y[7];
txmem[n+1] = ~x;
 
y = crc16r[7:0];
x[7] = y[0];
x[6] = y[1];
x[5] = y[2];
x[4] = y[3];
x[3] = y[4];
x[2] = y[5];
x[1] = y[6];
x[0] = y[7];
txmem[n+2] = ~x;
utmi_send_pack(len+3);
end
endtask
 
 
function [15:0] crc16;
input   [15:0]   crc_in;
input   [7:0]    din;
reg     [15:0]   crc_out;
 
begin
crc_out[0] =     din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^
                din[2] ^ din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9] ^
                crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^
                crc_in[14] ^ crc_in[15];
crc_out[1] =    din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^
                din[1] ^ crc_in[9] ^ crc_in[10] ^ crc_in[11] ^
                crc_in[12] ^ crc_in[13] ^ crc_in[14] ^ crc_in[15];
crc_out[2] =    din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9];
crc_out[3] =    din[2] ^ din[1] ^ crc_in[9] ^ crc_in[10];
crc_out[4] =    din[3] ^ din[2] ^ crc_in[10] ^ crc_in[11];
crc_out[5] =    din[4] ^ din[3] ^ crc_in[11] ^ crc_in[12];
crc_out[6] =    din[5] ^ din[4] ^ crc_in[12] ^ crc_in[13];
crc_out[7] =    din[6] ^ din[5] ^ crc_in[13] ^ crc_in[14];
crc_out[8] =    din[7] ^ din[6] ^ crc_in[0] ^ crc_in[14] ^ crc_in[15];
crc_out[9] =    din[7] ^ crc_in[1] ^ crc_in[15];
crc_out[10] =   crc_in[2];
crc_out[11] =   crc_in[3];
crc_out[12] =   crc_in[4];
crc_out[13] =   crc_in[5];
crc_out[14] =   crc_in[6];
crc_out[15] =   din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^
                din[1] ^ din[0] ^ crc_in[7] ^ crc_in[8] ^ crc_in[9] ^
                crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^
                crc_in[14] ^ crc_in[15];
crc16 = crc_out;
end
endfunction
 
///////////////////////////////////////////////////////////////////
//
// UTMI Low level Tasks
//
 
task utmi_send_pack;
input   size;
integer n,size;
 
begin
@(posedge clk);
#1;
tb_tx_valid = 1'b1;
for(n=0;n<size;n=n+1)
   begin
        tb_txdata = txmem[n];
        @(posedge clk);
        #2;
        while(!tb_tx_ready)     @(posedge clk);
        #1;
   end
tb_tx_valid = 1'b0;
@(posedge clk);
end
endtask
 
task utmi_recv_pack;
output  size;
integer size;
 
begin
size = 0;
while(!tb_rx_active)    @(posedge clk);
while(tb_rx_active)
   begin
        #1;
        while(!tb_rx_valid & tb_rx_active)      @(posedge clk);
 
        if(tb_rx_valid & tb_rx_active)
           begin
                txmem[size] = tb_rxdata;
                size = size + 1;
           end
        @(posedge clk);
   end
end
endtask
 

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[/] [usb11/] [trunk/] [bench/] [verilog/] [tests_lib.v] - Blame information for rev 13

Line No.	Rev	Author	Line
1	2	alfoltran	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Test Bench Library ////`
4			`//// ////`
5			`//// ////`
6			`//// Author: Rudolf Usselmann ////`
7			`//// rudi@asics.ws ////`
8			`//// ////`
9			`//// Modifications: Alfredo Luiz Foltran Fialho ////`
10			`//// alfoltran@opencores.org ////`
11			`//// ////`
12			`//// Downloaded from: http://www.opencores.org/cores/usb1_funct/////`
13			`//// ////`
14			`/////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2000-2002 Rudolf Usselmann ////`
17			`//// www.asics.ws ////`
18			`//// rudi@asics.ws ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer.////`
24			`//// ////`
25			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
26			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
27			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
28			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
29			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
30			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
31			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
32			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
33			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
34			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
35			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
36			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
37			`//// POSSIBILITY OF SUCH DAMAGE. ////`
38			`//// ////`
39			`/////////////////////////////////////////////////////////////////////`
40
41			`// CVS Log`
42			`//`
43			`// $Id: tests_lib.v,v 1.1 2004-05-10 19:23:26 alfoltran Exp $`
44			`//`
45			`// $Date: 2004-05-10 19:23:26 $`
46			`// $Revision: 1.1 $`
47			`// $Author: alfoltran $`
48			`// $Locker: $`
49			`// $State: Exp $`
50			`//`
51			`// Change History:`
52			`// $Log: not supported by cvs2svn $`
53			`// Revision 1.1 2002/09/25 06:10:10 rudi`
54			`// Added Test Bench`
55			`//`
56			`//`
57			`//`
58			`//`
59			`//`
60			`//`
61			`//`
62
63
64			`task show_errors;`
65
66			`begin`
67
68			`$display("\n");`
69			`$display(" +--------------------+");`
70			`$display(" \| Total ERRORS: %0d \|", error_cnt);`
71			`$display(" +--------------------+");`
72
73			`end`
74			`endtask`
75
76			`task recv_packet;`
77			`output [3:0] pid;`
78			`output size;`
79
80			`integer del, size,n;`
81			`reg [15:0] crc16r;`
82			`reg [7:0] x,y;`
83
84			`begin`
85			`crc16r = 16'hffff;`
86			`utmi_recv_pack(size);`
87
88			`if (size != 1)`
89			`begin`
90			`for(n=1;n<size-2;n=n+1)`
91			`begin`
92			`y = txmem[n];`
93			`x[7] = y[0];`
94			`x[6] = y[1];`
95			`x[5] = y[2];`
96			`x[4] = y[3];`
97			`x[3] = y[4];`
98			`x[2] = y[5];`
99			`x[1] = y[6];`
100			`x[0] = y[7];`
101			`crc16r = crc16(crc16r, x);`
102			`end`
103
104			`y = crc16r[15:8];`
105			`x[7] = y[0];`
106			`x[6] = y[1];`
107			`x[5] = y[2];`
108			`x[4] = y[3];`
109			`x[3] = y[4];`
110			`x[2] = y[5];`
111			`x[1] = y[6];`
112			`x[0] = y[7];`
113			`crc16r[15:8] = ~x;`
114
115			`y = crc16r[7:0];`
116			`x[7] = y[0];`
117			`x[6] = y[1];`
118			`x[5] = y[2];`
119			`x[4] = y[3];`
120			`x[3] = y[4];`
121			`x[2] = y[5];`
122			`x[1] = y[6];`
123			`x[0] = y[7];`
124			`crc16r[7:0] = ~x;`
125
126			`if(crc16r !== {txmem[n], txmem[n+1]})`
127			`$display("ERROR: CRC Mismatch: Expected: %h, Got: %h%h (%t)",`
128			`crc16r, txmem[n], txmem[n+1], $time);`
129
130			`for(n=0;n<size-3;n=n+1)`
131			`buffer1[buffer1_last+n] = txmem[n+1];`
132			`buffer1_last = buffer1_last+n;`
133
134			`end`
135			`else size = 3;`
136
137			`// Check PID`
138			`x = txmem[0];`
139
140			`if(x[7:4] !== ~x[3:0])`
141			`$display("ERROR: Pid Checksum mismatch: Top: %h Bottom: %h (%t)",`
142			`x[7:4], x[3:0], $time);`
143			`pid = x[3:0];`
144			`size=size-3;`
145			`end`
146			`endtask`
147
148
149
150			`task send_token;`
151			`input [6:0] fa;`
152			`input [3:0] ep;`
153			`input [3:0] pid;`
154
155			`reg [15:0] tmp_data;`
156			`reg [10:0] x,y;`
157			`integer len;`
158
159			`begin`
160
161			`tmp_data = {fa, ep, 5'h0};`
162			if(pid == `USBF_T_PID_ACK) len = 1;
163			`else len = 3;`
164
165			`y = {fa, ep};`
166			`x[10] = y[4];`
167			`x[9] = y[5];`
168			`x[8] = y[6];`
169			`x[7] = y[7];`
170			`x[6] = y[8];`
171			`x[5] = y[9];`
172			`x[4] = y[10];`
173			`x[3] = y[0];`
174			`x[2] = y[1];`
175			`x[1] = y[2];`
176			`x[0] = y[3];`
177
178			`y[4:0] = crc5( 5'h1f, x );`
179			`tmp_data[4:0] = ~y[4:0];`
180			`tmp_data[15:5] = x;`
181			`txmem[0] = {~pid, pid}; // PID`
182			`txmem[1] = { tmp_data[8],tmp_data[9],tmp_data[10],tmp_data[11],`
183			`tmp_data[12],tmp_data[13],tmp_data[14],tmp_data[15]};`
184			`txmem[2] = { tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],`
185			`tmp_data[4],tmp_data[5],tmp_data[6],tmp_data[7]};`
186			`utmi_send_pack(len);`
187			`end`
188			`endtask`
189
190
191			`task send_sof;`
192			`input [10:0] frmn;`
193
194			`reg [15:0] tmp_data;`
195			`reg [10:0] x,y;`
196			`begin`
197
198			`y = frmn;`
199			`x[10] = y[0];`
200			`x[9] = y[1];`
201			`x[8] = y[2];`
202			`x[7] = y[3];`
203			`x[6] = y[4];`
204			`x[5] = y[5];`
205			`x[4] = y[6];`
206			`x[3] = y[7];`
207			`x[2] = y[8];`
208			`x[1] = y[9];`
209			`x[0] = y[10];`
210
211			`tmp_data[15:5] = x;`
212			`y[4:0] = crc5( 5'h1f, x );`
213			`tmp_data[4:0] = ~y[4:0];`
214			txmem[0] = {~`USBF_T_PID_SOF, `USBF_T_PID_SOF}; // PID
215			`txmem[1] = { tmp_data[8],tmp_data[9],tmp_data[10],tmp_data[11],`
216			`tmp_data[12],tmp_data[13],tmp_data[14],tmp_data[15]};`
217			`txmem[2] = { tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],`
218			`tmp_data[4],tmp_data[5],tmp_data[6],tmp_data[7]};`
219			`txmem[1] = frmn[7:0];`
220			`txmem[2] = { tmp_data[0],tmp_data[1],tmp_data[2],tmp_data[3],`
221			`tmp_data[4], frmn[10:8] };`
222			`utmi_send_pack(3);`
223			`end`
224			`endtask`
225
226
227			`function [4:0] crc5;`
228			`input [4:0] crc_in;`
229			`input [10:0] din;`
230			`reg [4:0] crc_out;`
231
232			`begin`
233
234			`crc5[0] = din[10] ^ din[9] ^ din[6] ^ din[5] ^ din[3] ^`
235			`din[0] ^ crc_in[0] ^ crc_in[3] ^ crc_in[4];`
236			`crc5[1] = din[10] ^ din[7] ^ din[6] ^ din[4] ^ din[1] ^`
237			`crc_in[0] ^ crc_in[1] ^ crc_in[4];`
238			`crc5[2] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[6] ^`
239			`din[3] ^ din[2] ^ din[0] ^ crc_in[0] ^ crc_in[1] ^`
240			`crc_in[2] ^ crc_in[3] ^ crc_in[4];`
241			`crc5[3] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[4] ^ din[3] ^`
242			`din[1] ^ crc_in[1] ^ crc_in[2] ^ crc_in[3] ^ crc_in[4];`
243			`crc5[4] = din[10] ^ din[9] ^ din[8] ^ din[5] ^ din[4] ^ din[2] ^`
244			`crc_in[2] ^ crc_in[3] ^ crc_in[4];`
245			`end`
246			`endfunction`
247
248
249			`task send_data;`
250			`input [3:0] pid;`
251			`input len;`
252			`input mode;`
253			`integer n, len, mode, delay;`
254			`reg [15:0] crc16r;`
255			`reg [7:0] x,y;`
256
257			`begin`
258			`txmem[0] = {~pid, pid}; // PID`
259			`crc16r = 16'hffff;`
260			`for(n=0;n<len;n=n+1)`
261			`begin`
262			`if(mode==1) y = buffer1[buffer1_last+n];`
263			`else y = n;`
264			`x[7] = y[0];`
265			`x[6] = y[1];`
266			`x[5] = y[2];`
267			`x[4] = y[3];`
268			`x[3] = y[4];`
269			`x[2] = y[5];`
270			`x[1] = y[6];`
271			`x[0] = y[7];`
272			`txmem[n+1] = y;`
273			`crc16r = crc16(crc16r, x);`
274			`end`
275
276			`buffer1_last = buffer1_last + n;`
277			`y = crc16r[15:8];`
278			`x[7] = y[0];`
279			`x[6] = y[1];`
280			`x[5] = y[2];`
281			`x[4] = y[3];`
282			`x[3] = y[4];`
283			`x[2] = y[5];`
284			`x[1] = y[6];`
285			`x[0] = y[7];`
286			`txmem[n+1] = ~x;`
287
288			`y = crc16r[7:0];`
289			`x[7] = y[0];`
290			`x[6] = y[1];`
291			`x[5] = y[2];`
292			`x[4] = y[3];`
293			`x[3] = y[4];`
294			`x[2] = y[5];`
295			`x[1] = y[6];`
296			`x[0] = y[7];`
297			`txmem[n+2] = ~x;`
298			`utmi_send_pack(len+3);`
299			`end`
300			`endtask`
301
302
303			`function [15:0] crc16;`
304			`input [15:0] crc_in;`
305			`input [7:0] din;`
306			`reg [15:0] crc_out;`
307
308			`begin`
309			`crc_out[0] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^`
310			`din[2] ^ din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9] ^`
311			`crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^`
312			`crc_in[14] ^ crc_in[15];`
313			`crc_out[1] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^`
314			`din[1] ^ crc_in[9] ^ crc_in[10] ^ crc_in[11] ^`
315			`crc_in[12] ^ crc_in[13] ^ crc_in[14] ^ crc_in[15];`
316			`crc_out[2] = din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9];`
317			`crc_out[3] = din[2] ^ din[1] ^ crc_in[9] ^ crc_in[10];`
318			`crc_out[4] = din[3] ^ din[2] ^ crc_in[10] ^ crc_in[11];`
319			`crc_out[5] = din[4] ^ din[3] ^ crc_in[11] ^ crc_in[12];`
320			`crc_out[6] = din[5] ^ din[4] ^ crc_in[12] ^ crc_in[13];`
321			`crc_out[7] = din[6] ^ din[5] ^ crc_in[13] ^ crc_in[14];`
322			`crc_out[8] = din[7] ^ din[6] ^ crc_in[0] ^ crc_in[14] ^ crc_in[15];`
323			`crc_out[9] = din[7] ^ crc_in[1] ^ crc_in[15];`
324			`crc_out[10] = crc_in[2];`
325			`crc_out[11] = crc_in[3];`
326			`crc_out[12] = crc_in[4];`
327			`crc_out[13] = crc_in[5];`
328			`crc_out[14] = crc_in[6];`
329			`crc_out[15] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^`
330			`din[1] ^ din[0] ^ crc_in[7] ^ crc_in[8] ^ crc_in[9] ^`
331			`crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^`
332			`crc_in[14] ^ crc_in[15];`
333			`crc16 = crc_out;`
334			`end`
335			`endfunction`
336
337			`///////////////////////////////////////////////////////////////////`
338			`//`
339			`// UTMI Low level Tasks`
340			`//`
341
342			`task utmi_send_pack;`
343			`input size;`
344			`integer n,size;`
345
346			`begin`
347			`@(posedge clk);`
348			`#1;`
349			`tb_tx_valid = 1'b1;`
350			`for(n=0;n<size;n=n+1)`
351			`begin`
352			`tb_txdata = txmem[n];`
353			`@(posedge clk);`
354			`#2;`
355			`while(!tb_tx_ready) @(posedge clk);`
356			`#1;`
357			`end`
358			`tb_tx_valid = 1'b0;`
359			`@(posedge clk);`
360			`end`
361			`endtask`
362
363			`task utmi_recv_pack;`
364			`output size;`
365			`integer size;`
366
367			`begin`
368			`size = 0;`
369			`while(!tb_rx_active) @(posedge clk);`
370			`while(tb_rx_active)`
371			`begin`
372			`#1;`
373			`while(!tb_rx_valid & tb_rx_active) @(posedge clk);`
374
375			`if(tb_rx_valid & tb_rx_active)`
376			`begin`
377			`txmem[size] = tb_rxdata;`
378			`size = size + 1;`
379			`end`
380			`@(posedge clk);`
381			`end`
382			`end`
383			`endtask`
384